[linux-2.6-block.git] / arch / powerpc / boot / dts / sbc8641d.dts

/*
 * SBC8641D Device Tree Source
 *
 * Copyright 2008 Wind River Systems Inc.
 *
 * Paul Gortmaker (see MAINTAINERS for contact information)
 *
 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "SBC8641D";
	compatible = "wind,sbc8641";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8641@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;		// L1
			i-cache-size = <32768>;		// L1
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
		PowerPC,8641@1 {
			device_type = "cpu";
			reg = <1>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512M at 0x0
	};

	localbus@f8005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8641-localbus", "simple-bus";
		reg = <0xf8005000 0x1000>;
		interrupts = <19 2>;
		interrupt-parent = <&mpic>;

		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash
			  1 0 0xf0000000 0x00010000	// 64KB EEPROM
			  2 0 0xf1000000 0x00100000	// EPLD (1MB)
			  3 0 0xe0000000 0x04000000	// 64MB LB SDRAM (CS3)
			  4 0 0xe4000000 0x04000000	// 64MB LB SDRAM (CS4)
			  6 0 0xf4000000 0x00100000	// LCD display (1MB)
			  7 0 0xe8000000 0x04000000>;	// 64MB OneNAND

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x01000000>;
			bank-width = <2>;
			device-width = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			partition@0 {
				label = "dtb";
				reg = <0x00000000 0x00100000>;
				read-only;
			};
			partition@300000 {
				label = "kernel";
				reg = <0x00100000 0x00400000>;
				read-only;
			};
			partition@400000 {
				label = "fs";
				reg = <0x00500000 0x00a00000>;
			};
			partition@700000 {
				label = "firmware";
				reg = <0x00f00000 0x00100000>;
				read-only;
			};
		};

		epld@2,0 {
			compatible = "wrs,epld-localbus";
			#address-cells = <2>;
			#size-cells = <1>;
			reg = <2 0 0x100000>;
			ranges = <0 0 5 0 1	// User switches
				  1 0 5 1 1	// Board ID/Rev
				  3 0 5 3 1>;	// LEDs
		};
	};

	soc@f8000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x00000000 0xf8000000 0x00100000>;
		bus-frequency = <0>;

		mcm-law@0 {
			compatible = "fsl,mcm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <10>;
		};

		mcm@1000 {
			compatible = "fsl,mpc8641-mcm", "fsl,mcm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8641-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8641-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8641-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8641-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30  2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@1f {
					interrupt-parent = <&mpic>;
					interrupts = <10 1>;
					reg = <0x1f>;
				};
				phy1: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <10 1>;
					reg = <0>;
				};
				phy2: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <10 1>;
					reg = <1>;
				};
				phy3: ethernet-phy@2 {
					interrupt-parent = <&mpic>;
					interrupts = <10 1>;
					reg = <2>;
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet2: ethernet@26000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <2>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x26000 0x1000>;
			ranges = <0x0 0x26000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <31 2 32 2 33 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi2>;
			phy-handle = <&phy2>;
			phy-connection-type = "rgmii-id";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi2: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet3: ethernet@27000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <3>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x27000 0x1000>;
			ranges = <0x0 0x27000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <37 2 38 2 39 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi3>;
			phy-handle = <&phy3>;
			phy-connection-type = "rgmii-id";

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi3: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <28 2>;
			interrupt-parent = <&mpic>;
		};

		mpic: pic@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
			big-endian;
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8641-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};
	};

	pci0: pcie@f8008000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xf8008000 0x1000>;
		bus-range = <0x0 0xff>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xff00 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0x0000 0 0 1 &mpic 0 1
			0x0000 0 0 2 &mpic 1 1
			0x0000 0 0 3 &mpic 2 1
			0x0000 0 0 4 &mpic 3 1
			>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0x80000000
				  0x02000000 0x0 0x80000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
		};

	};

	pci1: pcie@f8009000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xf8009000 0x1000>;
		bus-range = <0 0xff>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0x0000 0 0 1 &mpic 4 1
			0x0000 0 0 2 &mpic 5 1
			0x0000 0 0 3 &mpic 6 1
			0x0000 0 0 4 &mpic 7 1
			>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
		};
	};
};
Commit	Line	Data
81fad217 PG	1	/*
	2	* SBC8641D Device Tree Source
	3	*
	4	* Copyright 2008 Wind River Systems Inc.
	5	*
	6	* Paul Gortmaker (see MAINTAINERS for contact information)
	7	*
	8	* Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	/dts-v1/;
	17
	18	/ {
	19	model = "SBC8641D";
	20	compatible = "wind,sbc8641";
	21	#address-cells = <1>;
	22	#size-cells = <1>;
	23
	24	aliases {
	25	ethernet0 = &enet0;
	26	ethernet1 = &enet1;
	27	ethernet2 = &enet2;
	28	ethernet3 = &enet3;
	29	serial0 = &serial0;
	30	serial1 = &serial1;
	31	pci0 = &pci0;
	32	pci1 = &pci1;
	33	};
	34
	35	cpus {
	36	#address-cells = <1>;
	37	#size-cells = <0>;
	38
	39	PowerPC,8641@0 {
	40	device_type = "cpu";
	41	reg = <0>;
	42	d-cache-line-size = <32>;
	43	i-cache-line-size = <32>;
	44	d-cache-size = <32768>; // L1
	45	i-cache-size = <32768>; // L1
	46	timebase-frequency = <0>; // From uboot
	47	bus-frequency = <0>; // From uboot
	48	clock-frequency = <0>; // From uboot
	49	};
	50	PowerPC,8641@1 {
	51	device_type = "cpu";
	52	reg = <1>;
	53	d-cache-line-size = <32>;
	54	i-cache-line-size = <32>;
	55	d-cache-size = <32768>;
	56	i-cache-size = <32768>;
	57	timebase-frequency = <0>; // From uboot
	58	bus-frequency = <0>; // From uboot
	59	clock-frequency = <0>; // From uboot
	60	};
	61	};
	62
	63	memory {
	64	device_type = "memory";
65	reg = <0x00000000 0x20000000>; // 512M at 0x0
66	};
67
68	localbus@f8005000 {
69	#address-cells = <2>;
70	#size-cells = <1>;
71	compatible = "fsl,mpc8641-localbus", "simple-bus";
72	reg = <0xf8005000 0x1000>;
73	interrupts = <19 2>;
74	interrupt-parent = <&mpic>;
75
76	ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
77	1 0 0xf0000000 0x00010000 // 64KB EEPROM
78	2 0 0xf1000000 0x00100000 // EPLD (1MB)
79	3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
80	4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
81	6 0 0xf4000000 0x00100000 // LCD display (1MB)
82	7 0 0xe8000000 0x04000000>; // 64MB OneNAND
83
84	flash@0,0 {
85	compatible = "cfi-flash";
86	reg = <0 0 0x01000000>;
87	bank-width = <2>;
88	device-width = <2>;
89	#address-cells = <1>;
90	#size-cells = <1>;
91	partition@0 {
92	label = "dtb";
93	reg = <0x00000000 0x00100000>;
94	read-only;
95	};
96	partition@300000 {
97	label = "kernel";
98	reg = <0x00100000 0x00400000>;
99	read-only;
100	};
101	partition@400000 {
102	label = "fs";
103	reg = <0x00500000 0x00a00000>;
104	};
105	partition@700000 {
106	label = "firmware";
107	reg = <0x00f00000 0x00100000>;
108	read-only;
109	};
110	};
111
112	epld@2,0 {
113	compatible = "wrs,epld-localbus";
114	#address-cells = <2>;
115	#size-cells = <1>;
116	reg = <2 0 0x100000>;
117	ranges = <0 0 5 0 1 // User switches
118	1 0 5 1 1 // Board ID/Rev
119	3 0 5 3 1>; // LEDs
120	};
121	};
122
123	soc@f8000000 {
124	#address-cells = <1>;
125	#size-cells = <1>;
126	device_type = "soc";
127	compatible = "simple-bus";
128	ranges = <0x00000000 0xf8000000 0x00100000>;
81fad217 PG	129	bus-frequency = <0>;
81fad217 PG	130
da385780 KG	131	mcm-law@0 {
	132	compatible = "fsl,mcm-law";
	133	reg = <0x0 0x1000>;
	134	fsl,num-laws = <10>;
	135	};
	136
	137	mcm@1000 {
	138	compatible = "fsl,mpc8641-mcm", "fsl,mcm";
	139	reg = <0x1000 0x1000>;
	140	interrupts = <17 2>;
	141	interrupt-parent = <&mpic>;
	142	};
	143
81fad217 PG	144	i2c@3000 {
	145	#address-cells = <1>;
	146	#size-cells = <0>;
	147	cell-index = <0>;
	148	compatible = "fsl-i2c";
	149	reg = <0x3000 0x100>;
	150	interrupts = <43 2>;
	151	interrupt-parent = <&mpic>;
	152	dfsrr;
	153	};
	154
	155	i2c@3100 {
	156	#address-cells = <1>;
	157	#size-cells = <0>;
	158	cell-index = <1>;
	159	compatible = "fsl-i2c";
	160	reg = <0x3100 0x100>;
	161	interrupts = <43 2>;
	162	interrupt-parent = <&mpic>;
	163	dfsrr;
	164	};
	165
dee80553 KG	166	dma@21300 {
	167	#address-cells = <1>;
	168	#size-cells = <1>;
	169	compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
	170	reg = <0x21300 0x4>;
	171	ranges = <0x0 0x21100 0x200>;
	172	cell-index = <0>;
	173	dma-channel@0 {
	174	compatible = "fsl,mpc8641-dma-channel",
	175	"fsl,eloplus-dma-channel";
	176	reg = <0x0 0x80>;
	177	cell-index = <0>;
	178	interrupt-parent = <&mpic>;
	179	interrupts = <20 2>;
	180	};
	181	dma-channel@80 {
	182	compatible = "fsl,mpc8641-dma-channel",
	183	"fsl,eloplus-dma-channel";
	184	reg = <0x80 0x80>;
	185	cell-index = <1>;
	186	interrupt-parent = <&mpic>;
	187	interrupts = <21 2>;
	188	};
	189	dma-channel@100 {
	190	compatible = "fsl,mpc8641-dma-channel",
	191	"fsl,eloplus-dma-channel";
	192	reg = <0x100 0x80>;
	193	cell-index = <2>;
	194	interrupt-parent = <&mpic>;
	195	interrupts = <22 2>;
	196	};
	197	dma-channel@180 {
	198	compatible = "fsl,mpc8641-dma-channel",
	199	"fsl,eloplus-dma-channel";
	200	reg = <0x180 0x80>;
	201	cell-index = <3>;
	202	interrupt-parent = <&mpic>;
	203	interrupts = <23 2>;
	204	};
	205	};
	206
81fad217	207	enet0: ethernet@24000 {
d8bc55fb AV	208	#address-cells = <1>;
d8bc55fb AV	209	#size-cells = <1>;
81fad217 PG	210	cell-index = <0>;
	211	device_type = "network";
	212	model = "TSEC";
	213	compatible = "gianfar";
	214	reg = <0x24000 0x1000>;
d8bc55fb	215	ranges = <0x0 0x24000 0x1000>;
81fad217 PG	216	local-mac-address = [ 00 00 00 00 00 00 ];
	217	interrupts = <29 2 30 2 34 2>;
	218	interrupt-parent = <&mpic>;
b31a1d8b	219	tbi-handle = <&tbi0>;
81fad217 PG	220	phy-handle = <&phy0>;
81fad217 PG	221	phy-connection-type = "rgmii-id";
d8bc55fb AV	222
	223	mdio@520 {
	224	#address-cells = <1>;
	225	#size-cells = <0>;
	226	compatible = "fsl,gianfar-mdio";
	227	reg = <0x520 0x20>;
	228
	229	phy0: ethernet-phy@1f {
	230	interrupt-parent = <&mpic>;
	231	interrupts = <10 1>;
	232	reg = <0x1f>;
d8bc55fb AV	233	};
	234	phy1: ethernet-phy@0 {
	235	interrupt-parent = <&mpic>;
	236	interrupts = <10 1>;
	237	reg = <0>;
d8bc55fb AV	238	};
	239	phy2: ethernet-phy@1 {
	240	interrupt-parent = <&mpic>;
	241	interrupts = <10 1>;
	242	reg = <1>;
d8bc55fb AV	243	};
	244	phy3: ethernet-phy@2 {
	245	interrupt-parent = <&mpic>;
	246	interrupts = <10 1>;
	247	reg = <2>;
d8bc55fb AV	248	};
	249	tbi0: tbi-phy@11 {
	250	reg = <0x11>;
	251	device_type = "tbi-phy";
	252	};
	253	};
81fad217 PG	254	};
	255
	256	enet1: ethernet@25000 {
d8bc55fb AV	257	#address-cells = <1>;
d8bc55fb AV	258	#size-cells = <1>;
81fad217 PG	259	cell-index = <1>;
	260	device_type = "network";
	261	model = "TSEC";
	262	compatible = "gianfar";
	263	reg = <0x25000 0x1000>;
d8bc55fb	264	ranges = <0x0 0x25000 0x1000>;
81fad217 PG	265	local-mac-address = [ 00 00 00 00 00 00 ];
	266	interrupts = <35 2 36 2 40 2>;
	267	interrupt-parent = <&mpic>;
b31a1d8b	268	tbi-handle = <&tbi1>;
81fad217 PG	269	phy-handle = <&phy1>;
81fad217 PG	270	phy-connection-type = "rgmii-id";
d8bc55fb AV	271
	272	mdio@520 {
	273	#address-cells = <1>;
	274	#size-cells = <0>;
	275	compatible = "fsl,gianfar-tbi";
	276	reg = <0x520 0x20>;
	277
	278	tbi1: tbi-phy@11 {
	279	reg = <0x11>;
	280	device_type = "tbi-phy";
	281	};
	282	};
81fad217 PG	283	};
	284
	285	enet2: ethernet@26000 {
d8bc55fb AV	286	#address-cells = <1>;
d8bc55fb AV	287	#size-cells = <1>;
81fad217 PG	288	cell-index = <2>;
	289	device_type = "network";
	290	model = "TSEC";
	291	compatible = "gianfar";
	292	reg = <0x26000 0x1000>;
d8bc55fb	293	ranges = <0x0 0x26000 0x1000>;
81fad217 PG	294	local-mac-address = [ 00 00 00 00 00 00 ];
	295	interrupts = <31 2 32 2 33 2>;
	296	interrupt-parent = <&mpic>;
b31a1d8b	297	tbi-handle = <&tbi2>;
81fad217 PG	298	phy-handle = <&phy2>;
81fad217 PG	299	phy-connection-type = "rgmii-id";
d8bc55fb AV	300
	301	mdio@520 {
	302	#address-cells = <1>;
	303	#size-cells = <0>;
	304	compatible = "fsl,gianfar-tbi";
	305	reg = <0x520 0x20>;
	306
	307	tbi2: tbi-phy@11 {
	308	reg = <0x11>;
	309	device_type = "tbi-phy";
	310	};
	311	};
81fad217 PG	312	};
	313
	314	enet3: ethernet@27000 {
d8bc55fb AV	315	#address-cells = <1>;
d8bc55fb AV	316	#size-cells = <1>;
81fad217 PG	317	cell-index = <3>;
	318	device_type = "network";
	319	model = "TSEC";
	320	compatible = "gianfar";
	321	reg = <0x27000 0x1000>;
d8bc55fb	322	ranges = <0x0 0x27000 0x1000>;
81fad217 PG	323	local-mac-address = [ 00 00 00 00 00 00 ];
	324	interrupts = <37 2 38 2 39 2>;
	325	interrupt-parent = <&mpic>;
b31a1d8b	326	tbi-handle = <&tbi3>;
81fad217 PG	327	phy-handle = <&phy3>;
81fad217 PG	328	phy-connection-type = "rgmii-id";
d8bc55fb AV	329
	330	mdio@520 {
	331	#address-cells = <1>;
	332	#size-cells = <0>;
	333	compatible = "fsl,gianfar-tbi";
	334	reg = <0x520 0x20>;
	335
	336	tbi3: tbi-phy@11 {
	337	reg = <0x11>;
	338	device_type = "tbi-phy";
	339	};
	340	};
81fad217 PG	341	};
	342
	343	serial0: serial@4500 {
	344	cell-index = <0>;
	345	device_type = "serial";
f706bed1	346	compatible = "fsl,ns16550", "ns16550";
81fad217 PG	347	reg = <0x4500 0x100>;
	348	clock-frequency = <0>;
	349	interrupts = <42 2>;
	350	interrupt-parent = <&mpic>;
	351	};
	352
	353	serial1: serial@4600 {
	354	cell-index = <1>;
	355	device_type = "serial";
f706bed1	356	compatible = "fsl,ns16550", "ns16550";
81fad217 PG	357	reg = <0x4600 0x100>;
	358	clock-frequency = <0>;
	359	interrupts = <28 2>;
	360	interrupt-parent = <&mpic>;
	361	};
	362
	363	mpic: pic@40000 {
	364	clock-frequency = <0>;
	365	interrupt-controller;
	366	#address-cells = <0>;
	367	#interrupt-cells = <2>;
	368	reg = <0x40000 0x40000>;
	369	compatible = "chrp,open-pic";
	370	device_type = "open-pic";
	371	big-endian;
	372	};
	373
	374	global-utilities@e0000 {
	375	compatible = "fsl,mpc8641-guts";
	376	reg = <0xe0000 0x1000>;
	377	fsl,has-rstcr;
	378	};
	379	};
	380
	381	pci0: pcie@f8008000 {
81fad217 PG	382	compatible = "fsl,mpc8641-pcie";
	383	device_type = "pci";
	384	#interrupt-cells = <1>;
	385	#size-cells = <2>;
	386	#address-cells = <3>;
	387	reg = <0xf8008000 0x1000>;
	388	bus-range = <0x0 0xff>;
	389	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	390	0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
	391	clock-frequency = <33333333>;
	392	interrupt-parent = <&mpic>;
	393	interrupts = <24 2>;
	394	interrupt-map-mask = <0xff00 0 0 7>;
	395	interrupt-map = <
	396	/* IDSEL 0x0 */
	397	0x0000 0 0 1 &mpic 0 1
	398	0x0000 0 0 2 &mpic 1 1
	399	0x0000 0 0 3 &mpic 2 1
	400	0x0000 0 0 4 &mpic 3 1
	401	>;
	402
	403	pcie@0 {
	404	reg = <0 0 0 0 0>;
	405	#size-cells = <2>;
	406	#address-cells = <3>;
	407	device_type = "pci";
	408	ranges = <0x02000000 0x0 0x80000000
	409	0x02000000 0x0 0x80000000
	410	0x0 0x20000000
	411
	412	0x01000000 0x0 0x00000000
	413	0x01000000 0x0 0x00000000
	414	0x0 0x00100000>;
	415	};
	416
	417	};
	418
	419	pci1: pcie@f8009000 {
81fad217 PG	420	compatible = "fsl,mpc8641-pcie";
	421	device_type = "pci";
	422	#interrupt-cells = <1>;
	423	#size-cells = <2>;
	424	#address-cells = <3>;
	425	reg = <0xf8009000 0x1000>;
	426	bus-range = <0 0xff>;
	427	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
	428	0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
	429	clock-frequency = <33333333>;
	430	interrupt-parent = <&mpic>;
	431	interrupts = <25 2>;
	432	interrupt-map-mask = <0xf800 0 0 7>;
	433	interrupt-map = <
	434	/* IDSEL 0x0 */
	435	0x0000 0 0 1 &mpic 4 1
	436	0x0000 0 0 2 &mpic 5 1
	437	0x0000 0 0 3 &mpic 6 1
	438	0x0000 0 0 4 &mpic 7 1
	439	>;
	440
	441	pcie@0 {
	442	reg = <0 0 0 0 0>;
	443	#size-cells = <2>;
	444	#address-cells = <3>;
	445	device_type = "pci";
	446	ranges = <0x02000000 0x0 0xa0000000
	447	0x02000000 0x0 0xa0000000
	448	0x0 0x20000000
	449
	450	0x01000000 0x0 0x00000000
	451	0x01000000 0x0 0x00000000
	452	0x0 0x00100000>;
	453	};
	454	};
	455	};