[linux-2.6-block.git] / arch / powerpc / boot / dts / mpc8610_hpcd.dts

/*
 * MPC8610 HPCD Device Tree Source
 *
 * Copyright 2007-2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under the terms of the GNU General Public License Version 2 as published
 * by the Free Software Foundation.
 */

/dts-v1/;

/ {
	model = "MPC8610HPCD";
	compatible = "fsl,MPC8610HPCD";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8610@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;		// L1
			i-cache-size = <32768>;		// L1
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512M at 0x0
	};

	board-control@e8000000 {
		compatible = "fsl,fpga-pixis";
		reg = <0xe8000000 32>;		// pixis at 0xe8000000
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		compatible = "fsl,mpc8610-immr", "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x1000>;
		bus-frequency = <0>;

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			cs4270:codec@4f {
				compatible = "cirrus,cs4270";
				reg = <0x4f>;
				/* MCLK source is a stand-alone oscillator */
				clock-frequency = <12288000>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		display@2c000 {
			compatible = "fsl,diu";
			reg = <0x2c000 100>;
			interrupts = <72 2>;
			interrupt-parent = <&mpic>;
		};

		mpic: interrupt-controller@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
			big-endian;
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8610-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		i2s@16000 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <0>;
			reg = <0x16000 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <62 2>;
			fsl,mode = "i2s-slave";
			codec-handle = <&cs4270>;
		};

		ssi@16100 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <1>;
			reg = <0x16100 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <63 2>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <0>;
			reg = <0x21300 0x4>; /* DMA general status register */
			ranges = <0x0 0x21100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		dma@c300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
			cell-index = <1>;
			reg = <0xc300 0x4>; /* DMA general status register */
			ranges = <0x0 0xc100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <60 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <61 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <62 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <63 2>;
			};
		};

	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		compatible = "fsl,mpc8610-pci";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 */
			0x8800 0 0 1 &mpic 4 1
			0x8800 0 0 2 &mpic 5 1
			0x8800 0 0 3 &mpic 6 1
			0x8800 0 0 4 &mpic 7 1

			/* IDSEL 0x12 */
			0x9000 0 0 1 &mpic 5 1
			0x9000 0 0 2 &mpic 6 1
			0x9000 0 0 3 &mpic 7 1
			0x9000 0 0 4 &mpic 4 1
			>;
	};

	pci1: pcie@e000a000 {
		cell-index = <1>;
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		bus-range = <1 3>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x1b */
			0xd800 0 0 1 &mpic 2 1

			/* IDSEL 0x1c*/
			0xe000 0 0 1 &mpic 1 1
			0xe000 0 0 2 &mpic 1 1
			0xe000 0 0 3 &mpic 1 1
			0xe000 0 0 4 &mpic 1 1

			/* IDSEL 0x1f */
			0xf800 0 0 1 &mpic 3 0
			0xf800 0 0 2 &mpic 0 1
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x10000000
				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0xa0000000
					  0x02000000 0x0 0xa0000000
					  0x0 0x10000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00100000>;
			};
		};
	};

	pci2: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8641-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
			  0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0x0000 0 0 1 &mpic 4 1
				 0x0000 0 0 2 &mpic 5 1
				 0x0000 0 0 3 &mpic 6 1
				 0x0000 0 0 4 &mpic 7 1>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		clock-frequency = <33333333>;
	};
};
Commit	Line	Data
53f3945a XX	1	/*
	2	* MPC8610 HPCD Device Tree Source
	3	*
c7d24a2d	4	* Copyright 2007-2008 Freescale Semiconductor Inc.
53f3945a XX	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License Version 2 as published
	8	* by the Free Software Foundation.
	9	*/
	10
6e050d4e	11	/dts-v1/;
53f3945a XX	12
	13	/ {
	14	model = "MPC8610HPCD";
	15	compatible = "fsl,MPC8610HPCD";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	serial0 = &serial0;
	21	serial1 = &serial1;
	22	pci0 = &pci0;
	23	pci1 = &pci1;
e598477a	24	pci2 = &pci2;
ea082fa9 KG	25	};
ea082fa9 KG	26
53f3945a XX	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
	31	PowerPC,8610@0 {
	32	device_type = "cpu";
	33	reg = <0>;
6e050d4e JL	34	d-cache-line-size = <32>;
	35	i-cache-line-size = <32>;
	36	d-cache-size = <32768>; // L1
	37	i-cache-size = <32768>; // L1
	38	timebase-frequency = <0>; // From uboot
53f3945a XX	39	bus-frequency = <0>; // From uboot
	40	clock-frequency = <0>; // From uboot
	41	};
	42	};
	43
	44	memory {
	45	device_type = "memory";
6e050d4e	46	reg = <0x00000000 0x20000000>; // 512M at 0x0
53f3945a XX	47	};
53f3945a XX	48
9b53a9e2 YS	49	board-control@e8000000 {
	50	compatible = "fsl,fpga-pixis";
	51	reg = <0xe8000000 32>; // pixis at 0xe8000000
	52	};
	53
53f3945a XX	54	soc@e0000000 {
	55	#address-cells = <1>;
	56	#size-cells = <1>;
	57	#interrupt-cells = <2>;
	58	device_type = "soc";
c7d24a2d	59	compatible = "fsl,mpc8610-immr", "simple-bus";
6e050d4e JL	60	ranges = <0x0 0xe0000000 0x00100000>;
6e050d4e JL	61	reg = <0xe0000000 0x1000>;
53f3945a XX	62	bus-frequency = <0>;
	63
	64	i2c@3000 {
53f3945a XX	65	#address-cells = <1>;
53f3945a XX	66	#size-cells = <0>;
ec9686c4 KG	67	cell-index = <0>;
ec9686c4 KG	68	compatible = "fsl-i2c";
6e050d4e JL	69	reg = <0x3000 0x100>;
6e050d4e JL	70	interrupts = <43 2>;
53f3945a XX	71	interrupt-parent = <&mpic>;
53f3945a XX	72	dfsrr;
c7d24a2d	73
6e050d4e	74	cs4270:codec@4f {
c7d24a2d	75	compatible = "cirrus,cs4270";
6e050d4e	76	reg = <0x4f>;
c7d24a2d	77	/* MCLK source is a stand-alone oscillator */
6e050d4e JL	78	clock-frequency = <12288000>;
6e050d4e JL	79	};
53f3945a XX	80	};
	81
	82	i2c@3100 {
53f3945a XX	83	#address-cells = <1>;
53f3945a XX	84	#size-cells = <0>;
ec9686c4 KG	85	cell-index = <1>;
ec9686c4 KG	86	compatible = "fsl-i2c";
6e050d4e JL	87	reg = <0x3100 0x100>;
6e050d4e JL	88	interrupts = <43 2>;
53f3945a XX	89	interrupt-parent = <&mpic>;
	90	dfsrr;
	91	};
	92
ea082fa9 KG	93	serial0: serial@4500 {
ea082fa9 KG	94	cell-index = <0>;
53f3945a XX	95	device_type = "serial";
53f3945a XX	96	compatible = "ns16550";
6e050d4e	97	reg = <0x4500 0x100>;
53f3945a	98	clock-frequency = <0>;
6e050d4e	99	interrupts = <42 2>;
53f3945a XX	100	interrupt-parent = <&mpic>;
	101	};
	102
ea082fa9 KG	103	serial1: serial@4600 {
ea082fa9 KG	104	cell-index = <1>;
53f3945a XX	105	device_type = "serial";
53f3945a XX	106	compatible = "ns16550";
6e050d4e	107	reg = <0x4600 0x100>;
53f3945a	108	clock-frequency = <0>;
aecb2b6e	109	interrupts = <42 2>;
53f3945a XX	110	interrupt-parent = <&mpic>;
	111	};
	112
9b53a9e2 YS	113	display@2c000 {
	114	compatible = "fsl,diu";
	115	reg = <0x2c000 100>;
	116	interrupts = <72 2>;
	117	interrupt-parent = <&mpic>;
	118	};
	119
53f3945a XX	120	mpic: interrupt-controller@40000 {
	121	clock-frequency = <0>;
	122	interrupt-controller;
	123	#address-cells = <0>;
	124	#interrupt-cells = <2>;
6e050d4e	125	reg = <0x40000 0x40000>;
53f3945a XX	126	compatible = "chrp,open-pic";
	127	device_type = "open-pic";
	128	big-endian;
	129	};
	130
	131	global-utilities@e0000 {
	132	compatible = "fsl,mpc8610-guts";
6e050d4e	133	reg = <0xe0000 0x1000>;
53f3945a XX	134	fsl,has-rstcr;
53f3945a XX	135	};
c7d24a2d TT	136
	137	i2s@16000 {
	138	compatible = "fsl,mpc8610-ssi";
	139	cell-index = <0>;
6e050d4e	140	reg = <0x16000 0x100>;
c7d24a2d	141	interrupt-parent = <&mpic>;
6e050d4e	142	interrupts = <62 2>;
c7d24a2d TT	143	fsl,mode = "i2s-slave";
	144	codec-handle = <&cs4270>;
	145	};
	146
	147	ssi@16100 {
	148	compatible = "fsl,mpc8610-ssi";
	149	cell-index = <1>;
6e050d4e	150	reg = <0x16100 0x100>;
c7d24a2d	151	interrupt-parent = <&mpic>;
6e050d4e	152	interrupts = <63 2>;
c7d24a2d TT	153	};
c7d24a2d TT	154
6e050d4e JL	155	dma@21300 {
	156	#address-cells = <1>;
	157	#size-cells = <1>;
	158	compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
	159	cell-index = <0>;
	160	reg = <0x21300 0x4>; /* DMA general status register */
	161	ranges = <0x0 0x21100 0x200>;
c7d24a2d	162
6e050d4e	163	dma-channel@0 {
c7d24a2d TT	164	compatible = "fsl,mpc8610-dma-channel",
	165	"fsl,eloplus-dma-channel";
	166	cell-index = <0>;
6e050d4e	167	reg = <0x0 0x80>;
c7d24a2d	168	interrupt-parent = <&mpic>;
6e050d4e JL	169	interrupts = <20 2>;
	170	};
	171	dma-channel@1 {
c7d24a2d TT	172	compatible = "fsl,mpc8610-dma-channel",
	173	"fsl,eloplus-dma-channel";
	174	cell-index = <1>;
6e050d4e	175	reg = <0x80 0x80>;
c7d24a2d	176	interrupt-parent = <&mpic>;
6e050d4e JL	177	interrupts = <21 2>;
	178	};
	179	dma-channel@2 {
c7d24a2d TT	180	compatible = "fsl,mpc8610-dma-channel",
	181	"fsl,eloplus-dma-channel";
	182	cell-index = <2>;
6e050d4e	183	reg = <0x100 0x80>;
c7d24a2d	184	interrupt-parent = <&mpic>;
6e050d4e JL	185	interrupts = <22 2>;
	186	};
	187	dma-channel@3 {
c7d24a2d TT	188	compatible = "fsl,mpc8610-dma-channel",
	189	"fsl,eloplus-dma-channel";
	190	cell-index = <3>;
6e050d4e	191	reg = <0x180 0x80>;
c7d24a2d	192	interrupt-parent = <&mpic>;
6e050d4e JL	193	interrupts = <23 2>;
	194	};
	195	};
c7d24a2d	196
6e050d4e JL	197	dma@c300 {
	198	#address-cells = <1>;
	199	#size-cells = <1>;
	200	compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
	201	cell-index = <1>;
	202	reg = <0xc300 0x4>; /* DMA general status register */
	203	ranges = <0x0 0xc100 0x200>;
c7d24a2d	204
6e050d4e	205	dma-channel@0 {
c7d24a2d TT	206	compatible = "fsl,mpc8610-dma-channel",
	207	"fsl,mpc8540-dma-channel";
	208	cell-index = <0>;
6e050d4e	209	reg = <0x0 0x80>;
c7d24a2d	210	interrupt-parent = <&mpic>;
6e050d4e JL	211	interrupts = <60 2>;
	212	};
	213	dma-channel@1 {
c7d24a2d TT	214	compatible = "fsl,mpc8610-dma-channel",
	215	"fsl,mpc8540-dma-channel";
	216	cell-index = <1>;
6e050d4e	217	reg = <0x80 0x80>;
c7d24a2d	218	interrupt-parent = <&mpic>;
6e050d4e JL	219	interrupts = <61 2>;
	220	};
	221	dma-channel@2 {
c7d24a2d TT	222	compatible = "fsl,mpc8610-dma-channel",
	223	"fsl,mpc8540-dma-channel";
	224	cell-index = <2>;
6e050d4e	225	reg = <0x100 0x80>;
c7d24a2d	226	interrupt-parent = <&mpic>;
6e050d4e JL	227	interrupts = <62 2>;
	228	};
	229	dma-channel@3 {
c7d24a2d TT	230	compatible = "fsl,mpc8610-dma-channel",
	231	"fsl,mpc8540-dma-channel";
	232	cell-index = <3>;
6e050d4e	233	reg = <0x180 0x80>;
c7d24a2d	234	interrupt-parent = <&mpic>;
6e050d4e JL	235	interrupts = <63 2>;
	236	};
	237	};
c7d24a2d	238
53f3945a XX	239	};
53f3945a XX	240
ea082fa9 KG	241	pci0: pci@e0008000 {
ea082fa9 KG	242	cell-index = <0>;
53f3945a XX	243	compatible = "fsl,mpc8610-pci";
	244	device_type = "pci";
	245	#interrupt-cells = <1>;
	246	#size-cells = <2>;
	247	#address-cells = <3>;
6e050d4e	248	reg = <0xe0008000 0x1000>;
53f3945a	249	bus-range = <0 0>;
6e050d4e JL	250	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	251	0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
	252	clock-frequency = <33333333>;
53f3945a	253	interrupt-parent = <&mpic>;
6e050d4e JL	254	interrupts = <24 2>;
6e050d4e JL	255	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	256	interrupt-map = <
53f3945a XX	257	/* IDSEL 0x11 */
6e050d4e JL	258	0x8800 0 0 1 &mpic 4 1
	259	0x8800 0 0 2 &mpic 5 1
	260	0x8800 0 0 3 &mpic 6 1
	261	0x8800 0 0 4 &mpic 7 1
53f3945a XX	262
53f3945a XX	263	/* IDSEL 0x12 */
6e050d4e JL	264	0x9000 0 0 1 &mpic 5 1
	265	0x9000 0 0 2 &mpic 6 1
	266	0x9000 0 0 3 &mpic 7 1
	267	0x9000 0 0 4 &mpic 4 1
53f3945a XX	268	>;
	269	};
	270
ea082fa9 KG	271	pci1: pcie@e000a000 {
ea082fa9 KG	272	cell-index = <1>;
53f3945a XX	273	compatible = "fsl,mpc8641-pcie";
	274	device_type = "pci";
	275	#interrupt-cells = <1>;
	276	#size-cells = <2>;
	277	#address-cells = <3>;
6e050d4e	278	reg = <0xe000a000 0x1000>;
53f3945a	279	bus-range = <1 3>;
6e050d4e JL	280	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	281	0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
	282	clock-frequency = <33333333>;
53f3945a	283	interrupt-parent = <&mpic>;
6e050d4e JL	284	interrupts = <26 2>;
6e050d4e JL	285	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	286
	287	interrupt-map = <
	288	/* IDSEL 0x1b */
6e050d4e	289	0xd800 0 0 1 &mpic 2 1
53f3945a XX	290
53f3945a XX	291	/* IDSEL 0x1c*/
6e050d4e JL	292	0xe000 0 0 1 &mpic 1 1
	293	0xe000 0 0 2 &mpic 1 1
	294	0xe000 0 0 3 &mpic 1 1
	295	0xe000 0 0 4 &mpic 1 1
53f3945a XX	296
53f3945a XX	297	/* IDSEL 0x1f */
6e050d4e JL	298	0xf800 0 0 1 &mpic 3 0
6e050d4e JL	299	0xf800 0 0 2 &mpic 0 1
53f3945a XX	300	>;
	301
	302	pcie@0 {
	303	reg = <0 0 0 0 0>;
	304	#size-cells = <2>;
	305	#address-cells = <3>;
	306	device_type = "pci";
6e050d4e JL	307	ranges = <0x02000000 0x0 0xa0000000
	308	0x02000000 0x0 0xa0000000
	309	0x0 0x10000000
	310	0x01000000 0x0 0x00000000
	311	0x01000000 0x0 0x00000000
	312	0x0 0x00100000>;
53f3945a XX	313	uli1575@0 {
	314	reg = <0 0 0 0 0>;
	315	#size-cells = <2>;
	316	#address-cells = <3>;
6e050d4e JL	317	ranges = <0x02000000 0x0 0xa0000000
	318	0x02000000 0x0 0xa0000000
	319	0x0 0x10000000
	320	0x01000000 0x0 0x00000000
	321	0x01000000 0x0 0x00000000
	322	0x0 0x00100000>;
53f3945a XX	323	};
	324	};
	325	};
e598477a AV	326
	327	pci2: pcie@e0009000 {
	328	#address-cells = <3>;
	329	#size-cells = <2>;
	330	#interrupt-cells = <1>;
	331	device_type = "pci";
	332	compatible = "fsl,mpc8641-pcie";
	333	reg = <0xe0009000 0x00001000>;
	334	ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
	335	0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
	336	bus-range = <0 255>;
	337	interrupt-map-mask = <0xf800 0 0 7>;
	338	interrupt-map = <0x0000 0 0 1 &mpic 4 1
	339	0x0000 0 0 2 &mpic 5 1
	340	0x0000 0 0 3 &mpic 6 1
	341	0x0000 0 0 4 &mpic 7 1>;
	342	interrupt-parent = <&mpic>;
	343	interrupts = <25 2>;
	344	clock-frequency = <33333333>;
	345	};
53f3945a	346	};