[linux-2.6-block.git] / arch / powerpc / boot / dts / mpc8610_hpcd.dts

/*
 * MPC8610 HPCD Device Tree Source
 *
 * Copyright 2007-2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under the terms of the GNU General Public License Version 2 as published
 * by the Free Software Foundation.
 */

/dts-v1/;

/ {
	model = "MPC8610HPCD";
	compatible = "fsl,MPC8610HPCD";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8610@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;		// L1
			i-cache-size = <32768>;		// L1
			sleep = <&pmc 0x00008000 0	// core
				 &pmc 0x00004000 0>;	// timebase
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512M at 0x0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <19 2>;
		interrupt-parent = <&mpic>;
		ranges = <0 0 0xf8000000 0x08000000
			  1 0 0xf0000000 0x08000000
			  2 0 0xe8400000 0x00008000
			  4 0 0xe8440000 0x00008000
			  5 0 0xe8480000 0x00008000
			  6 0 0xe84c0000 0x00008000
			  3 0 0xe8000000 0x00000020>;
		sleep = <&pmc 0x08000000 0>;

		flash@0,0 {
			compatible = "cfi-flash";
			reg = <0 0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;
		};

		flash@1,0 {
			compatible = "cfi-flash";
			reg = <1 0 0x8000000>;
			bank-width = <2>;
			device-width = <1>;
		};

		flash@2,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <2 0 0x8000>;
		};

		flash@4,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <4 0 0x8000>;
		};

		flash@5,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <5 0 0x8000>;
		};

		flash@6,0 {
			compatible = "fsl,mpc8610-fcm-nand",
				     "fsl,elbc-fcm-nand";
			reg = <6 0 0x8000>;
		};

		board-control@3,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,fpga-pixis";
			reg = <3 0 0x20>;
			ranges = <0 3 0 0x20>;
			interrupt-parent = <&mpic>;
			interrupts = <8 8>;

			sdcsr_pio: gpio-controller@a {
				#gpio-cells = <2>;
				compatible = "fsl,fpga-pixis-gpio-bank";
				reg = <0xa 1>;
				gpio-controller;
			};
		};
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		compatible = "fsl,mpc8610-immr", "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		bus-frequency = <0>;

		mcm-law@0 {
			compatible = "fsl,mcm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <10>;
		};

		mcm@1000 {
			compatible = "fsl,mpc8610-mcm", "fsl,mcm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			cs4270:codec@4f {
				compatible = "cirrus,cs4270";
				reg = <0x4f>;
				/* MCLK source is a stand-alone oscillator */
				clock-frequency = <12288000>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			sleep = <&pmc 0x00000004 0>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
			sleep = <&pmc 0x00000002 0>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
			sleep = <&pmc 0x00000008 0>;
		};

		spi@7000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc8610-spi", "fsl,spi";
			reg = <0x7000 0x40>;
			cell-index = <0>;
			interrupts = <59 2>;
			interrupt-parent = <&mpic>;
			mode = "cpu";
			gpios = <&sdcsr_pio 7 0>;
			sleep = <&pmc 0x00000800 0>;

			mmc-slot@0 {
				compatible = "fsl,mpc8610hpcd-mmc-slot",
					     "mmc-spi-slot";
				reg = <0>;
				gpios = <&sdcsr_pio 0 1   /* nCD */
					 &sdcsr_pio 1 0>; /*  WP */
				voltage-ranges = <3300 3300>;
				spi-max-frequency = <50000000>;
			};
		};

		display@2c000 {
			compatible = "fsl,diu";
			reg = <0x2c000 100>;
			interrupts = <72 2>;
			interrupt-parent = <&mpic>;
			sleep = <&pmc 0x04000000 0>;
		};

		mpic: interrupt-controller@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		msi@41600 {
			compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
			reg = <0x41600 0x80>;
			msi-available-ranges = <0 0x100>;
			interrupts = <
				0xe0 0
				0xe1 0
				0xe2 0
				0xe3 0
				0xe4 0
				0xe5 0
				0xe6 0
				0xe7 0>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-guts";
			reg = <0xe0000 0x1000>;
			ranges = <0 0xe0000 0x1000>;
			fsl,has-rstcr;

			pmc: power@70 {
				compatible = "fsl,mpc8610-pmc",
					     "fsl,mpc8641d-pmc";
				reg = <0x70 0x20>;
			};
		};

		wdt@e4000 {
			compatible = "fsl,mpc8610-wdt";
			reg = <0xe4000 0x100>;
		};

		ssi@16000 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <0>;
			reg = <0x16000 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <62 2>;
			fsl,mode = "i2s-slave";
			codec-handle = <&cs4270>;
			fsl,playback-dma = <&dma00>;
			fsl,capture-dma = <&dma01>;
			fsl,fifo-depth = <8>;
			sleep = <&pmc 0 0x08000000>;
		};

		ssi@16100 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <1>;
			reg = <0x16100 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <63 2>;
			fsl,fifo-depth = <8>;
			sleep = <&pmc 0 0x04000000>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <0>;
			reg = <0x21300 0x4>; /* DMA general status register */
			ranges = <0x0 0x21100 0x200>;
			sleep = <&pmc 0x00000400 0>;

			dma00: dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,ssi-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma01: dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,ssi-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		dma@c300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <1>;
			reg = <0xc300 0x4>; /* DMA general status register */
			ranges = <0x0 0xc100 0x200>;
			sleep = <&pmc 0x00000200 0>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <76 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <77 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <78 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <79 2>;
			};
		};

	};

	pci0: pci@e0008000 {
		compatible = "fsl,mpc8610-pci";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
		sleep = <&pmc 0x80000000 0>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 */
			0x8800 0 0 1 &mpic 4 1
			0x8800 0 0 2 &mpic 5 1
			0x8800 0 0 3 &mpic 6 1
			0x8800 0 0 4 &mpic 7 1

			/* IDSEL 0x12 */
			0x9000 0 0 1 &mpic 5 1
			0x9000 0 0 2 &mpic 6 1
			0x9000 0 0 3 &mpic 7 1
			0x9000 0 0 4 &mpic 4 1
			>;
	};

	pci1: pcie@e000a000 {
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		bus-range = <1 3>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
		sleep = <&pmc 0x40000000 0>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x1b */
			0xd800 0 0 1 &mpic 2 1

			/* IDSEL 0x1c*/
			0xe000 0 0 1 &mpic 1 1
			0xe000 0 0 2 &mpic 1 1
			0xe000 0 0 3 &mpic 1 1
			0xe000 0 0 4 &mpic 1 1

			/* IDSEL 0x1f */
			0xf800 0 0 1 &mpic 3 2
			0xf800 0 0 2 &mpic 0 1
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x10000000
				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0xa0000000
					  0x02000000 0x0 0xa0000000
					  0x0 0x10000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00100000>;

				isa@1e {
					device_type = "isa";
					#size-cells = <1>;
					#address-cells = <2>;
					reg = <0xf000 0 0 0 0>;
					ranges = <1 0 0x01000000 0 0
						  0x00001000>;

					rtc@70 {
						compatible = "pnpPNP,b00";
						reg = <1 0x70 2>;
					};
				};
			};
		};
	};

	pci2: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8641-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
			  0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0x0000 0 0 1 &mpic 4 1
				 0x0000 0 0 2 &mpic 5 1
				 0x0000 0 0 3 &mpic 6 1
				 0x0000 0 0 4 &mpic 7 1>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		sleep = <&pmc 0x20000000 0>;
		clock-frequency = <33333333>;
	};
};
Commit	Line	Data
53f3945a XX	1	/*
	2	* MPC8610 HPCD Device Tree Source
	3	*
c7d24a2d	4	* Copyright 2007-2008 Freescale Semiconductor Inc.
53f3945a XX	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License Version 2 as published
	8	* by the Free Software Foundation.
	9	*/
	10
6e050d4e	11	/dts-v1/;
53f3945a XX	12
	13	/ {
	14	model = "MPC8610HPCD";
	15	compatible = "fsl,MPC8610HPCD";
	16	#address-cells = <1>;
	17	#size-cells = <1>;
	18
ea082fa9 KG	19	aliases {
	20	serial0 = &serial0;
	21	serial1 = &serial1;
	22	pci0 = &pci0;
	23	pci1 = &pci1;
e598477a	24	pci2 = &pci2;
ea082fa9 KG	25	};
ea082fa9 KG	26
53f3945a XX	27	cpus {
	28	#address-cells = <1>;
	29	#size-cells = <0>;
	30
	31	PowerPC,8610@0 {
	32	device_type = "cpu";
	33	reg = <0>;
6e050d4e JL	34	d-cache-line-size = <32>;
	35	i-cache-line-size = <32>;
	36	d-cache-size = <32768>; // L1
	37	i-cache-size = <32768>; // L1
8c68e2f7 AV	38	sleep = <&pmc 0x00008000 0 // core
8c68e2f7 AV	39	&pmc 0x00004000 0>; // timebase
6e050d4e	40	timebase-frequency = <0>; // From uboot
53f3945a XX	41	bus-frequency = <0>; // From uboot
	42	clock-frequency = <0>; // From uboot
	43	};
	44	};
	45
	46	memory {
	47	device_type = "memory";
6e050d4e	48	reg = <0x00000000 0x20000000>; // 512M at 0x0
53f3945a XX	49	};
53f3945a XX	50
34b4a873 AV	51	localbus@e0005000 {
	52	#address-cells = <2>;
	53	#size-cells = <1>;
	54	compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
	55	reg = <0xe0005000 0x1000>;
	56	interrupts = <19 2>;
	57	interrupt-parent = <&mpic>;
	58	ranges = <0 0 0xf8000000 0x08000000
	59	1 0 0xf0000000 0x08000000
	60	2 0 0xe8400000 0x00008000
	61	4 0 0xe8440000 0x00008000
	62	5 0 0xe8480000 0x00008000
	63	6 0 0xe84c0000 0x00008000
	64	3 0 0xe8000000 0x00000020>;
8c68e2f7	65	sleep = <&pmc 0x08000000 0>;
34b4a873 AV	66
	67	flash@0,0 {
	68	compatible = "cfi-flash";
	69	reg = <0 0 0x8000000>;
	70	bank-width = <2>;
	71	device-width = <1>;
	72	};
	73
	74	flash@1,0 {
	75	compatible = "cfi-flash";
	76	reg = <1 0 0x8000000>;
	77	bank-width = <2>;
	78	device-width = <1>;
	79	};
	80
	81	flash@2,0 {
	82	compatible = "fsl,mpc8610-fcm-nand",
	83	"fsl,elbc-fcm-nand";
	84	reg = <2 0 0x8000>;
	85	};
	86
	87	flash@4,0 {
	88	compatible = "fsl,mpc8610-fcm-nand",
	89	"fsl,elbc-fcm-nand";
	90	reg = <4 0 0x8000>;
	91	};
	92
	93	flash@5,0 {
	94	compatible = "fsl,mpc8610-fcm-nand",
	95	"fsl,elbc-fcm-nand";
	96	reg = <5 0 0x8000>;
	97	};
	98
	99	flash@6,0 {
	100	compatible = "fsl,mpc8610-fcm-nand",
	101	"fsl,elbc-fcm-nand";
	102	reg = <6 0 0x8000>;
	103	};
	104
	105	board-control@3,0 {
d2998c2c AV	106	#address-cells = <1>;
d2998c2c AV	107	#size-cells = <1>;
34b4a873 AV	108	compatible = "fsl,fpga-pixis";
34b4a873 AV	109	reg = <3 0 0x20>;
d2998c2c	110	ranges = <0 3 0 0x20>;
8c68e2f7 AV	111	interrupt-parent = <&mpic>;
8c68e2f7 AV	112	interrupts = <8 8>;
d2998c2c AV	113
	114	sdcsr_pio: gpio-controller@a {
	115	#gpio-cells = <2>;
	116	compatible = "fsl,fpga-pixis-gpio-bank";
	117	reg = <0xa 1>;
	118	gpio-controller;
	119	};
34b4a873	120	};
9b53a9e2 YS	121	};
9b53a9e2 YS	122
53f3945a XX	123	soc@e0000000 {
	124	#address-cells = <1>;
	125	#size-cells = <1>;
	126	#interrupt-cells = <2>;
	127	device_type = "soc";
c7d24a2d	128	compatible = "fsl,mpc8610-immr", "simple-bus";
6e050d4e	129	ranges = <0x0 0xe0000000 0x00100000>;
53f3945a XX	130	bus-frequency = <0>;
53f3945a XX	131
da385780 KG	132	mcm-law@0 {
	133	compatible = "fsl,mcm-law";
	134	reg = <0x0 0x1000>;
	135	fsl,num-laws = <10>;
	136	};
	137
	138	mcm@1000 {
	139	compatible = "fsl,mpc8610-mcm", "fsl,mcm";
	140	reg = <0x1000 0x1000>;
	141	interrupts = <17 2>;
	142	interrupt-parent = <&mpic>;
	143	};
	144
53f3945a	145	i2c@3000 {
53f3945a XX	146	#address-cells = <1>;
53f3945a XX	147	#size-cells = <0>;
ec9686c4 KG	148	cell-index = <0>;
ec9686c4 KG	149	compatible = "fsl-i2c";
6e050d4e JL	150	reg = <0x3000 0x100>;
6e050d4e JL	151	interrupts = <43 2>;
53f3945a XX	152	interrupt-parent = <&mpic>;
53f3945a XX	153	dfsrr;
c7d24a2d	154
6e050d4e	155	cs4270:codec@4f {
c7d24a2d	156	compatible = "cirrus,cs4270";
6e050d4e	157	reg = <0x4f>;
c7d24a2d	158	/* MCLK source is a stand-alone oscillator */
6e050d4e JL	159	clock-frequency = <12288000>;
6e050d4e JL	160	};
53f3945a XX	161	};
	162
	163	i2c@3100 {
53f3945a XX	164	#address-cells = <1>;
53f3945a XX	165	#size-cells = <0>;
ec9686c4 KG	166	cell-index = <1>;
ec9686c4 KG	167	compatible = "fsl-i2c";
6e050d4e JL	168	reg = <0x3100 0x100>;
6e050d4e JL	169	interrupts = <43 2>;
53f3945a	170	interrupt-parent = <&mpic>;
8c68e2f7	171	sleep = <&pmc 0x00000004 0>;
53f3945a XX	172	dfsrr;
	173	};
	174
ea082fa9 KG	175	serial0: serial@4500 {
ea082fa9 KG	176	cell-index = <0>;
53f3945a XX	177	device_type = "serial";
53f3945a XX	178	compatible = "ns16550";
6e050d4e	179	reg = <0x4500 0x100>;
53f3945a	180	clock-frequency = <0>;
6e050d4e	181	interrupts = <42 2>;
53f3945a	182	interrupt-parent = <&mpic>;
8c68e2f7	183	sleep = <&pmc 0x00000002 0>;
53f3945a XX	184	};
53f3945a XX	185
ea082fa9 KG	186	serial1: serial@4600 {
ea082fa9 KG	187	cell-index = <1>;
53f3945a XX	188	device_type = "serial";
53f3945a XX	189	compatible = "ns16550";
6e050d4e	190	reg = <0x4600 0x100>;
53f3945a	191	clock-frequency = <0>;
aecb2b6e	192	interrupts = <42 2>;
53f3945a	193	interrupt-parent = <&mpic>;
8c68e2f7	194	sleep = <&pmc 0x00000008 0>;
53f3945a XX	195	};
53f3945a XX	196
d2998c2c AV	197	spi@7000 {
	198	#address-cells = <1>;
	199	#size-cells = <0>;
	200	compatible = "fsl,mpc8610-spi", "fsl,spi";
	201	reg = <0x7000 0x40>;
	202	cell-index = <0>;
	203	interrupts = <59 2>;
	204	interrupt-parent = <&mpic>;
	205	mode = "cpu";
	206	gpios = <&sdcsr_pio 7 0>;
8c68e2f7	207	sleep = <&pmc 0x00000800 0>;
d2998c2c AV	208
	209	mmc-slot@0 {
	210	compatible = "fsl,mpc8610hpcd-mmc-slot",
	211	"mmc-spi-slot";
	212	reg = <0>;
	213	gpios = <&sdcsr_pio 0 1 /* nCD */
	214	&sdcsr_pio 1 0>; /* WP */
	215	voltage-ranges = <3300 3300>;
	216	spi-max-frequency = <50000000>;
	217	};
	218	};
	219
9b53a9e2 YS	220	display@2c000 {
	221	compatible = "fsl,diu";
	222	reg = <0x2c000 100>;
	223	interrupts = <72 2>;
	224	interrupt-parent = <&mpic>;
8c68e2f7	225	sleep = <&pmc 0x04000000 0>;
9b53a9e2 YS	226	};
9b53a9e2 YS	227
53f3945a	228	mpic: interrupt-controller@40000 {
53f3945a XX	229	interrupt-controller;
	230	#address-cells = <0>;
	231	#interrupt-cells = <2>;
6e050d4e	232	reg = <0x40000 0x40000>;
53f3945a XX	233	compatible = "chrp,open-pic";
53f3945a XX	234	device_type = "open-pic";
53f3945a XX	235	};
53f3945a XX	236
0023352f JJ	237	msi@41600 {
	238	compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
	239	reg = <0x41600 0x80>;
	240	msi-available-ranges = <0 0x100>;
	241	interrupts = <
	242	0xe0 0
	243	0xe1 0
	244	0xe2 0
	245	0xe3 0
	246	0xe4 0
	247	0xe5 0
	248	0xe6 0
	249	0xe7 0>;
	250	interrupt-parent = <&mpic>;
	251	};
	252
53f3945a	253	global-utilities@e0000 {
8c68e2f7 AV	254	#address-cells = <1>;
8c68e2f7 AV	255	#size-cells = <1>;
53f3945a	256	compatible = "fsl,mpc8610-guts";
6e050d4e	257	reg = <0xe0000 0x1000>;
8c68e2f7	258	ranges = <0 0xe0000 0x1000>;
53f3945a	259	fsl,has-rstcr;
8c68e2f7 AV	260
	261	pmc: power@70 {
	262	compatible = "fsl,mpc8610-pmc",
	263	"fsl,mpc8641d-pmc";
	264	reg = <0x70 0x20>;
	265	};
53f3945a	266	};
c7d24a2d	267
775587b6 AV	268	wdt@e4000 {
	269	compatible = "fsl,mpc8610-wdt";
	270	reg = <0xe4000 0x100>;
	271	};
	272
c2fe5944	273	ssi@16000 {
c7d24a2d TT	274	compatible = "fsl,mpc8610-ssi";
c7d24a2d TT	275	cell-index = <0>;
6e050d4e	276	reg = <0x16000 0x100>;
c7d24a2d	277	interrupt-parent = <&mpic>;
6e050d4e	278	interrupts = <62 2>;
c7d24a2d TT	279	fsl,mode = "i2s-slave";
c7d24a2d TT	280	codec-handle = <&cs4270>;
c2fe5944 TT	281	fsl,playback-dma = <&dma00>;
c2fe5944 TT	282	fsl,capture-dma = <&dma01>;
0bcd783c	283	fsl,fifo-depth = <8>;
8c68e2f7	284	sleep = <&pmc 0 0x08000000>;
c7d24a2d TT	285	};
	286
	287	ssi@16100 {
	288	compatible = "fsl,mpc8610-ssi";
	289	cell-index = <1>;
6e050d4e	290	reg = <0x16100 0x100>;
c7d24a2d	291	interrupt-parent = <&mpic>;
6e050d4e	292	interrupts = <63 2>;
0bcd783c	293	fsl,fifo-depth = <8>;
8c68e2f7	294	sleep = <&pmc 0 0x04000000>;
c7d24a2d TT	295	};
c7d24a2d TT	296
6e050d4e JL	297	dma@21300 {
	298	#address-cells = <1>;
	299	#size-cells = <1>;
	300	compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
	301	cell-index = <0>;
	302	reg = <0x21300 0x4>; /* DMA general status register */
	303	ranges = <0x0 0x21100 0x200>;
8c68e2f7	304	sleep = <&pmc 0x00000400 0>;
c7d24a2d	305
c2fe5944	306	dma00: dma-channel@0 {
c7d24a2d	307	compatible = "fsl,mpc8610-dma-channel",
7de0c22b	308	"fsl,ssi-dma-channel";
c7d24a2d	309	cell-index = <0>;
6e050d4e	310	reg = <0x0 0x80>;
c7d24a2d	311	interrupt-parent = <&mpic>;
6e050d4e JL	312	interrupts = <20 2>;
6e050d4e JL	313	};
c2fe5944	314	dma01: dma-channel@1 {
c7d24a2d	315	compatible = "fsl,mpc8610-dma-channel",
7de0c22b	316	"fsl,ssi-dma-channel";
c7d24a2d	317	cell-index = <1>;
6e050d4e	318	reg = <0x80 0x80>;
c7d24a2d	319	interrupt-parent = <&mpic>;
6e050d4e JL	320	interrupts = <21 2>;
	321	};
	322	dma-channel@2 {
c7d24a2d TT	323	compatible = "fsl,mpc8610-dma-channel",
	324	"fsl,eloplus-dma-channel";
	325	cell-index = <2>;
6e050d4e	326	reg = <0x100 0x80>;
c7d24a2d	327	interrupt-parent = <&mpic>;
6e050d4e JL	328	interrupts = <22 2>;
	329	};
	330	dma-channel@3 {
c7d24a2d TT	331	compatible = "fsl,mpc8610-dma-channel",
	332	"fsl,eloplus-dma-channel";
	333	cell-index = <3>;
6e050d4e	334	reg = <0x180 0x80>;
c7d24a2d	335	interrupt-parent = <&mpic>;
6e050d4e JL	336	interrupts = <23 2>;
	337	};
	338	};
c7d24a2d	339
6e050d4e JL	340	dma@c300 {
	341	#address-cells = <1>;
	342	#size-cells = <1>;
9c8b28c2	343	compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
6e050d4e JL	344	cell-index = <1>;
	345	reg = <0xc300 0x4>; /* DMA general status register */
	346	ranges = <0x0 0xc100 0x200>;
8c68e2f7	347	sleep = <&pmc 0x00000200 0>;
c7d24a2d	348
6e050d4e	349	dma-channel@0 {
c7d24a2d	350	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	351	"fsl,eloplus-dma-channel";
c7d24a2d	352	cell-index = <0>;
6e050d4e	353	reg = <0x0 0x80>;
c7d24a2d	354	interrupt-parent = <&mpic>;
612f9d33	355	interrupts = <76 2>;
6e050d4e JL	356	};
6e050d4e JL	357	dma-channel@1 {
c7d24a2d	358	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	359	"fsl,eloplus-dma-channel";
c7d24a2d	360	cell-index = <1>;
6e050d4e	361	reg = <0x80 0x80>;
c7d24a2d	362	interrupt-parent = <&mpic>;
612f9d33	363	interrupts = <77 2>;
6e050d4e JL	364	};
6e050d4e JL	365	dma-channel@2 {
c7d24a2d	366	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	367	"fsl,eloplus-dma-channel";
c7d24a2d	368	cell-index = <2>;
6e050d4e	369	reg = <0x100 0x80>;
c7d24a2d	370	interrupt-parent = <&mpic>;
612f9d33	371	interrupts = <78 2>;
6e050d4e JL	372	};
6e050d4e JL	373	dma-channel@3 {
c7d24a2d	374	compatible = "fsl,mpc8610-dma-channel",
9c8b28c2	375	"fsl,eloplus-dma-channel";
c7d24a2d	376	cell-index = <3>;
6e050d4e	377	reg = <0x180 0x80>;
c7d24a2d	378	interrupt-parent = <&mpic>;
612f9d33	379	interrupts = <79 2>;
6e050d4e JL	380	};
6e050d4e JL	381	};
c7d24a2d	382
53f3945a XX	383	};
53f3945a XX	384
ea082fa9	385	pci0: pci@e0008000 {
53f3945a XX	386	compatible = "fsl,mpc8610-pci";
	387	device_type = "pci";
	388	#interrupt-cells = <1>;
	389	#size-cells = <2>;
	390	#address-cells = <3>;
6e050d4e	391	reg = <0xe0008000 0x1000>;
53f3945a	392	bus-range = <0 0>;
6e050d4e JL	393	ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
6e050d4e JL	394	0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
8c68e2f7	395	sleep = <&pmc 0x80000000 0>;
6e050d4e	396	clock-frequency = <33333333>;
53f3945a	397	interrupt-parent = <&mpic>;
6e050d4e JL	398	interrupts = <24 2>;
6e050d4e JL	399	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	400	interrupt-map = <
53f3945a XX	401	/* IDSEL 0x11 */
6e050d4e JL	402	0x8800 0 0 1 &mpic 4 1
	403	0x8800 0 0 2 &mpic 5 1
	404	0x8800 0 0 3 &mpic 6 1
	405	0x8800 0 0 4 &mpic 7 1
53f3945a XX	406
53f3945a XX	407	/* IDSEL 0x12 */
6e050d4e JL	408	0x9000 0 0 1 &mpic 5 1
	409	0x9000 0 0 2 &mpic 6 1
	410	0x9000 0 0 3 &mpic 7 1
	411	0x9000 0 0 4 &mpic 4 1
53f3945a XX	412	>;
	413	};
	414
ea082fa9	415	pci1: pcie@e000a000 {
53f3945a XX	416	compatible = "fsl,mpc8641-pcie";
	417	device_type = "pci";
	418	#interrupt-cells = <1>;
	419	#size-cells = <2>;
	420	#address-cells = <3>;
6e050d4e	421	reg = <0xe000a000 0x1000>;
53f3945a	422	bus-range = <1 3>;
6e050d4e JL	423	ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
6e050d4e JL	424	0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
8c68e2f7	425	sleep = <&pmc 0x40000000 0>;
6e050d4e	426	clock-frequency = <33333333>;
53f3945a	427	interrupt-parent = <&mpic>;
6e050d4e JL	428	interrupts = <26 2>;
6e050d4e JL	429	interrupt-map-mask = <0xf800 0 0 7>;
53f3945a XX	430
	431	interrupt-map = <
	432	/* IDSEL 0x1b */
6e050d4e	433	0xd800 0 0 1 &mpic 2 1
53f3945a XX	434
53f3945a XX	435	/* IDSEL 0x1c*/
6e050d4e JL	436	0xe000 0 0 1 &mpic 1 1
	437	0xe000 0 0 2 &mpic 1 1
	438	0xe000 0 0 3 &mpic 1 1
	439	0xe000 0 0 4 &mpic 1 1
53f3945a XX	440
53f3945a XX	441	/* IDSEL 0x1f */
deabeabf	442	0xf800 0 0 1 &mpic 3 2
6e050d4e	443	0xf800 0 0 2 &mpic 0 1
53f3945a XX	444	>;
	445
	446	pcie@0 {
	447	reg = <0 0 0 0 0>;
	448	#size-cells = <2>;
	449	#address-cells = <3>;
	450	device_type = "pci";
6e050d4e JL	451	ranges = <0x02000000 0x0 0xa0000000
	452	0x02000000 0x0 0xa0000000
	453	0x0 0x10000000
	454	0x01000000 0x0 0x00000000
	455	0x01000000 0x0 0x00000000
	456	0x0 0x00100000>;
53f3945a XX	457	uli1575@0 {
	458	reg = <0 0 0 0 0>;
	459	#size-cells = <2>;
	460	#address-cells = <3>;
6e050d4e JL	461	ranges = <0x02000000 0x0 0xa0000000
	462	0x02000000 0x0 0xa0000000
	463	0x0 0x10000000
	464	0x01000000 0x0 0x00000000
	465	0x01000000 0x0 0x00000000
	466	0x0 0x00100000>;
a47fda93 AV	467
	468	isa@1e {
	469	device_type = "isa";
	470	#size-cells = <1>;
	471	#address-cells = <2>;
	472	reg = <0xf000 0 0 0 0>;
	473	ranges = <1 0 0x01000000 0 0
	474	0x00001000>;
	475
	476	rtc@70 {
	477	compatible = "pnpPNP,b00";
	478	reg = <1 0x70 2>;
	479	};
	480	};
53f3945a XX	481	};
	482	};
	483	};
e598477a AV	484
	485	pci2: pcie@e0009000 {
	486	#address-cells = <3>;
	487	#size-cells = <2>;
	488	#interrupt-cells = <1>;
	489	device_type = "pci";
	490	compatible = "fsl,mpc8641-pcie";
	491	reg = <0xe0009000 0x00001000>;
	492	ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
	493	0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
	494	bus-range = <0 255>;
	495	interrupt-map-mask = <0xf800 0 0 7>;
	496	interrupt-map = <0x0000 0 0 1 &mpic 4 1
	497	0x0000 0 0 2 &mpic 5 1
	498	0x0000 0 0 3 &mpic 6 1
	499	0x0000 0 0 4 &mpic 7 1>;
	500	interrupt-parent = <&mpic>;
	501	interrupts = <25 2>;
8c68e2f7	502	sleep = <&pmc 0x20000000 0>;
e598477a AV	503	clock-frequency = <33333333>;
e598477a AV	504	};
53f3945a	505	};