[linux-2.6-block.git] / arch / powerpc / boot / dts / mpc8568mds.dts

/*
 * MPC8568E MDS Device Tree Source
 *
 * Copyright 2007, 2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/dts-v1/;

/ {
	model = "MPC8568EMDS";
	compatible = "MPC8568EMDS", "MPC85xxMDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		ethernet2 = &enet2;
		ethernet3 = &enet3;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8568@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x10000000>;
	};

	bcsr@f8000000 {
		device_type = "board-control";
		reg = <0xf8000000 0x8000>;
	};

	soc8568@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		ranges = <0x0 0xe0000000 0x100000>;
		reg = <0xe0000000 0x1000>;
		bus-frequency = <0>;

		memory-controller@2000 {
			compatible = "fsl,8568-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,8568-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x80000>;	// L2, 512K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			rtc@68 {
				compatible = "dallas,ds1374";
				reg = <0x68>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8568-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8568-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8568-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8568-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		mdio@24520 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,gianfar-mdio";
			reg = <0x24520 0x20>;

			phy0: ethernet-phy@7 {
				interrupt-parent = <&mpic>;
				interrupts = <1 1>;
				reg = <0x7>;
				device_type = "ethernet-phy";
			};
			phy1: ethernet-phy@1 {
				interrupt-parent = <&mpic>;
				interrupts = <2 1>;
				reg = <0x1>;
				device_type = "ethernet-phy";
			};
			phy2: ethernet-phy@2 {
				interrupt-parent = <&mpic>;
				interrupts = <1 1>;
				reg = <0x2>;
				device_type = "ethernet-phy";
			};
			phy3: ethernet-phy@3 {
				interrupt-parent = <&mpic>;
				interrupts = <2 1>;
				reg = <0x3>;
				device_type = "ethernet-phy";
			};
		};

		enet0: ethernet@24000 {
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
 			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy2>;
		};

		enet1: ethernet@25000 {
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
 			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			phy-handle = <&phy3>;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		global-utilities@e0000 {	//global utilities block
			compatible = "fsl,mpc8548-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		crypto@30000 {
			device_type = "crypto";
			model = "SEC2";
			compatible = "talitos";
			reg = <0x30000 0xf000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			num-channels = <4>;
			channel-fifo-len = <24>;
			exec-units-mask = <0xfe>;
			descriptor-types-mask = <0x12b0ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		par_io@e0100 {
			reg = <0xe0100 0x100>;
			device_type = "par_io";
			num-ports = <7>;

			pio1: ucc_pin@01 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0x4  0xa  0x1  0x0  0x2  0x0 	/* TxD0 */
					0x4  0x9  0x1  0x0  0x2  0x0 	/* TxD1 */
					0x4  0x8  0x1  0x0  0x2  0x0 	/* TxD2 */
					0x4  0x7  0x1  0x0  0x2  0x0 	/* TxD3 */
					0x4  0x17  0x1  0x0  0x2  0x0 	/* TxD4 */
					0x4  0x16  0x1  0x0  0x2  0x0 	/* TxD5 */
					0x4  0x15  0x1  0x0  0x2  0x0 	/* TxD6 */
					0x4  0x14  0x1  0x0  0x2  0x0 	/* TxD7 */
					0x4  0xf  0x2  0x0  0x2  0x0 	/* RxD0 */
					0x4  0xe  0x2  0x0  0x2  0x0 	/* RxD1 */
					0x4  0xd  0x2  0x0  0x2  0x0 	/* RxD2 */
					0x4  0xc  0x2  0x0  0x2  0x0 	/* RxD3 */
					0x4  0x1d  0x2  0x0  0x2  0x0 	/* RxD4 */
					0x4  0x1c  0x2  0x0  0x2  0x0 	/* RxD5 */
					0x4  0x1b  0x2  0x0  0x2  0x0 	/* RxD6 */
					0x4  0x1a  0x2  0x0  0x2  0x0 	/* RxD7 */
					0x4  0xb  0x1  0x0  0x2  0x0 	/* TX_EN */
					0x4  0x18  0x1  0x0  0x2  0x0 	/* TX_ER */
					0x4  0x10  0x2  0x0  0x2  0x0 	/* RX_DV */
					0x4  0x1e  0x2  0x0  0x2  0x0 	/* RX_ER */
					0x4  0x11  0x2  0x0  0x2  0x0 	/* RX_CLK */
					0x4  0x13  0x1  0x0  0x2  0x0 	/* GTX_CLK */
					0x1  0x1f  0x2  0x0  0x3  0x0>;	/* GTX125 */
			};

			pio2: ucc_pin@02 {
				pio-map = <
			/* port  pin  dir  open_drain  assignment  has_irq */
					0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
					0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
					0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
					0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
					0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
					0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
					0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
					0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
					0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
					0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
					0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
					0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
					0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
					0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
					0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
					0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
					0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
					0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
					0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
					0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
					0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
					0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
					0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
					0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
					0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
			};
		};
	};

	qe@e0080000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "qe";
		compatible = "fsl,qe";
		ranges = <0x0 0xe0080000 0x40000>;
		reg = <0xe0080000 0x480>;
		brg-frequency = <0>;
		bus-frequency = <396000000>;

		muram@10000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
			compatible = "fsl,qe-muram", "fsl,cpm-muram";
			ranges = <0x0 0x10000 0x10000>;

			data-only@0 {
				compatible = "fsl,qe-muram-data",
					     "fsl,cpm-muram-data";
				reg = <0x0 0x10000>;
			};
		};

		spi@4c0 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x4c0 0x40>;
			interrupts = <2>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		spi@500 {
			cell-index = <1>;
			compatible = "fsl,spi";
			reg = <0x500 0x40>;
			interrupts = <1>;
			interrupt-parent = <&qeic>;
			mode = "cpu";
		};

		enet2: ucc@2000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <1>;
			reg = <0x2000 0x200>;
			interrupts = <32>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk16";
			pio-handle = <&pio1>;
			phy-handle = <&phy0>;
			phy-connection-type = "rgmii-id";
		};

		enet3: ucc@3000 {
			device_type = "network";
			compatible = "ucc_geth";
			cell-index = <2>;
			reg = <0x3000 0x200>;
			interrupts = <33>;
			interrupt-parent = <&qeic>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			rx-clock-name = "none";
			tx-clock-name = "clk16";
			pio-handle = <&pio2>;
			phy-handle = <&phy1>;
			phy-connection-type = "rgmii-id";
		};

		mdio@2120 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2120 0x18>;
			compatible = "fsl,ucc-mdio";

			/* These are the same PHYs as on
			 * gianfar's MDIO bus */
			qe_phy0: ethernet-phy@07 {
				interrupt-parent = <&mpic>;
				interrupts = <1 1>;
				reg = <0x7>;
				device_type = "ethernet-phy";
			};
			qe_phy1: ethernet-phy@01 {
				interrupt-parent = <&mpic>;
				interrupts = <2 1>;
				reg = <0x1>;
				device_type = "ethernet-phy";
			};
			qe_phy2: ethernet-phy@02 {
				interrupt-parent = <&mpic>;
				interrupts = <1 1>;
				reg = <0x2>;
				device_type = "ethernet-phy";
			};
			qe_phy3: ethernet-phy@03 {
				interrupt-parent = <&mpic>;
				interrupts = <2 1>;
				reg = <0x3>;
				device_type = "ethernet-phy";
			};
		};

		qeic: interrupt-controller@80 {
			interrupt-controller;
			compatible = "fsl,qe-ic";
			#address-cells = <0>;
			#interrupt-cells = <1>;
			reg = <0x80 0x80>;
			big-endian;
			interrupts = <46 2 46 2>; //high:30 low:30
			interrupt-parent = <&mpic>;
		};

	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <
			/* IDSEL 0x12 AD18 */
			0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x4 0x1

			/* IDSEL 0x13 AD19 */
			0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
			0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
			0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
			0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
	};

	/* PCI Express */
	pci1: pcie@e000a000 {
		cell-index = <2>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x0 (PEX) */
			00000 0x0 0x0 0x1 &mpic 0x0 0x1
			00000 0x0 0x0 0x2 &mpic 0x1 0x1
			00000 0x0 0x0 0x3 &mpic 0x2 0x1
			00000 0x0 0x0 0x4 &mpic 0x3 0x1>;

		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		bus-range = <0 255>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
		clock-frequency = <33333333>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		compatible = "fsl,mpc8548-pcie";
		device_type = "pci";
		pcie@0 {
			reg = <0x0 0x0 0x0 0x0 0x0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x10000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x800000>;
		};
	};
};
Commit	Line	Data
c2882bb1 AF	1	/*
	2	* MPC8568E MDS Device Tree Source
	3	*
32f960e9	4	* Copyright 2007, 2008 Freescale Semiconductor Inc.
c2882bb1 AF	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the
	8	* Free Software Foundation; either version 2 of the License, or (at your
	9	* option) any later version.
	10	*/
	11
32f960e9	12	/dts-v1/;
c2882bb1	13
c2882bb1 AF	14	/ {
c2882bb1 AF	15	model = "MPC8568EMDS";
52094879	16	compatible = "MPC8568EMDS", "MPC85xxMDS";
c2882bb1 AF	17	#address-cells = <1>;
c2882bb1 AF	18	#size-cells = <1>;
c2882bb1	19
ea082fa9 KG	20	aliases {
	21	ethernet0 = &enet0;
	22	ethernet1 = &enet1;
	23	ethernet2 = &enet2;
	24	ethernet3 = &enet3;
	25	serial0 = &serial0;
	26	serial1 = &serial1;
	27	pci0 = &pci0;
	28	pci1 = &pci1;
	29	};
	30
c2882bb1	31	cpus {
c2882bb1 AF	32	#address-cells = <1>;
c2882bb1 AF	33	#size-cells = <0>;
c2882bb1 AF	34
	35	PowerPC,8568@0 {
	36	device_type = "cpu";
32f960e9 KG	37	reg = <0x0>;
	38	d-cache-line-size = <32>; // 32 bytes
	39	i-cache-line-size = <32>; // 32 bytes
	40	d-cache-size = <0x8000>; // L1, 32K
	41	i-cache-size = <0x8000>; // L1, 32K
c2882bb1 AF	42	timebase-frequency = <0>;
	43	bus-frequency = <0>;
	44	clock-frequency = <0>;
c054065b	45	next-level-cache = <&L2>;
c2882bb1 AF	46	};
	47	};
	48
	49	memory {
	50	device_type = "memory";
32f960e9	51	reg = <0x0 0x10000000>;
c2882bb1 AF	52	};
	53
	54	bcsr@f8000000 {
	55	device_type = "board-control";
32f960e9	56	reg = <0xf8000000 0x8000>;
c2882bb1 AF	57	};
	58
	59	soc8568@e0000000 {
	60	#address-cells = <1>;
	61	#size-cells = <1>;
c2882bb1	62	device_type = "soc";
32f960e9 KG	63	ranges = <0x0 0xe0000000 0x100000>;
32f960e9 KG	64	reg = <0xe0000000 0x1000>;
c2882bb1 AF	65	bus-frequency = <0>;
c2882bb1 AF	66
4da421d6 KG	67	memory-controller@2000 {
4da421d6 KG	68	compatible = "fsl,8568-memory-controller";
32f960e9	69	reg = <0x2000 0x1000>;
4da421d6	70	interrupt-parent = <&mpic>;
32f960e9	71	interrupts = <18 2>;
4da421d6 KG	72	};
4da421d6 KG	73
c054065b	74	L2: l2-cache-controller@20000 {
4da421d6	75	compatible = "fsl,8568-l2-cache-controller";
32f960e9 KG	76	reg = <0x20000 0x1000>;
	77	cache-line-size = <32>; // 32 bytes
	78	cache-size = <0x80000>; // L2, 512K
4da421d6	79	interrupt-parent = <&mpic>;
32f960e9	80	interrupts = <16 2>;
4da421d6 KG	81	};
4da421d6 KG	82
c2882bb1	83	i2c@3000 {
c0e4eb2d AV	84	#address-cells = <1>;
c0e4eb2d AV	85	#size-cells = <0>;
ec9686c4	86	cell-index = <0>;
c2882bb1	87	compatible = "fsl-i2c";
32f960e9 KG	88	reg = <0x3000 0x100>;
32f960e9 KG	89	interrupts = <43 2>;
52094879	90	interrupt-parent = <&mpic>;
c2882bb1	91	dfsrr;
c0e4eb2d AV	92
	93	rtc@68 {
	94	compatible = "dallas,ds1374";
32f960e9	95	reg = <0x68>;
c0e4eb2d	96	};
c2882bb1 AF	97	};
	98
	99	i2c@3100 {
c0e4eb2d AV	100	#address-cells = <1>;
c0e4eb2d AV	101	#size-cells = <0>;
ec9686c4	102	cell-index = <1>;
c2882bb1	103	compatible = "fsl-i2c";
32f960e9 KG	104	reg = <0x3100 0x100>;
32f960e9 KG	105	interrupts = <43 2>;
52094879	106	interrupt-parent = <&mpic>;
c2882bb1 AF	107	dfsrr;
	108	};
	109
dee80553 KG	110	dma@21300 {
	111	#address-cells = <1>;
	112	#size-cells = <1>;
	113	compatible = "fsl,mpc8568-dma", "fsl,eloplus-dma";
	114	reg = <0x21300 0x4>;
	115	ranges = <0x0 0x21100 0x200>;
	116	cell-index = <0>;
	117	dma-channel@0 {
	118	compatible = "fsl,mpc8568-dma-channel",
	119	"fsl,eloplus-dma-channel";
	120	reg = <0x0 0x80>;
	121	cell-index = <0>;
	122	interrupt-parent = <&mpic>;
	123	interrupts = <20 2>;
	124	};
	125	dma-channel@80 {
	126	compatible = "fsl,mpc8568-dma-channel",
	127	"fsl,eloplus-dma-channel";
	128	reg = <0x80 0x80>;
	129	cell-index = <1>;
	130	interrupt-parent = <&mpic>;
	131	interrupts = <21 2>;
	132	};
	133	dma-channel@100 {
	134	compatible = "fsl,mpc8568-dma-channel",
	135	"fsl,eloplus-dma-channel";
	136	reg = <0x100 0x80>;
	137	cell-index = <2>;
	138	interrupt-parent = <&mpic>;
	139	interrupts = <22 2>;
	140	};
	141	dma-channel@180 {
	142	compatible = "fsl,mpc8568-dma-channel",
	143	"fsl,eloplus-dma-channel";
	144	reg = <0x180 0x80>;
	145	cell-index = <3>;
	146	interrupt-parent = <&mpic>;
	147	interrupts = <23 2>;
	148	};
	149	};
	150
c2882bb1 AF	151	mdio@24520 {
	152	#address-cells = <1>;
	153	#size-cells = <0>;
e77b28eb	154	compatible = "fsl,gianfar-mdio";
32f960e9	155	reg = <0x24520 0x20>;
e77b28eb	156
af6521ea	157	phy0: ethernet-phy@7 {
52094879	158	interrupt-parent = <&mpic>;
b533f8ae	159	interrupts = <1 1>;
32f960e9	160	reg = <0x7>;
c2882bb1 AF	161	device_type = "ethernet-phy";
c2882bb1 AF	162	};
52094879 KG	163	phy1: ethernet-phy@1 {
52094879 KG	164	interrupt-parent = <&mpic>;
b533f8ae	165	interrupts = <2 1>;
32f960e9	166	reg = <0x1>;
c2882bb1 AF	167	device_type = "ethernet-phy";
c2882bb1 AF	168	};
52094879 KG	169	phy2: ethernet-phy@2 {
52094879 KG	170	interrupt-parent = <&mpic>;
b533f8ae	171	interrupts = <1 1>;
32f960e9	172	reg = <0x2>;
c2882bb1 AF	173	device_type = "ethernet-phy";
c2882bb1 AF	174	};
52094879 KG	175	phy3: ethernet-phy@3 {
52094879 KG	176	interrupt-parent = <&mpic>;
b533f8ae	177	interrupts = <2 1>;
32f960e9	178	reg = <0x3>;
c2882bb1 AF	179	device_type = "ethernet-phy";
	180	};
	181	};
	182
e77b28eb KG	183	enet0: ethernet@24000 {
e77b28eb KG	184	cell-index = <0>;
c2882bb1 AF	185	device_type = "network";
	186	model = "eTSEC";
	187	compatible = "gianfar";
32f960e9	188	reg = <0x24000 0x1000>;
eae98266	189	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	190	interrupts = <29 2 30 2 34 2>;
52094879 KG	191	interrupt-parent = <&mpic>;
52094879 KG	192	phy-handle = <&phy2>;
c2882bb1 AF	193	};
c2882bb1 AF	194
e77b28eb KG	195	enet1: ethernet@25000 {
e77b28eb KG	196	cell-index = <1>;
c2882bb1 AF	197	device_type = "network";
	198	model = "eTSEC";
	199	compatible = "gianfar";
32f960e9	200	reg = <0x25000 0x1000>;
eae98266	201	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	202	interrupts = <35 2 36 2 40 2>;
52094879 KG	203	interrupt-parent = <&mpic>;
52094879 KG	204	phy-handle = <&phy3>;
c2882bb1 AF	205	};
c2882bb1 AF	206
ea082fa9 KG	207	serial0: serial@4500 {
ea082fa9 KG	208	cell-index = <0>;
c2882bb1 AF	209	device_type = "serial";
c2882bb1 AF	210	compatible = "ns16550";
32f960e9	211	reg = <0x4500 0x100>;
c2882bb1	212	clock-frequency = <0>;
32f960e9	213	interrupts = <42 2>;
52094879	214	interrupt-parent = <&mpic>;
c2882bb1 AF	215	};
c2882bb1 AF	216
10ce8c69 RZ	217	global-utilities@e0000 { //global utilities block
10ce8c69 RZ	218	compatible = "fsl,mpc8548-guts";
32f960e9	219	reg = <0xe0000 0x1000>;
10ce8c69 RZ	220	fsl,has-rstcr;
	221	};
	222
ea082fa9 KG	223	serial1: serial@4600 {
ea082fa9 KG	224	cell-index = <1>;
c2882bb1 AF	225	device_type = "serial";
c2882bb1 AF	226	compatible = "ns16550";
32f960e9	227	reg = <0x4600 0x100>;
c2882bb1	228	clock-frequency = <0>;
32f960e9	229	interrupts = <42 2>;
52094879	230	interrupt-parent = <&mpic>;
c2882bb1 AF	231	};
	232
	233	crypto@30000 {
	234	device_type = "crypto";
	235	model = "SEC2";
	236	compatible = "talitos";
32f960e9 KG	237	reg = <0x30000 0xf000>;
32f960e9 KG	238	interrupts = <45 2>;
52094879	239	interrupt-parent = <&mpic>;
c2882bb1	240	num-channels = <4>;
32f960e9 KG	241	channel-fifo-len = <24>;
	242	exec-units-mask = <0xfe>;
	243	descriptor-types-mask = <0x12b0ebf>;
c2882bb1 AF	244	};
c2882bb1 AF	245
52094879	246	mpic: pic@40000 {
c2882bb1 AF	247	interrupt-controller;
	248	#address-cells = <0>;
	249	#interrupt-cells = <2>;
32f960e9	250	reg = <0x40000 0x40000>;
c2882bb1 AF	251	compatible = "chrp,open-pic";
c2882bb1 AF	252	device_type = "open-pic";
c2882bb1	253	};
86a04d9c	254
c2882bb1	255	par_io@e0100 {
32f960e9	256	reg = <0xe0100 0x100>;
c2882bb1 AF	257	device_type = "par_io";
	258	num-ports = <7>;
	259
52094879	260	pio1: ucc_pin@01 {
c2882bb1 AF	261	pio-map = <
c2882bb1 AF	262	/* port pin dir open_drain assignment has_irq */
32f960e9 KG	263	0x4 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
	264	0x4 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
	265	0x4 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
	266	0x4 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
	267	0x4 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
	268	0x4 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
	269	0x4 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
	270	0x4 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
	271	0x4 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
	272	0x4 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
	273	0x4 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
	274	0x4 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
	275	0x4 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
	276	0x4 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
	277	0x4 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
	278	0x4 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
	279	0x4 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
	280	0x4 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
	281	0x4 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
	282	0x4 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
	283	0x4 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
	284	0x4 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
	285	0x1 0x1f 0x2 0x0 0x3 0x0>; /* GTX125 */
c2882bb1	286	};
86a04d9c	287
52094879	288	pio2: ucc_pin@02 {
c2882bb1 AF	289	pio-map = <
c2882bb1 AF	290	/* port pin dir open_drain assignment has_irq */
32f960e9 KG	291	0x5 0xa 0x1 0x0 0x2 0x0 /* TxD0 */
	292	0x5 0x9 0x1 0x0 0x2 0x0 /* TxD1 */
	293	0x5 0x8 0x1 0x0 0x2 0x0 /* TxD2 */
	294	0x5 0x7 0x1 0x0 0x2 0x0 /* TxD3 */
	295	0x5 0x17 0x1 0x0 0x2 0x0 /* TxD4 */
	296	0x5 0x16 0x1 0x0 0x2 0x0 /* TxD5 */
	297	0x5 0x15 0x1 0x0 0x2 0x0 /* TxD6 */
	298	0x5 0x14 0x1 0x0 0x2 0x0 /* TxD7 */
	299	0x5 0xf 0x2 0x0 0x2 0x0 /* RxD0 */
	300	0x5 0xe 0x2 0x0 0x2 0x0 /* RxD1 */
	301	0x5 0xd 0x2 0x0 0x2 0x0 /* RxD2 */
	302	0x5 0xc 0x2 0x0 0x2 0x0 /* RxD3 */
	303	0x5 0x1d 0x2 0x0 0x2 0x0 /* RxD4 */
	304	0x5 0x1c 0x2 0x0 0x2 0x0 /* RxD5 */
	305	0x5 0x1b 0x2 0x0 0x2 0x0 /* RxD6 */
	306	0x5 0x1a 0x2 0x0 0x2 0x0 /* RxD7 */
	307	0x5 0xb 0x1 0x0 0x2 0x0 /* TX_EN */
	308	0x5 0x18 0x1 0x0 0x2 0x0 /* TX_ER */
	309	0x5 0x10 0x2 0x0 0x2 0x0 /* RX_DV */
	310	0x5 0x1e 0x2 0x0 0x2 0x0 /* RX_ER */
	311	0x5 0x11 0x2 0x0 0x2 0x0 /* RX_CLK */
	312	0x5 0x13 0x1 0x0 0x2 0x0 /* GTX_CLK */
	313	0x1 0x1f 0x2 0x0 0x3 0x0 /* GTX125 */
	314	0x4 0x6 0x3 0x0 0x2 0x0 /* MDIO */
	315	0x4 0x5 0x1 0x0 0x2 0x0>; /* MDC */
c2882bb1 AF	316	};
	317	};
	318	};
	319
	320	qe@e0080000 {
	321	#address-cells = <1>;
	322	#size-cells = <1>;
	323	device_type = "qe";
a2dd70a1	324	compatible = "fsl,qe";
32f960e9 KG	325	ranges = <0x0 0xe0080000 0x40000>;
32f960e9 KG	326	reg = <0xe0080000 0x480>;
c2882bb1	327	brg-frequency = <0>;
32f960e9	328	bus-frequency = <396000000>;
c2882bb1 AF	329
c2882bb1 AF	330	muram@10000 {
390167ef PG	331	#address-cells = <1>;
390167ef PG	332	#size-cells = <1>;
a2dd70a1	333	compatible = "fsl,qe-muram", "fsl,cpm-muram";
8bdf5733	334	ranges = <0x0 0x10000 0x10000>;
c2882bb1	335
390167ef	336	data-only@0 {
a2dd70a1 AV	337	compatible = "fsl,qe-muram-data",
a2dd70a1 AV	338	"fsl,cpm-muram-data";
8bdf5733	339	reg = <0x0 0x10000>;
c2882bb1 AF	340	};
	341	};
	342
	343	spi@4c0 {
f3a2b29d AV	344	cell-index = <0>;
f3a2b29d AV	345	compatible = "fsl,spi";
32f960e9	346	reg = <0x4c0 0x40>;
c2882bb1	347	interrupts = <2>;
52094879	348	interrupt-parent = <&qeic>;
c2882bb1 AF	349	mode = "cpu";
	350	};
	351
	352	spi@500 {
f3a2b29d AV	353	cell-index = <1>;
f3a2b29d AV	354	compatible = "fsl,spi";
32f960e9	355	reg = <0x500 0x40>;
c2882bb1	356	interrupts = <1>;
52094879	357	interrupt-parent = <&qeic>;
c2882bb1 AF	358	mode = "cpu";
	359	};
	360
e77b28eb	361	enet2: ucc@2000 {
c2882bb1 AF	362	device_type = "network";
c2882bb1 AF	363	compatible = "ucc_geth";
e77b28eb	364	cell-index = <1>;
32f960e9 KG	365	reg = <0x2000 0x200>;
32f960e9 KG	366	interrupts = <32>;
52094879	367	interrupt-parent = <&qeic>;
eae98266	368	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	369	rx-clock-name = "none";
9fb1e350 TT	370	tx-clock-name = "clk16";
52094879	371	pio-handle = <&pio1>;
af6521ea AV	372	phy-handle = <&phy0>;
af6521ea AV	373	phy-connection-type = "rgmii-id";
c2882bb1 AF	374	};
c2882bb1 AF	375
e77b28eb	376	enet3: ucc@3000 {
c2882bb1 AF	377	device_type = "network";
c2882bb1 AF	378	compatible = "ucc_geth";
e77b28eb	379	cell-index = <2>;
32f960e9 KG	380	reg = <0x3000 0x200>;
32f960e9 KG	381	interrupts = <33>;
52094879	382	interrupt-parent = <&qeic>;
eae98266	383	local-mac-address = [ 00 00 00 00 00 00 ];
9fb1e350 TT	384	rx-clock-name = "none";
9fb1e350 TT	385	tx-clock-name = "clk16";
52094879	386	pio-handle = <&pio2>;
af6521ea AV	387	phy-handle = <&phy1>;
af6521ea AV	388	phy-connection-type = "rgmii-id";
c2882bb1 AF	389	};
	390
	391	mdio@2120 {
	392	#address-cells = <1>;
	393	#size-cells = <0>;
32f960e9	394	reg = <0x2120 0x18>;
d0a2f82d	395	compatible = "fsl,ucc-mdio";
c2882bb1 AF	396
	397	/* These are the same PHYs as on
	398	* gianfar's MDIO bus */
af6521ea	399	qe_phy0: ethernet-phy@07 {
52094879	400	interrupt-parent = <&mpic>;
b533f8ae	401	interrupts = <1 1>;
32f960e9	402	reg = <0x7>;
c2882bb1	403	device_type = "ethernet-phy";
c2882bb1	404	};
52094879 KG	405	qe_phy1: ethernet-phy@01 {
52094879 KG	406	interrupt-parent = <&mpic>;
b533f8ae	407	interrupts = <2 1>;
32f960e9	408	reg = <0x1>;
c2882bb1	409	device_type = "ethernet-phy";
c2882bb1	410	};
52094879 KG	411	qe_phy2: ethernet-phy@02 {
52094879 KG	412	interrupt-parent = <&mpic>;
b533f8ae	413	interrupts = <1 1>;
32f960e9	414	reg = <0x2>;
c2882bb1	415	device_type = "ethernet-phy";
c2882bb1	416	};
52094879 KG	417	qe_phy3: ethernet-phy@03 {
52094879 KG	418	interrupt-parent = <&mpic>;
b533f8ae	419	interrupts = <2 1>;
32f960e9	420	reg = <0x3>;
c2882bb1	421	device_type = "ethernet-phy";
c2882bb1 AF	422	};
	423	};
	424
a2dd70a1	425	qeic: interrupt-controller@80 {
c2882bb1	426	interrupt-controller;
a2dd70a1	427	compatible = "fsl,qe-ic";
c2882bb1 AF	428	#address-cells = <0>;
c2882bb1 AF	429	#interrupt-cells = <1>;
32f960e9	430	reg = <0x80 0x80>;
c2882bb1	431	big-endian;
32f960e9	432	interrupts = <46 2 46 2>; //high:30 low:30
52094879	433	interrupt-parent = <&mpic>;
c2882bb1 AF	434	};
	435
	436	};
86a04d9c	437
ea082fa9 KG	438	pci0: pci@e0008000 {
ea082fa9 KG	439	cell-index = <0>;
32f960e9	440	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
86a04d9c KG	441	interrupt-map = <
86a04d9c KG	442	/* IDSEL 0x12 AD18 */
32f960e9 KG	443	0x9000 0x0 0x0 0x1 &mpic 0x5 0x1
	444	0x9000 0x0 0x0 0x2 &mpic 0x6 0x1
	445	0x9000 0x0 0x0 0x3 &mpic 0x7 0x1
	446	0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
86a04d9c KG	447
86a04d9c KG	448	/* IDSEL 0x13 AD19 */
32f960e9 KG	449	0x9800 0x0 0x0 0x1 &mpic 0x6 0x1
	450	0x9800 0x0 0x0 0x2 &mpic 0x7 0x1
	451	0x9800 0x0 0x0 0x3 &mpic 0x4 0x1
	452	0x9800 0x0 0x0 0x4 &mpic 0x5 0x1>;
86a04d9c KG	453
86a04d9c KG	454	interrupt-parent = <&mpic>;
32f960e9 KG	455	interrupts = <24 2>;
	456	bus-range = <0 255>;
	457	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	458	0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
	459	clock-frequency = <66666666>;
86a04d9c KG	460	#interrupt-cells = <1>;
	461	#size-cells = <2>;
	462	#address-cells = <3>;
32f960e9	463	reg = <0xe0008000 0x1000>;
86a04d9c KG	464	compatible = "fsl,mpc8540-pci";
	465	device_type = "pci";
	466	};
	467
	468	/* PCI Express */
ea082fa9 KG	469	pci1: pcie@e000a000 {
ea082fa9 KG	470	cell-index = <2>;
32f960e9	471	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
86a04d9c KG	472	interrupt-map = <
	473
	474	/* IDSEL 0x0 (PEX) */
32f960e9 KG	475	00000 0x0 0x0 0x1 &mpic 0x0 0x1
	476	00000 0x0 0x0 0x2 &mpic 0x1 0x1
	477	00000 0x0 0x0 0x3 &mpic 0x2 0x1
	478	00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
86a04d9c KG	479
86a04d9c KG	480	interrupt-parent = <&mpic>;
32f960e9 KG	481	interrupts = <26 2>;
	482	bus-range = <0 255>;
	483	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
	484	0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
	485	clock-frequency = <33333333>;
86a04d9c KG	486	#interrupt-cells = <1>;
	487	#size-cells = <2>;
	488	#address-cells = <3>;
32f960e9	489	reg = <0xe000a000 0x1000>;
86a04d9c KG	490	compatible = "fsl,mpc8548-pcie";
	491	device_type = "pci";
	492	pcie@0 {
32f960e9	493	reg = <0x0 0x0 0x0 0x0 0x0>;
86a04d9c KG	494	#size-cells = <2>;
	495	#address-cells = <3>;
	496	device_type = "pci";
32f960e9 KG	497	ranges = <0x2000000 0x0 0xa0000000
	498	0x2000000 0x0 0xa0000000
	499	0x0 0x10000000
86a04d9c	500
32f960e9 KG	501	0x1000000 0x0 0x0
	502	0x1000000 0x0 0x0
	503	0x0 0x800000>;
86a04d9c KG	504	};
86a04d9c KG	505	};
c2882bb1	506	};