[linux-2.6-block.git] / arch / powerpc / boot / dts / mpc8378_mds.dts

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8378E MDS Device Tree Source
 *
 * Copyright 2007 Freescale Semiconductor Inc.
 */

/dts-v1/;

/ {
	model = "fsl,mpc8378emds";
	compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8378@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;
			i-cache-size = <32768>;
			timebase-frequency = <0>;
			bus-frequency = <0>;
			clock-frequency = <0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512MB at 0
	};

	localbus@e0005000 {
		#address-cells = <2>;
		#size-cells = <1>;
		compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
		reg = <0xe0005000 0x1000>;
		interrupts = <77 0x8>;
		interrupt-parent = <&ipic>;

		// booting from NOR flash
		ranges = <0 0x0 0xfe000000 0x02000000
		          1 0x0 0xf8000000 0x00008000
		          3 0x0 0xe0600000 0x00008000>;

		flash@0,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0 0x0 0x2000000>;
			bank-width = <2>;
			device-width = <1>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			fs@100000 {
				reg = <0x100000 0x800000>;
			};

			kernel@1d00000 {
				reg = <0x1d00000 0x200000>;
			};

			dtb@1f00000 {
				reg = <0x1f00000 0x100000>;
			};
		};

		bcsr@1,0 {
			reg = <1 0x0 0x8000>;
			compatible = "fsl,mpc837xmds-bcsr";
		};

		nand@3,0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8378-fcm-nand",
			             "fsl,elbc-fcm-nand";
			reg = <3 0x0 0x8000>;

			u-boot@0 {
				reg = <0x0 0x100000>;
				read-only;
			};

			kernel@100000 {
				reg = <0x100000 0x300000>;
			};

			fs@400000 {
				reg = <0x400000 0x1c00000>;
			};
		};
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x00000200>;
		bus-frequency = <0>;

		wdt@200 {
			compatible = "mpc83xx_wdt";
			reg = <0x200 0x100>;
		};

		sleep-nexus {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			sleep = <&pmc 0x0c000000>;
			ranges;

			i2c@3000 {
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				compatible = "fsl-i2c";
				reg = <0x3000 0x100>;
				interrupts = <14 0x8>;
				interrupt-parent = <&ipic>;
				dfsrr;

				rtc@68 {
					compatible = "dallas,ds1374";
					reg = <0x68>;
					interrupts = <19 0x8>;
					interrupt-parent = <&ipic>;
				};
			};

			sdhci@2e000 {
				compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
				reg = <0x2e000 0x1000>;
				interrupts = <42 0x8>;
				interrupt-parent = <&ipic>;
				sdhci,wp-inverted;
				/* Filled in by U-Boot */
				clock-frequency = <0>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <15 0x8>;
			interrupt-parent = <&ipic>;
			dfsrr;
		};

		spi@7000 {
			cell-index = <0>;
			compatible = "fsl,spi";
			reg = <0x7000 0x1000>;
			interrupts = <16 0x8>;
			interrupt-parent = <&ipic>;
			mode = "cpu";
		};

		dma@82a8 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
			reg = <0x82a8 4>;
			ranges = <0 0x8100 0x1a8>;
			interrupt-parent = <&ipic>;
			interrupts = <71 8>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
				reg = <0x180 0x28>;
				cell-index = <3>;
				interrupt-parent = <&ipic>;
				interrupts = <71 8>;
			};
		};

		usb@23000 {
			compatible = "fsl-usb2-dr";
			reg = <0x23000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupt-parent = <&ipic>;
			interrupts = <38 0x8>;
			dr_mode = "host";
			phy_type = "ulpi";
			sleep = <&pmc 0x00c00000>;
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <32 0x8 33 0x8 34 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy2>;
			sleep = <&pmc 0xc0000000>;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy2: ethernet-phy@2 {
					interrupt-parent = <&ipic>;
					interrupts = <17 0x8>;
					reg = <0x2>;
				};

				phy3: ethernet-phy@3 {
					interrupt-parent = <&ipic>;
					interrupts = <18 0x8>;
					reg = <0x3>;
				};

				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "eTSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 0x8 36 0x8 37 0x8>;
			phy-connection-type = "mii";
			interrupt-parent = <&ipic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy3>;
			sleep = <&pmc 0x30000000>;
			fsl,magic-packet;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <9 0x8>;
			interrupt-parent = <&ipic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <10 0x8>;
			interrupt-parent = <&ipic>;
		};

		crypto@30000 {
			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
				     "fsl,sec2.1", "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <11 0x8>;
			interrupt-parent = <&ipic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x9fe>;
			fsl,descriptor-types-mask = <0x3ab0ebf>;
			sleep = <&pmc 0x03000000>;
		};

		/* IPIC
		 * interrupts cell = <intr #, sense>
		 * sense values match linux IORESOURCE_IRQ_* defines:
		 * sense == 8: Level, low assertion
		 * sense == 2: Edge, high-to-low change
		 */
		ipic: pic@700 {
			compatible = "fsl,ipic";
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x700 0x100>;
		};

		pmc: power@b00 {
			compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
			reg = <0xb00 0x100 0xa00 0x100>;
			interrupts = <80 0x8>;
			interrupt-parent = <&ipic>;
		};
	};

	pci0: pci@e0008500 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

				/* IDSEL 0x11 */
				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
				 0x8800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x12 */
				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
				 0x9000 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x13 */
				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
				 0x9800 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x15 */
				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
				 0xa800 0x0 0x0 0x4 &ipic 23 0x8

				/* IDSEL 0x16 */
				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
				 0xb000 0x0 0x0 0x4 &ipic 22 0x8

				/* IDSEL 0x17 */
				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
				 0xb800 0x0 0x0 0x4 &ipic 21 0x8

				/* IDSEL 0x18 */
				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
		interrupt-parent = <&ipic>;
		interrupts = <66 0x8>;
		bus-range = <0x0 0x0>;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
		clock-frequency = <0>;
		sleep = <&pmc 0x00010000>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008500 0x100		/* internal registers */
		       0xe0008300 0x8>;		/* config space access registers */
		compatible = "fsl,mpc8349-pci";
		device_type = "pci";
	};

	pci1: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 1 8
				 0 0 0 2 &ipic 1 8
				 0 0 0 3 &ipic 1 8
				 0 0 0 4 &ipic 1 8>;
		sleep = <&pmc 0x00300000>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xa8000000
				  0x02000000 0 0xa8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};

	pci2: pcie@e000a000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
		reg = <0xe000a000 0x00001000>;
		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0 0 0 1 &ipic 2 8
				 0 0 0 2 &ipic 2 8
				 0 0 0 3 &ipic 2 8
				 0 0 0 4 &ipic 2 8>;
		sleep = <&pmc 0x000c0000>;
		clock-frequency = <0>;

		pcie@0 {
			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";
			reg = <0 0 0 0 0>;
			ranges = <0x02000000 0 0xc8000000
				  0x02000000 0 0xc8000000
				  0 0x10000000
				  0x01000000 0 0x00000000
				  0x01000000 0 0x00000000
				  0 0x00800000>;
		};
	};
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
5761bc5d LY	2	/*
	3	* MPC8378E MDS Device Tree Source
	4	*
	5	* Copyright 2007 Freescale Semiconductor Inc.
5761bc5d LY	6	*/
	7
	8	/dts-v1/;
	9
	10	/ {
	11	model = "fsl,mpc8378emds";
	12	compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
	13	#address-cells = <1>;
	14	#size-cells = <1>;
	15
	16	aliases {
	17	ethernet0 = &enet0;
	18	ethernet1 = &enet1;
	19	serial0 = &serial0;
	20	serial1 = &serial1;
	21	pci0 = &pci0;
0585a155 AV	22	pci1 = &pci1;
0585a155 AV	23	pci2 = &pci2;
5761bc5d LY	24	};
	25
	26	cpus {
	27	#address-cells = <1>;
	28	#size-cells = <0>;
	29
	30	PowerPC,8378@0 {
	31	device_type = "cpu";
cda13dd1 PG	32	reg = <0x0>;
	33	d-cache-line-size = <32>;
	34	i-cache-line-size = <32>;
	35	d-cache-size = <32768>;
	36	i-cache-size = <32768>;
5761bc5d LY	37	timebase-frequency = <0>;
	38	bus-frequency = <0>;
	39	clock-frequency = <0>;
	40	};
	41	};
	42
	43	memory {
	44	device_type = "memory";
	45	reg = <0x00000000 0x20000000>; // 512MB at 0
	46	};
	47
d7f46190 LY	48	localbus@e0005000 {
	49	#address-cells = <2>;
	50	#size-cells = <1>;
	51	compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
	52	reg = <0xe0005000 0x1000>;
	53	interrupts = <77 0x8>;
	54	interrupt-parent = <&ipic>;
	55
	56	// booting from NOR flash
	57	ranges = <0 0x0 0xfe000000 0x02000000
	58	1 0x0 0xf8000000 0x00008000
	59	3 0x0 0xe0600000 0x00008000>;
	60
	61	flash@0,0 {
	62	#address-cells = <1>;
	63	#size-cells = <1>;
	64	compatible = "cfi-flash";
	65	reg = <0 0x0 0x2000000>;
	66	bank-width = <2>;
	67	device-width = <1>;
	68
	69	u-boot@0 {
	70	reg = <0x0 0x100000>;
	71	read-only;
	72	};
	73
	74	fs@100000 {
	75	reg = <0x100000 0x800000>;
	76	};
	77
	78	kernel@1d00000 {
	79	reg = <0x1d00000 0x200000>;
	80	};
	81
	82	dtb@1f00000 {
	83	reg = <0x1f00000 0x100000>;
	84	};
	85	};
	86
	87	bcsr@1,0 {
	88	reg = <1 0x0 0x8000>;
	89	compatible = "fsl,mpc837xmds-bcsr";
	90	};
	91
	92	nand@3,0 {
	93	#address-cells = <1>;
	94	#size-cells = <1>;
	95	compatible = "fsl,mpc8378-fcm-nand",
	96	"fsl,elbc-fcm-nand";
	97	reg = <3 0x0 0x8000>;
	98
	99	u-boot@0 {
	100	reg = <0x0 0x100000>;
	101	read-only;
	102	};
	103
	104	kernel@100000 {
	105	reg = <0x100000 0x300000>;
	106	};
	107
	108	fs@400000 {
	109	reg = <0x400000 0x1c00000>;
	110	};
	111	};
112	};
113
5761bc5d LY	114	soc@e0000000 {
	115	#address-cells = <1>;
	116	#size-cells = <1>;
	117	device_type = "soc";
cf0d19fb	118	compatible = "simple-bus";
5761bc5d LY	119	ranges = <0x0 0xe0000000 0x00100000>;
	120	reg = <0xe0000000 0x00000200>;
	121	bus-frequency = <0>;
	122
	123	wdt@200 {
	124	compatible = "mpc83xx_wdt";
	125	reg = <0x200 0x100>;
	126	};
	127
125a00d7	128	sleep-nexus {
5761bc5d	129	#address-cells = <1>;
125a00d7 AV	130	#size-cells = <1>;
	131	compatible = "simple-bus";
	132	sleep = <&pmc 0x0c000000>;
	133	ranges;
8b77aeb4	134
125a00d7 AV	135	i2c@3000 {
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138	cell-index = <0>;
	139	compatible = "fsl-i2c";
	140	reg = <0x3000 0x100>;
	141	interrupts = <14 0x8>;
8b77aeb4	142	interrupt-parent = <&ipic>;
125a00d7 AV	143	dfsrr;
	144
	145	rtc@68 {
	146	compatible = "dallas,ds1374";
	147	reg = <0x68>;
	148	interrupts = <19 0x8>;
	149	interrupt-parent = <&ipic>;
	150	};
	151	};
	152
	153	sdhci@2e000 {
1a2eceaa	154	compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
125a00d7 AV	155	reg = <0x2e000 0x1000>;
	156	interrupts = <42 0x8>;
	157	interrupt-parent = <&ipic>;
50dfe70f	158	sdhci,wp-inverted;
125a00d7 AV	159	/* Filled in by U-Boot */
125a00d7 AV	160	clock-frequency = <0>;
8b77aeb4	161	};
5761bc5d LY	162	};
	163
	164	i2c@3100 {
	165	#address-cells = <1>;
	166	#size-cells = <0>;
	167	cell-index = <1>;
	168	compatible = "fsl-i2c";
	169	reg = <0x3100 0x100>;
cda13dd1 PG	170	interrupts = <15 0x8>;
cda13dd1 PG	171	interrupt-parent = <&ipic>;
5761bc5d LY	172	dfsrr;
	173	};
	174
	175	spi@7000 {
f3a2b29d AV	176	cell-index = <0>;
f3a2b29d AV	177	compatible = "fsl,spi";
5761bc5d	178	reg = <0x7000 0x1000>;
cda13dd1 PG	179	interrupts = <16 0x8>;
cda13dd1 PG	180	interrupt-parent = <&ipic>;
5761bc5d LY	181	mode = "cpu";
	182	};
	183
dee80553 KG	184	dma@82a8 {
	185	#address-cells = <1>;
	186	#size-cells = <1>;
	187	compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
	188	reg = <0x82a8 4>;
	189	ranges = <0 0x8100 0x1a8>;
	190	interrupt-parent = <&ipic>;
	191	interrupts = <71 8>;
	192	cell-index = <0>;
	193	dma-channel@0 {
	194	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	195	reg = <0 0x80>;
aeb42762	196	cell-index = <0>;
dee80553 KG	197	interrupt-parent = <&ipic>;
	198	interrupts = <71 8>;
	199	};
	200	dma-channel@80 {
	201	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	202	reg = <0x80 0x80>;
aeb42762	203	cell-index = <1>;
dee80553 KG	204	interrupt-parent = <&ipic>;
	205	interrupts = <71 8>;
	206	};
	207	dma-channel@100 {
	208	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	209	reg = <0x100 0x80>;
aeb42762	210	cell-index = <2>;
dee80553 KG	211	interrupt-parent = <&ipic>;
	212	interrupts = <71 8>;
	213	};
	214	dma-channel@180 {
	215	compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
	216	reg = <0x180 0x28>;
aeb42762	217	cell-index = <3>;
dee80553 KG	218	interrupt-parent = <&ipic>;
	219	interrupts = <71 8>;
	220	};
	221	};
	222
5761bc5d LY	223	usb@23000 {
	224	compatible = "fsl-usb2-dr";
	225	reg = <0x23000 0x1000>;
	226	#address-cells = <1>;
	227	#size-cells = <0>;
cda13dd1 PG	228	interrupt-parent = <&ipic>;
cda13dd1 PG	229	interrupts = <38 0x8>;
28b95885 LY	230	dr_mode = "host";
28b95885 LY	231	phy_type = "ulpi";
125a00d7	232	sleep = <&pmc 0x00c00000>;
5761bc5d LY	233	};
5761bc5d LY	234
5761bc5d	235	enet0: ethernet@24000 {
70b3adbb AV	236	#address-cells = <1>;
70b3adbb AV	237	#size-cells = <1>;
5761bc5d LY	238	cell-index = <0>;
	239	device_type = "network";
	240	model = "eTSEC";
	241	compatible = "gianfar";
	242	reg = <0x24000 0x1000>;
70b3adbb	243	ranges = <0x0 0x24000 0x1000>;
5761bc5d	244	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	245	interrupts = <32 0x8 33 0x8 34 0x8>;
5761bc5d	246	phy-connection-type = "mii";
cda13dd1	247	interrupt-parent = <&ipic>;
b31a1d8b	248	tbi-handle = <&tbi0>;
cda13dd1	249	phy-handle = <&phy2>;
125a00d7 AV	250	sleep = <&pmc 0xc0000000>;
125a00d7 AV	251	fsl,magic-packet;
70b3adbb AV	252
	253	mdio@520 {
	254	#address-cells = <1>;
	255	#size-cells = <0>;
	256	compatible = "fsl,gianfar-mdio";
	257	reg = <0x520 0x20>;
	258
	259	phy2: ethernet-phy@2 {
	260	interrupt-parent = <&ipic>;
	261	interrupts = <17 0x8>;
	262	reg = <0x2>;
70b3adbb AV	263	};
	264
	265	phy3: ethernet-phy@3 {
	266	interrupt-parent = <&ipic>;
	267	interrupts = <18 0x8>;
	268	reg = <0x3>;
70b3adbb AV	269	};
	270
	271	tbi0: tbi-phy@11 {
	272	reg = <0x11>;
	273	device_type = "tbi-phy";
	274	};
	275	};
5761bc5d LY	276	};
	277
	278	enet1: ethernet@25000 {
70b3adbb AV	279	#address-cells = <1>;
70b3adbb AV	280	#size-cells = <1>;
5761bc5d LY	281	cell-index = <1>;
	282	device_type = "network";
	283	model = "eTSEC";
	284	compatible = "gianfar";
	285	reg = <0x25000 0x1000>;
70b3adbb	286	ranges = <0x0 0x25000 0x1000>;
5761bc5d	287	local-mac-address = [ 00 00 00 00 00 00 ];
cda13dd1	288	interrupts = <35 0x8 36 0x8 37 0x8>;
5761bc5d	289	phy-connection-type = "mii";
cda13dd1	290	interrupt-parent = <&ipic>;
b31a1d8b	291	tbi-handle = <&tbi1>;
cda13dd1	292	phy-handle = <&phy3>;
125a00d7 AV	293	sleep = <&pmc 0x30000000>;
125a00d7 AV	294	fsl,magic-packet;
70b3adbb AV	295
	296	mdio@520 {
	297	#address-cells = <1>;
	298	#size-cells = <0>;
	299	compatible = "fsl,gianfar-tbi";
	300	reg = <0x520 0x20>;
	301
	302	tbi1: tbi-phy@11 {
	303	reg = <0x11>;
	304	device_type = "tbi-phy";
	305	};
	306	};
5761bc5d LY	307	};
	308
	309	serial0: serial@4500 {
	310	cell-index = <0>;
	311	device_type = "serial";
f706bed1	312	compatible = "fsl,ns16550", "ns16550";
5761bc5d LY	313	reg = <0x4500 0x100>;
5761bc5d LY	314	clock-frequency = <0>;
cda13dd1 PG	315	interrupts = <9 0x8>;
cda13dd1 PG	316	interrupt-parent = <&ipic>;
5761bc5d LY	317	};
	318
	319	serial1: serial@4600 {
	320	cell-index = <1>;
	321	device_type = "serial";
f706bed1	322	compatible = "fsl,ns16550", "ns16550";
5761bc5d LY	323	reg = <0x4600 0x100>;
5761bc5d LY	324	clock-frequency = <0>;
cda13dd1 PG	325	interrupts = <10 0x8>;
cda13dd1 PG	326	interrupt-parent = <&ipic>;
5761bc5d LY	327	};
	328
	329	crypto@30000 {
3fd44736 KP	330	compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
3fd44736 KP	331	"fsl,sec2.1", "fsl,sec2.0";
5761bc5d	332	reg = <0x30000 0x10000>;
cda13dd1 PG	333	interrupts = <11 0x8>;
cda13dd1 PG	334	interrupt-parent = <&ipic>;
3fd44736 KP	335	fsl,num-channels = <4>;
	336	fsl,channel-fifo-len = <24>;
	337	fsl,exec-units-mask = <0x9fe>;
	338	fsl,descriptor-types-mask = <0x3ab0ebf>;
125a00d7	339	sleep = <&pmc 0x03000000>;
5761bc5d LY	340	};
	341
	342	/* IPIC
	343	* interrupts cell = <intr #, sense>
	344	* sense values match linux IORESOURCE_IRQ_* defines:
	345	* sense == 8: Level, low assertion
	346	* sense == 2: Edge, high-to-low change
	347	*/
	348	ipic: pic@700 {
	349	compatible = "fsl,ipic";
	350	interrupt-controller;
	351	#address-cells = <0>;
	352	#interrupt-cells = <2>;
	353	reg = <0x700 0x100>;
	354	};
125a00d7 AV	355
	356	pmc: power@b00 {
	357	compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
	358	reg = <0xb00 0x100 0xa00 0x100>;
	359	interrupts = <80 0x8>;
	360	interrupt-parent = <&ipic>;
	361	};
5761bc5d LY	362	};
	363
	364	pci0: pci@e0008500 {
5761bc5d LY	365	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
	366	interrupt-map = <
	367
	368	/* IDSEL 0x11 */
cda13dd1 PG	369	0x8800 0x0 0x0 0x1 &ipic 20 0x8
	370	0x8800 0x0 0x0 0x2 &ipic 21 0x8
	371	0x8800 0x0 0x0 0x3 &ipic 22 0x8
	372	0x8800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	373
5761bc5d LY	374	/* IDSEL 0x12 */
cda13dd1 PG	375	0x9000 0x0 0x0 0x1 &ipic 22 0x8
	376	0x9000 0x0 0x0 0x2 &ipic 23 0x8
	377	0x9000 0x0 0x0 0x3 &ipic 20 0x8
	378	0x9000 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	379
5761bc5d LY	380	/* IDSEL 0x13 */
cda13dd1 PG	381	0x9800 0x0 0x0 0x1 &ipic 23 0x8
	382	0x9800 0x0 0x0 0x2 &ipic 20 0x8
	383	0x9800 0x0 0x0 0x3 &ipic 21 0x8
	384	0x9800 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	385
5761bc5d LY	386	/* IDSEL 0x15 */
cda13dd1 PG	387	0xa800 0x0 0x0 0x1 &ipic 20 0x8
	388	0xa800 0x0 0x0 0x2 &ipic 21 0x8
	389	0xa800 0x0 0x0 0x3 &ipic 22 0x8
	390	0xa800 0x0 0x0 0x4 &ipic 23 0x8
5761bc5d LY	391
5761bc5d LY	392	/* IDSEL 0x16 */
cda13dd1 PG	393	0xb000 0x0 0x0 0x1 &ipic 23 0x8
	394	0xb000 0x0 0x0 0x2 &ipic 20 0x8
	395	0xb000 0x0 0x0 0x3 &ipic 21 0x8
	396	0xb000 0x0 0x0 0x4 &ipic 22 0x8
5761bc5d LY	397
5761bc5d LY	398	/* IDSEL 0x17 */
cda13dd1 PG	399	0xb800 0x0 0x0 0x1 &ipic 22 0x8
	400	0xb800 0x0 0x0 0x2 &ipic 23 0x8
	401	0xb800 0x0 0x0 0x3 &ipic 20 0x8
	402	0xb800 0x0 0x0 0x4 &ipic 21 0x8
5761bc5d LY	403
5761bc5d LY	404	/* IDSEL 0x18 */
cda13dd1 PG	405	0xc000 0x0 0x0 0x1 &ipic 21 0x8
	406	0xc000 0x0 0x0 0x2 &ipic 22 0x8
	407	0xc000 0x0 0x0 0x3 &ipic 23 0x8
	408	0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
	409	interrupt-parent = <&ipic>;
	410	interrupts = <66 0x8>;
	411	bus-range = <0x0 0x0>;
5761bc5d LY	412	ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
	413	0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
	414	0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
	415	clock-frequency = <0>;
125a00d7	416	sleep = <&pmc 0x00010000>;
5761bc5d LY	417	#interrupt-cells = <1>;
	418	#size-cells = <2>;
	419	#address-cells = <3>;
5b70a097 JR	420	reg = <0xe0008500 0x100 /* internal registers */
5b70a097 JR	421	0xe0008300 0x8>; /* config space access registers */
5761bc5d LY	422	compatible = "fsl,mpc8349-pci";
	423	device_type = "pci";
	424	};
0585a155 AV	425
	426	pci1: pcie@e0009000 {
	427	#address-cells = <3>;
	428	#size-cells = <2>;
	429	#interrupt-cells = <1>;
	430	device_type = "pci";
	431	compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
	432	reg = <0xe0009000 0x00001000>;
	433	ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
	434	0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
	435	bus-range = <0 255>;
	436	interrupt-map-mask = <0xf800 0 0 7>;
	437	interrupt-map = <0 0 0 1 &ipic 1 8
	438	0 0 0 2 &ipic 1 8
	439	0 0 0 3 &ipic 1 8
	440	0 0 0 4 &ipic 1 8>;
125a00d7	441	sleep = <&pmc 0x00300000>;
0585a155 AV	442	clock-frequency = <0>;
	443
	444	pcie@0 {
	445	#address-cells = <3>;
	446	#size-cells = <2>;
	447	device_type = "pci";
	448	reg = <0 0 0 0 0>;
	449	ranges = <0x02000000 0 0xa8000000
	450	0x02000000 0 0xa8000000
	451	0 0x10000000
	452	0x01000000 0 0x00000000
	453	0x01000000 0 0x00000000
	454	0 0x00800000>;
	455	};
	456	};
	457
	458	pci2: pcie@e000a000 {
	459	#address-cells = <3>;
	460	#size-cells = <2>;
	461	#interrupt-cells = <1>;
	462	device_type = "pci";
	463	compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
	464	reg = <0xe000a000 0x00001000>;
	465	ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
	466	0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
	467	bus-range = <0 255>;
	468	interrupt-map-mask = <0xf800 0 0 7>;
	469	interrupt-map = <0 0 0 1 &ipic 2 8
	470	0 0 0 2 &ipic 2 8
	471	0 0 0 3 &ipic 2 8
	472	0 0 0 4 &ipic 2 8>;
125a00d7	473	sleep = <&pmc 0x000c0000>;
0585a155 AV	474	clock-frequency = <0>;
	475
	476	pcie@0 {
	477	#address-cells = <3>;
	478	#size-cells = <2>;
	479	device_type = "pci";
	480	reg = <0 0 0 0 0>;
	481	ranges = <0x02000000 0 0xc8000000
	482	0x02000000 0 0xc8000000
	483	0 0x10000000
	484	0x01000000 0 0x00000000
	485	0x01000000 0 0x00000000
	486	0 0x00800000>;
	487	};
	488	};
5761bc5d	489	};