[linux-2.6-block.git] / arch / powerpc / boot / dts / makalu.dts

/*
 * Device Tree Source for AMCC Makalu (405EX)
 *
 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without
 * any warranty of any kind, whether express or implied.
 */

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "amcc,makalu";
	compatible = "amcc,makalu";
	dcr-parent = <&/cpus/cpu@0>;

	aliases {
		ethernet0 = &EMAC0;
		ethernet1 = &EMAC1;
		serial0 = &UART0;
		serial1 = &UART1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,405EX";
			reg = <0>;
			clock-frequency = <0>; /* Filled in by U-Boot */
			timebase-frequency = <0>; /* Filled in by U-Boot */
			i-cache-line-size = <20>;
			d-cache-line-size = <20>;
			i-cache-size = <4000>; /* 16 kB */
			d-cache-size = <4000>; /* 16 kB */
			dcr-controller;
			dcr-access-method = "native";
		};
	};

	memory {
		device_type = "memory";
		reg = <0 0>; /* Filled in by U-Boot */
	};

	UIC0: interrupt-controller {
		compatible = "ibm,uic-405ex", "ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0c0 009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-405ex","ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0d0 009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <1e 4 1f 4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC2: interrupt-controller2 {
		compatible = "ibm,uic-405ex","ibm,uic";
		interrupt-controller;
		cell-index = <2>;
		dcr-reg = <0e0 009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <1c 4 1d 4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	plb {
		compatible = "ibm,plb-405ex", "ibm,plb4";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		clock-frequency = <0>; /* Filled in by U-Boot */

		SDRAM0: memory-controller {
			compatible = "ibm,sdram-405ex";
			dcr-reg = <010 2>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
			dcr-reg = <180 62>;
			num-tx-chans = <2>;
			num-rx-chans = <2>;
			interrupt-parent = <&MAL0>;
			interrupts = <0 1 2 3 4>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
					/*RXEOB*/ 1 &UIC0 b 4
					/*SERR*/  2 &UIC1 0 4
					/*TXDE*/  3 &UIC1 1 4
					/*RXDE*/  4 &UIC1 2 4>;
			interrupt-map-mask = <ffffffff>;
		};

		POB0: opb {
			compatible = "ibm,opb-405ex", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <80000000 80000000 10000000
				  ef600000 ef600000 a00000
				  f0000000 f0000000 10000000>;
			dcr-reg = <0a0 5>;
			clock-frequency = <0>; /* Filled in by U-Boot */

			EBC0: ebc {
				compatible = "ibm,ebc-405ex", "ibm,ebc";
				dcr-reg = <012 2>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				/* ranges property is supplied by U-Boot */
				interrupts = <5 1>;
				interrupt-parent = <&UIC1>;

				nor_flash@0,0 {
					compatible = "amd,s29gl512n", "cfi-flash";
					bank-width = <2>;
					reg = <0 000000 4000000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "kernel";
						reg = <0 200000>;
					};
					partition@200000 {
						label = "root";
						reg = <200000 200000>;
					};
					partition@400000 {
						label = "user";
						reg = <400000 3b60000>;
					};
					partition@3f60000 {
						label = "env";
						reg = <3f60000 40000>;
					};
					partition@3fa0000 {
						label = "u-boot";
						reg = <3fa0000 60000>;
					};
				};
			};

			UART0: serial@ef600200 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <ef600200 8>;
				virtual-reg = <ef600200>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <1a 4>;
			};

			UART1: serial@ef600300 {
				device_type = "serial";
				compatible = "ns16550";
				reg = <ef600300 8>;
				virtual-reg = <ef600300>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>;
				interrupt-parent = <&UIC0>;
				interrupts = <1 4>;
			};

			IIC0: i2c@ef600400 {
				compatible = "ibm,iic-405ex", "ibm,iic";
				reg = <ef600400 14>;
				interrupt-parent = <&UIC0>;
				interrupts = <2 4>;
			};

			IIC1: i2c@ef600500 {
				compatible = "ibm,iic-405ex", "ibm,iic";
				reg = <ef600500 14>;
				interrupt-parent = <&UIC0>;
				interrupts = <7 4>;
			};


			RGMII0: emac-rgmii@ef600b00 {
				compatible = "ibm,rgmii-405ex", "ibm,rgmii";
				reg = <ef600b00 104>;
				has-mdio;
			};

			EMAC0: ethernet@ef600900 {
				linux,network-index = <0>;
				device_type = "network";
				compatible = "ibm,emac-405ex", "ibm,emac4";
				interrupt-parent = <&EMAC0>;
				interrupts = <0 1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0 &UIC0 18 4
						/*Wake*/  1 &UIC1 1d 4>;
				reg = <ef600900 70>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <0>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <2328>;
				rx-fifo-size = <1000>;
				tx-fifo-size = <800>;
				phy-mode = "rgmii";
				phy-map = <0000003f>;	/* Start at 6 */
				rgmii-device = <&RGMII0>;
				rgmii-channel = <0>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};

			EMAC1: ethernet@ef600a00 {
				linux,network-index = <1>;
				device_type = "network";
				compatible = "ibm,emac-405ex", "ibm,emac4";
				interrupt-parent = <&EMAC1>;
				interrupts = <0 1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0 &UIC0 19 4
						/*Wake*/  1 &UIC1 1f 4>;
				reg = <ef600a00 70>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <1>;
				mal-rx-channel = <1>;
				cell-index = <1>;
				max-frame-size = <2328>;
				rx-fifo-size = <1000>;
				tx-fifo-size = <800>;
				phy-mode = "rgmii";
				phy-map = <00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <1>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};
		};

		PCIE0: pciex@0a0000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
			primary;
			port = <0>; /* port number */
			reg = <a0000000 20000000	/* Config space access */
			       ef000000 00001000>;	/* Registers */
			dcr-reg = <040 020>;
			sdr-base = <400>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <02000000 0 80000000 90000000 0 08000000
				  01000000 0 00000000 e0000000 0 00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <42000000 0 0 0 0 80000000>;

			/* This drives busses 0x00 to 0x3f */
			bus-range = <00 3f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0000 0 0 7>;
			interrupt-map = <
				0000 0 0 1 &UIC2 0 4 /* swizzled int A */
				0000 0 0 2 &UIC2 1 4 /* swizzled int B */
				0000 0 0 3 &UIC2 2 4 /* swizzled int C */
				0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
		};

		PCIE1: pciex@0c0000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
			primary;
			port = <1>; /* port number */
			reg = <c0000000 20000000	/* Config space access */
			       ef001000 00001000>;	/* Registers */
			dcr-reg = <060 020>;
			sdr-base = <440>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <02000000 0 80000000 98000000 0 08000000
				  01000000 0 00000000 e0010000 0 00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <42000000 0 0 0 0 80000000>;

			/* This drives busses 0x40 to 0x7f */
			bus-range = <40 7f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0000 0 0 7>;
			interrupt-map = <
				0000 0 0 1 &UIC2 b 4 /* swizzled int A */
				0000 0 0 2 &UIC2 c 4 /* swizzled int B */
				0000 0 0 3 &UIC2 d 4 /* swizzled int C */
				0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
		};
	};
};
Commit	Line	Data
1b55883a SR	1	/*
	2	* Device Tree Source for AMCC Makalu (405EX)
	3	*
	4	* Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
	5	*
	6	* This file is licensed under the terms of the GNU General Public
	7	* License version 2. This program is licensed "as is" without
	8	* any warranty of any kind, whether express or implied.
	9	*/
	10
	11	/ {
	12	#address-cells = <1>;
	13	#size-cells = <1>;
	14	model = "amcc,makalu";
	15	compatible = "amcc,makalu";
	16	dcr-parent = <&/cpus/cpu@0>;
	17
	18	aliases {
	19	ethernet0 = &EMAC0;
	20	ethernet1 = &EMAC1;
	21	serial0 = &UART0;
	22	serial1 = &UART1;
	23	};
	24
	25	cpus {
	26	#address-cells = <1>;
	27	#size-cells = <0>;
	28
	29	cpu@0 {
	30	device_type = "cpu";
	31	model = "PowerPC,405EX";
	32	reg = <0>;
	33	clock-frequency = <0>; /* Filled in by U-Boot */
	34	timebase-frequency = <0>; /* Filled in by U-Boot */
	35	i-cache-line-size = <20>;
	36	d-cache-line-size = <20>;
	37	i-cache-size = <4000>; /* 16 kB */
	38	d-cache-size = <4000>; /* 16 kB */
	39	dcr-controller;
	40	dcr-access-method = "native";
	41	};
	42	};
	43
	44	memory {
	45	device_type = "memory";
	46	reg = <0 0>; /* Filled in by U-Boot */
	47	};
	48
	49	UIC0: interrupt-controller {
	50	compatible = "ibm,uic-405ex", "ibm,uic";
	51	interrupt-controller;
	52	cell-index = <0>;
	53	dcr-reg = <0c0 009>;
	54	#address-cells = <0>;
	55	#size-cells = <0>;
	56	#interrupt-cells = <2>;
	57	};
	58
	59	UIC1: interrupt-controller1 {
	60	compatible = "ibm,uic-405ex","ibm,uic";
	61	interrupt-controller;
	62	cell-index = <1>;
	63	dcr-reg = <0d0 009>;
	64	#address-cells = <0>;
65	#size-cells = <0>;
66	#interrupt-cells = <2>;
67	interrupts = <1e 4 1f 4>; /* cascade */
68	interrupt-parent = <&UIC0>;
69	};
70
71	UIC2: interrupt-controller2 {
72	compatible = "ibm,uic-405ex","ibm,uic";
73	interrupt-controller;
74	cell-index = <2>;
75	dcr-reg = <0e0 009>;
76	#address-cells = <0>;
77	#size-cells = <0>;
78	#interrupt-cells = <2>;
79	interrupts = <1c 4 1d 4>; /* cascade */
80	interrupt-parent = <&UIC0>;
81	};
82
83	plb {
84	compatible = "ibm,plb-405ex", "ibm,plb4";
85	#address-cells = <1>;
86	#size-cells = <1>;
87	ranges;
88	clock-frequency = <0>; /* Filled in by U-Boot */
89
90	SDRAM0: memory-controller {
91	compatible = "ibm,sdram-405ex";
92	dcr-reg = <010 2>;
93	};
94
95	MAL0: mcmal {
96	compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
97	dcr-reg = <180 62>;
98	num-tx-chans = <2>;
99	num-rx-chans = <2>;
100	interrupt-parent = <&MAL0>;
101	interrupts = <0 1 2 3 4>;
102	#interrupt-cells = <1>;
103	#address-cells = <0>;
104	#size-cells = <0>;
105	interrupt-map = </TXEOB/ 0 &UIC0 a 4
106	/RXEOB/ 1 &UIC0 b 4
107	/SERR/ 2 &UIC1 0 4
108	/TXDE/ 3 &UIC1 1 4
109	/RXDE/ 4 &UIC1 2 4>;
110	interrupt-map-mask = <ffffffff>;
111	};
112
113	POB0: opb {
114	compatible = "ibm,opb-405ex", "ibm,opb";
115	#address-cells = <1>;
116	#size-cells = <1>;
117	ranges = <80000000 80000000 10000000
118	ef600000 ef600000 a00000
119	f0000000 f0000000 10000000>;
120	dcr-reg = <0a0 5>;
121	clock-frequency = <0>; /* Filled in by U-Boot */
122
123	EBC0: ebc {
124	compatible = "ibm,ebc-405ex", "ibm,ebc";
125	dcr-reg = <012 2>;
126	#address-cells = <2>;
127	#size-cells = <1>;
128	clock-frequency = <0>; /* Filled in by U-Boot */
129	/* ranges property is supplied by U-Boot */
130	interrupts = <5 1>;
131	interrupt-parent = <&UIC1>;
132
133	nor_flash@0,0 {
134	compatible = "amd,s29gl512n", "cfi-flash";
135	bank-width = <2>;
136	reg = <0 000000 4000000>;
137	#address-cells = <1>;
138	#size-cells = <1>;
139	partition@0 {
140	label = "kernel";
141	reg = <0 200000>;
142	};
143	partition@200000 {
144	label = "root";
145	reg = <200000 200000>;
146	};
147	partition@400000 {
148	label = "user";
149	reg = <400000 3b60000>;
150	};
151	partition@3f60000 {
152	label = "env";
153	reg = <3f60000 40000>;
154	};
155	partition@3fa0000 {
156	label = "u-boot";
157	reg = <3fa0000 60000>;
158	};
159	};
160	};
161
162	UART0: serial@ef600200 {
163	device_type = "serial";
164	compatible = "ns16550";
165	reg = <ef600200 8>;
166	virtual-reg = <ef600200>;
167	clock-frequency = <0>; /* Filled in by U-Boot */
168	current-speed = <0>;
169	interrupt-parent = <&UIC0>;
170	interrupts = <1a 4>;
171	};
172
173	UART1: serial@ef600300 {
174	device_type = "serial";
175	compatible = "ns16550";
176	reg = <ef600300 8>;
177	virtual-reg = <ef600300>;
178	clock-frequency = <0>; /* Filled in by U-Boot */
179	current-speed = <0>;
180	interrupt-parent = <&UIC0>;
181	interrupts = <1 4>;
182	};
183
184	IIC0: i2c@ef600400 {
1b55883a SR	185	compatible = "ibm,iic-405ex", "ibm,iic";
	186	reg = <ef600400 14>;
	187	interrupt-parent = <&UIC0>;
	188	interrupts = <2 4>;
	189	};
	190
	191	IIC1: i2c@ef600500 {
1b55883a SR	192	compatible = "ibm,iic-405ex", "ibm,iic";
	193	reg = <ef600500 14>;
	194	interrupt-parent = <&UIC0>;
	195	interrupts = <7 4>;
	196	};
	197
	198
	199	RGMII0: emac-rgmii@ef600b00 {
1b55883a SR	200	compatible = "ibm,rgmii-405ex", "ibm,rgmii";
	201	reg = <ef600b00 104>;
	202	has-mdio;
	203	};
	204
	205	EMAC0: ethernet@ef600900 {
	206	linux,network-index = <0>;
	207	device_type = "network";
	208	compatible = "ibm,emac-405ex", "ibm,emac4";
	209	interrupt-parent = <&EMAC0>;
	210	interrupts = <0 1>;
	211	#interrupt-cells = <1>;
	212	#address-cells = <0>;
	213	#size-cells = <0>;
	214	interrupt-map = </Status/ 0 &UIC0 18 4
	215	/Wake/ 1 &UIC1 1d 4>;
	216	reg = <ef600900 70>;
	217	local-mac-address = [000000000000]; /* Filled in by U-Boot */
	218	mal-device = <&MAL0>;
	219	mal-tx-channel = <0>;
	220	mal-rx-channel = <0>;
	221	cell-index = <0>;
9d7030be	222	max-frame-size = <2328>;
1b55883a SR	223	rx-fifo-size = <1000>;
	224	tx-fifo-size = <800>;
	225	phy-mode = "rgmii";
	226	phy-map = <0000003f>; /* Start at 6 */
	227	rgmii-device = <&RGMII0>;
	228	rgmii-channel = <0>;
	229	has-inverted-stacr-oc;
	230	has-new-stacr-staopc;
	231	};
	232
	233	EMAC1: ethernet@ef600a00 {
	234	linux,network-index = <1>;
	235	device_type = "network";
	236	compatible = "ibm,emac-405ex", "ibm,emac4";
	237	interrupt-parent = <&EMAC1>;
	238	interrupts = <0 1>;
	239	#interrupt-cells = <1>;
	240	#address-cells = <0>;
	241	#size-cells = <0>;
	242	interrupt-map = </Status/ 0 &UIC0 19 4
	243	/Wake/ 1 &UIC1 1f 4>;
	244	reg = <ef600a00 70>;
	245	local-mac-address = [000000000000]; /* Filled in by U-Boot */
	246	mal-device = <&MAL0>;
	247	mal-tx-channel = <1>;
	248	mal-rx-channel = <1>;
	249	cell-index = <1>;
9d7030be	250	max-frame-size = <2328>;
1b55883a SR	251	rx-fifo-size = <1000>;
	252	tx-fifo-size = <800>;
	253	phy-mode = "rgmii";
	254	phy-map = <00000000>;
	255	rgmii-device = <&RGMII0>;
	256	rgmii-channel = <1>;
	257	has-inverted-stacr-oc;
	258	has-new-stacr-staopc;
	259	};
	260	};
	261
	262	PCIE0: pciex@0a0000000 {
	263	device_type = "pci";
	264	#interrupt-cells = <1>;
	265	#size-cells = <2>;
	266	#address-cells = <3>;
	267	compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
	268	primary;
	269	port = <0>; /* port number */
	270	reg = <a0000000 20000000 /* Config space access */
	271	ef000000 00001000>; /* Registers */
	272	dcr-reg = <040 020>;
	273	sdr-base = <400>;
	274
	275	/* Outbound ranges, one memory and one IO,
	276	* later cannot be changed
	277	*/
	278	ranges = <02000000 0 80000000 90000000 0 08000000
	279	01000000 0 00000000 e0000000 0 00010000>;
	280
	281	/* Inbound 2GB range starting at 0 */
	282	dma-ranges = <42000000 0 0 0 0 80000000>;
	283
	284	/* This drives busses 0x00 to 0x3f */
	285	bus-range = <00 3f>;
	286
	287	/* Legacy interrupts (note the weird polarity, the bridge seems
	288	* to invert PCIe legacy interrupts).
	289	* We are de-swizzling here because the numbers are actually for
	290	* port of the root complex virtual P2P bridge. But I want
	291	* to avoid putting a node for it in the tree, so the numbers
	292	* below are basically de-swizzled numbers.
	293	* The real slot is on idsel 0, so the swizzling is 1:1
	294	*/
	295	interrupt-map-mask = <0000 0 0 7>;
	296	interrupt-map = <
	297	0000 0 0 1 &UIC2 0 4 /* swizzled int A */
	298	0000 0 0 2 &UIC2 1 4 /* swizzled int B */
	299	0000 0 0 3 &UIC2 2 4 /* swizzled int C */
	300	0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
	301	};
	302
	303	PCIE1: pciex@0c0000000 {
	304	device_type = "pci";
	305	#interrupt-cells = <1>;
	306	#size-cells = <2>;
	307	#address-cells = <3>;
	308	compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
	309	primary;
	310	port = <1>; /* port number */
	311	reg = <c0000000 20000000 /* Config space access */
	312	ef001000 00001000>; /* Registers */
	313	dcr-reg = <060 020>;
	314	sdr-base = <440>;
315
316	/* Outbound ranges, one memory and one IO,
317	* later cannot be changed
318	*/
319	ranges = <02000000 0 80000000 98000000 0 08000000
320	01000000 0 00000000 e0010000 0 00010000>;
321
322	/* Inbound 2GB range starting at 0 */
323	dma-ranges = <42000000 0 0 0 0 80000000>;
324
325	/* This drives busses 0x40 to 0x7f */
326	bus-range = <40 7f>;
327
328	/* Legacy interrupts (note the weird polarity, the bridge seems
329	* to invert PCIe legacy interrupts).
330	* We are de-swizzling here because the numbers are actually for
331	* port of the root complex virtual P2P bridge. But I want
332	* to avoid putting a node for it in the tree, so the numbers
333	* below are basically de-swizzled numbers.
334	* The real slot is on idsel 0, so the swizzling is 1:1
335	*/
336	interrupt-map-mask = <0000 0 0 7>;
337	interrupt-map = <
338	0000 0 0 1 &UIC2 b 4 /* swizzled int A */
339	0000 0 0 2 &UIC2 c 4 /* swizzled int B */
340	0000 0 0 3 &UIC2 d 4 /* swizzled int C */
341	0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
342	};
343	};
344	};