[linux-block.git] / arch / powerpc / boot / dts / fsl / p1022si-post.dtsi

/*
 * P1022/P1013 Silicon/SoC Device Tree Source (post include)
 *
 * Copyright 2011 Freescale Semiconductor Inc.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
 *     * Neither the name of Freescale Semiconductor nor the
 *       names of its contributors may be used to endorse or promote products
 *       derived from this software without specific prior written permission.
 *
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") as published by the Free Software
 * Foundation, either version 2 of that License or (at your option) any
 * later version.
 *
 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

&lbc {
	#address-cells = <2>;
	#size-cells = <1>;
	/*
	 * The localbus on the P1022 is not a simple-bus because of the eLBC
	 * pin muxing when the DIU is enabled.
	 */
	compatible = "fsl,p1022-elbc", "fsl,elbc";
	interrupts = <19 2 0 0>,
		     <16 2 0 0>;
};

/* controller at 0x9000 */
&pci0 {
	compatible = "fsl,mpc8548-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0 255>;
	clock-frequency = <33333333>;
	interrupts = <16 2 0 0>;

	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
			0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
			0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
			0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
			>;
	};
};

/* controller at 0xa000 */
&pci1 {
	compatible = "fsl,mpc8548-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0 255>;
	clock-frequency = <33333333>;
	interrupts = <16 2 0 0>;

	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
			0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
			0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
			0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
			>;
	};
};

/* controller at 0xb000 */
&pci2 {
	compatible = "fsl,mpc8548-pcie";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0 255>;
	clock-frequency = <33333333>;
	interrupts = <16 2 0 0>;

	pcie@0 {
		reg = <0 0 0 0 0>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		interrupts = <16 2 0 0>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x0 */
			0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
			0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
			0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
			0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
			>;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "fsl,p1022-immr", "simple-bus";
	bus-frequency = <0>;		// Filled out by uboot.

	ecm-law@0 {
		compatible = "fsl,ecm-law";
		reg = <0x0 0x1000>;
		fsl,num-laws = <12>;
	};

	ecm@1000 {
		compatible = "fsl,p1022-ecm", "fsl,ecm";
		reg = <0x1000 0x1000>;
		interrupts = <16 2 0 0>;
	};

	memory-controller@2000 {
		compatible = "fsl,p1022-memory-controller";
		reg = <0x2000 0x1000>;
		interrupts = <16 2 0 0>;
	};

/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-duart-0.dtsi"
/include/ "pq3-espi-0.dtsi"
	spi@7000 {
		fsl,espi-num-chipselects = <4>;
	};

/include/ "pq3-dma-1.dtsi"
	dma@c300 {
		dma00: dma-channel@0 {
			compatible = "fsl,ssi-dma-channel";
		};
		dma01: dma-channel@80 {
			compatible = "fsl,ssi-dma-channel";
		};
	};

/include/ "pq3-gpio-0.dtsi"

	display: display@10000 {
		compatible = "fsl,diu", "fsl,p1022-diu";
		reg = <0x10000 1000>;
		interrupts = <64 2 0 0>;
	};

	ssi@15000 {
		compatible = "fsl,mpc8610-ssi";
		cell-index = <0>;
		reg = <0x15000 0x100>;
		interrupts = <75 2 0 0>;
		fsl,playback-dma = <&dma00>;
		fsl,capture-dma = <&dma01>;
		fsl,fifo-depth = <15>;
	};

/include/ "pq3-sata2-0.dtsi"
/include/ "pq3-sata2-1.dtsi"

	L2: l2-cache-controller@20000 {
		compatible = "fsl,p1022-l2-cache-controller";
		reg = <0x20000 0x1000>;
		cache-line-size = <32>;	// 32 bytes
		cache-size = <0x40000>; // L2,256K
		interrupts = <16 2 0 0>;
	};

/include/ "pq3-dma-0.dtsi"
/include/ "pq3-usb2-dr-0.dtsi"
	usb@22000 {
		compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
	};
/include/ "pq3-usb2-dr-1.dtsi"
	usb@23000 {
		compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
	};

/include/ "pq3-esdhc-0.dtsi"
	sdhc@2e000 {
		compatible = "fsl,p1022-esdhc", "fsl,esdhc";
		sdhci,auto-cmd12;
	};

/include/ "pq3-sec3.3-0.dtsi"
/include/ "pq3-mpic.dtsi"
/include/ "pq3-mpic-timer-B.dtsi"

/include/ "pq3-etsec2-0.dtsi"
	enet0: enet0_grp2: ethernet@b0000 {
		fsl,wake-on-filer;
		fsl,pmc-handle = <&etsec1_clk>;
	};

/include/ "pq3-etsec2-1.dtsi"
	enet1: enet1_grp2: ethernet@b1000 {
		fsl,wake-on-filer;
		fsl,pmc-handle = <&etsec2_clk>;
	};

	global-utilities@e0000 {
		compatible = "fsl,p1022-guts";
		reg = <0xe0000 0x1000>;
		fsl,has-rstcr;
	};

/include/ "pq3-power.dtsi"
	power@e0070 {
		compatible = "fsl,p1022-pmc", "fsl,mpc8536-pmc",
				"fsl,mpc8548-pmc";
	};

};

/include/ "pq3-etsec2-grp2-0.dtsi"
/include/ "pq3-etsec2-grp2-1.dtsi"
Commit	Line	Data
ab827d97 KG	1	/*
	2	* P1022/P1013 Silicon/SoC Device Tree Source (post include)
	3	*
	4	* Copyright 2011 Freescale Semiconductor Inc.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions are met:
	8	* * Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* * Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	* * Neither the name of Freescale Semiconductor nor the
	14	* names of its contributors may be used to endorse or promote products
	15	* derived from this software without specific prior written permission.
	16	*
	17	*
	18	* ALTERNATIVELY, this software may be distributed under the terms of the
	19	* GNU General Public License ("GPL") as published by the Free Software
	20	* Foundation, either version 2 of that License or (at your option) any
	21	* later version.
	22	*
	23	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	24	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	25	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	26	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	27	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	28	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	29	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	30	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	31	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	32	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	&lbc {
	36	#address-cells = <2>;
	37	#size-cells = <1>;
4951896a TT	38	/*
	39	* The localbus on the P1022 is not a simple-bus because of the eLBC
	40	* pin muxing when the DIU is enabled.
	41	*/
	42	compatible = "fsl,p1022-elbc", "fsl,elbc";
297649b9 WD	43	interrupts = <19 2 0 0>,
297649b9 WD	44	<16 2 0 0>;
ab827d97 KG	45	};
	46
	47	/* controller at 0x9000 */
	48	&pci0 {
14bdc913	49	compatible = "fsl,mpc8548-pcie";
ab827d97 KG	50	device_type = "pci";
	51	#size-cells = <2>;
	52	#address-cells = <3>;
	53	bus-range = <0 255>;
	54	clock-frequency = <33333333>;
	55	interrupts = <16 2 0 0>;
	56
	57	pcie@0 {
	58	reg = <0 0 0 0 0>;
	59	#interrupt-cells = <1>;
	60	#size-cells = <2>;
	61	#address-cells = <3>;
	62	device_type = "pci";
	63	interrupts = <16 2 0 0>;
	64	interrupt-map-mask = <0xf800 0 0 7>;
	65	interrupt-map = <
	66	/* IDSEL 0x0 */
	67	0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
	68	0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
	69	0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
	70	0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
	71	>;
	72	};
	73	};
	74
	75	/* controller at 0xa000 */
	76	&pci1 {
14bdc913	77	compatible = "fsl,mpc8548-pcie";
ab827d97 KG	78	device_type = "pci";
	79	#size-cells = <2>;
	80	#address-cells = <3>;
	81	bus-range = <0 255>;
	82	clock-frequency = <33333333>;
	83	interrupts = <16 2 0 0>;
	84
	85	pcie@0 {
	86	reg = <0 0 0 0 0>;
	87	#interrupt-cells = <1>;
	88	#size-cells = <2>;
	89	#address-cells = <3>;
	90	device_type = "pci";
	91	interrupts = <16 2 0 0>;
	92	interrupt-map-mask = <0xf800 0 0 7>;
	93
	94	interrupt-map = <
	95	/* IDSEL 0x0 */
	96	0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
	97	0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
	98	0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
	99	0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
	100	>;
	101	};
	102	};
	103
	104	/* controller at 0xb000 */
	105	&pci2 {
14bdc913	106	compatible = "fsl,mpc8548-pcie";
ab827d97 KG	107	device_type = "pci";
	108	#size-cells = <2>;
	109	#address-cells = <3>;
	110	bus-range = <0 255>;
	111	clock-frequency = <33333333>;
	112	interrupts = <16 2 0 0>;
	113
	114	pcie@0 {
	115	reg = <0 0 0 0 0>;
	116	#interrupt-cells = <1>;
	117	#size-cells = <2>;
	118	#address-cells = <3>;
	119	device_type = "pci";
	120	interrupts = <16 2 0 0>;
	121	interrupt-map-mask = <0xf800 0 0 7>;
	122
	123	interrupt-map = <
	124	/* IDSEL 0x0 */
	125	0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
	126	0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
	127	0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
	128	0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
	129	>;
	130	};
	131	};
	132
	133	&soc {
	134	#address-cells = <1>;
	135	#size-cells = <1>;
	136	device_type = "soc";
	137	compatible = "fsl,p1022-immr", "simple-bus";
	138	bus-frequency = <0>; // Filled out by uboot.
	139
	140	ecm-law@0 {
	141	compatible = "fsl,ecm-law";
	142	reg = <0x0 0x1000>;
	143	fsl,num-laws = <12>;
	144	};
	145
	146	ecm@1000 {
	147	compatible = "fsl,p1022-ecm", "fsl,ecm";
	148	reg = <0x1000 0x1000>;
	149	interrupts = <16 2 0 0>;
	150	};
	151
	152	memory-controller@2000 {
	153	compatible = "fsl,p1022-memory-controller";
	154	reg = <0x2000 0x1000>;
	155	interrupts = <16 2 0 0>;
	156	};
	157
	158	/include/ "pq3-i2c-0.dtsi"
	159	/include/ "pq3-i2c-1.dtsi"
	160	/include/ "pq3-duart-0.dtsi"
	161	/include/ "pq3-espi-0.dtsi"
	162	spi@7000 {
	163	fsl,espi-num-chipselects = <4>;
	164	};
	165
	166	/include/ "pq3-dma-1.dtsi"
	167	dma@c300 {
	168	dma00: dma-channel@0 {
	169	compatible = "fsl,ssi-dma-channel";
	170	};
171	dma01: dma-channel@80 {
172	compatible = "fsl,ssi-dma-channel";
173	};
174	};
175
176	/include/ "pq3-gpio-0.dtsi"
177
e8c4b3df	178	display: display@10000 {
ab827d97 KG	179	compatible = "fsl,diu", "fsl,p1022-diu";
	180	reg = <0x10000 1000>;
	181	interrupts = <64 2 0 0>;
	182	};
	183
	184	ssi@15000 {
	185	compatible = "fsl,mpc8610-ssi";
	186	cell-index = <0>;
	187	reg = <0x15000 0x100>;
	188	interrupts = <75 2 0 0>;
	189	fsl,playback-dma = <&dma00>;
	190	fsl,capture-dma = <&dma01>;
	191	fsl,fifo-depth = <15>;
	192	};
	193
	194	/include/ "pq3-sata2-0.dtsi"
	195	/include/ "pq3-sata2-1.dtsi"
	196
	197	L2: l2-cache-controller@20000 {
	198	compatible = "fsl,p1022-l2-cache-controller";
	199	reg = <0x20000 0x1000>;
	200	cache-line-size = <32>; // 32 bytes
	201	cache-size = <0x40000>; // L2,256K
	202	interrupts = <16 2 0 0>;
	203	};
	204
	205	/include/ "pq3-dma-0.dtsi"
	206	/include/ "pq3-usb2-dr-0.dtsi"
465aceb8 RM	207	usb@22000 {
	208	compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
	209	};
ab827d97	210	/include/ "pq3-usb2-dr-1.dtsi"
465aceb8 RM	211	usb@23000 {
	212	compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
	213	};
ab827d97 KG	214
	215	/include/ "pq3-esdhc-0.dtsi"
	216	sdhc@2e000 {
f8b5a318 JH	217	compatible = "fsl,p1022-esdhc", "fsl,esdhc";
f8b5a318 JH	218	sdhci,auto-cmd12;
ab827d97 KG	219	};
	220
	221	/include/ "pq3-sec3.3-0.dtsi"
	222	/include/ "pq3-mpic.dtsi"
	223	/include/ "pq3-mpic-timer-B.dtsi"
	224
	225	/include/ "pq3-etsec2-0.dtsi"
	226	enet0: enet0_grp2: ethernet@b0000 {
70963d24	227	fsl,wake-on-filer;
b12ba096	228	fsl,pmc-handle = <&etsec1_clk>;
ab827d97 KG	229	};
	230
	231	/include/ "pq3-etsec2-1.dtsi"
	232	enet1: enet1_grp2: ethernet@b1000 {
70963d24	233	fsl,wake-on-filer;
b12ba096	234	fsl,pmc-handle = <&etsec2_clk>;
ab827d97 KG	235	};
	236
	237	global-utilities@e0000 {
	238	compatible = "fsl,p1022-guts";
	239	reg = <0xe0000 0x1000>;
	240	fsl,has-rstcr;
	241	};
	242
b12ba096	243	/include/ "pq3-power.dtsi"
11073886	244	power@e0070 {
b12ba096 RW	245	compatible = "fsl,p1022-pmc", "fsl,mpc8536-pmc",
b12ba096 RW	246	"fsl,mpc8548-pmc";
ab827d97 KG	247	};
	248
	249	};
	250
	251	/include/ "pq3-etsec2-grp2-0.dtsi"
	252	/include/ "pq3-etsec2-grp2-1.dtsi"