[linux-block.git] / arch / powerpc / boot / dts / fsl / mpc8541cds.dts

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * MPC8541 CDS Device Tree Source
 *
 * Copyright 2006, 2008 Freescale Semiconductor Inc.
 */

/dts-v1/;

/include/ "e500v2_power_isa.dtsi"

/ {
	model = "MPC8541CDS";
	compatible = "MPC8541CDS", "MPC85xxCDS";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet1;
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8541@0 {
			device_type = "cpu";
			reg = <0x0>;
			d-cache-line-size = <32>;	// 32 bytes
			i-cache-line-size = <32>;	// 32 bytes
			d-cache-size = <0x8000>;		// L1, 32K
			i-cache-size = <0x8000>;		// L1, 32K
			timebase-frequency = <0>;	//  33 MHz, from uboot
			bus-frequency = <0>;	// 166 MHz
			clock-frequency = <0>;	// 825 MHz, from uboot
			next-level-cache = <&L2>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x8000000>;	// 128M at 0x0
	};

	soc8541@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";
		ranges = <0x0 0xe0000000 0x100000>;
		bus-frequency = <0>;

		ecm-law@0 {
			compatible = "fsl,ecm-law";
			reg = <0x0 0x1000>;
			fsl,num-laws = <8>;
		};

		ecm@1000 {
			compatible = "fsl,mpc8541-ecm", "fsl,ecm";
			reg = <0x1000 0x1000>;
			interrupts = <17 2>;
			interrupt-parent = <&mpic>;
		};

		memory-controller@2000 {
			compatible = "fsl,mpc8541-memory-controller";
			reg = <0x2000 0x1000>;
			interrupt-parent = <&mpic>;
			interrupts = <18 2>;
		};

		L2: l2-cache-controller@20000 {
			compatible = "fsl,mpc8541-l2-cache-controller";
			reg = <0x20000 0x1000>;
			cache-line-size = <32>;	// 32 bytes
			cache-size = <0x40000>;	// L2, 256K
			interrupt-parent = <&mpic>;
			interrupts = <16 2>;
		};

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
			reg = <0x21300 0x4>;
			ranges = <0x0 0x21100 0x200>;
			cell-index = <0>;
			dma-channel@0 {
				compatible = "fsl,mpc8541-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x0 0x80>;
				cell-index = <0>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@80 {
				compatible = "fsl,mpc8541-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x80 0x80>;
				cell-index = <1>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@100 {
				compatible = "fsl,mpc8541-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x100 0x80>;
				cell-index = <2>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@180 {
				compatible = "fsl,mpc8541-dma-channel",
						"fsl,eloplus-dma-channel";
				reg = <0x180 0x80>;
				cell-index = <3>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		enet0: ethernet@24000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <0>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x24000 0x1000>;
			ranges = <0x0 0x24000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <29 2 30 2 34 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi0>;
			phy-handle = <&phy0>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-mdio";
				reg = <0x520 0x20>;

				phy0: ethernet-phy@0 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x0>;
				};
				phy1: ethernet-phy@1 {
					interrupt-parent = <&mpic>;
					interrupts = <5 1>;
					reg = <0x1>;
				};
				tbi0: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		enet1: ethernet@25000 {
			#address-cells = <1>;
			#size-cells = <1>;
			cell-index = <1>;
			device_type = "network";
			model = "TSEC";
			compatible = "gianfar";
			reg = <0x25000 0x1000>;
			ranges = <0x0 0x25000 0x1000>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <35 2 36 2 40 2>;
			interrupt-parent = <&mpic>;
			tbi-handle = <&tbi1>;
			phy-handle = <&phy1>;

			mdio@520 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,gianfar-tbi";
				reg = <0x520 0x20>;

				tbi1: tbi-phy@11 {
					reg = <0x11>;
					device_type = "tbi-phy";
				};
			};
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4500 0x100>; 	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "fsl,ns16550", "ns16550";
			reg = <0x4600 0x100>;	// reg base, size
			clock-frequency = <0>; 	// should we fill in in uboot?
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		crypto@30000 {
			compatible = "fsl,sec2.0";
			reg = <0x30000 0x10000>;
			interrupts = <45 2>;
			interrupt-parent = <&mpic>;
			fsl,num-channels = <4>;
			fsl,channel-fifo-len = <24>;
			fsl,exec-units-mask = <0x7e>;
			fsl,descriptor-types-mask = <0x01010ebf>;
		};

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
		};

		cpm@919c0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
			reg = <0x919c0 0x30>;
			ranges;

			muram@80000 {
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0x0 0x80000 0x10000>;

				data@0 {
					compatible = "fsl,cpm-muram-data";
					reg = <0x0 0x2000 0x9000 0x1000>;
				};
			};

			brg@919f0 {
				compatible = "fsl,mpc8541-brg",
				             "fsl,cpm2-brg",
				             "fsl,cpm-brg";
				reg = <0x919f0 0x10 0x915f0 0x10>;
			};

			cpmpic: pic@90c00 {
				interrupt-controller;
				#address-cells = <0>;
				#interrupt-cells = <2>;
				interrupts = <46 2>;
				interrupt-parent = <&mpic>;
				reg = <0x90c00 0x80>;
				compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
			};
		};
	};

	pci0: pci@e0008000 {
		interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x10 */
			0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x8000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x11 */
			0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
			0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
			0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
			0x8800 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x12 (Slot 1) */
			0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x9000 0x0 0x0 0x4 &mpic 0x3 0x1

			/* IDSEL 0x13 (Slot 2) */
			0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
			0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
			0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
			0x9800 0x0 0x0 0x4 &mpic 0x0 0x1

			/* IDSEL 0x14 (Slot 3) */
			0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
			0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
			0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
			0xa000 0x0 0x0 0x4 &mpic 0x1 0x1

			/* IDSEL 0x15 (Slot 4) */
			0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
			0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
			0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
			0xa800 0x0 0x0 0x4 &mpic 0x2 0x1

			/* Bus 1 (Tundra Bridge) */
			/* IDSEL 0x12 (ISA bridge) */
			0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
			0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
			0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
			0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";

		i8259@19000 {
			interrupt-controller;
			device_type = "interrupt-controller";
			reg = <0x19000 0x0 0x0 0x0 0x1>;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			compatible = "chrp,iic";
			interrupts = <1>;
			interrupt-parent = <&pci0>;
		};
	};

	pci1: pci@e0009000 {
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
		interrupt-map = <

			/* IDSEL 0x15 */
			0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
			0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		bus-range = <0 0>;
		ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
		clock-frequency = <66666666>;
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0009000 0x1000>;
		compatible = "fsl,mpc8540-pci";
		device_type = "pci";
	};
};
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
2654d638 AF	2	/*
	3	* MPC8541 CDS Device Tree Source
	4	*
32f960e9	5	* Copyright 2006, 2008 Freescale Semiconductor Inc.
2654d638 AF	6	*/
2654d638 AF	7
32f960e9	8	/dts-v1/;
2654d638	9
dc37374b	10	/include/ "e500v2_power_isa.dtsi"
2eb28006	11
2654d638 AF	12	/ {
2654d638 AF	13	model = "MPC8541CDS";
52094879	14	compatible = "MPC8541CDS", "MPC85xxCDS";
2654d638 AF	15	#address-cells = <1>;
2654d638 AF	16	#size-cells = <1>;
2654d638	17
ea082fa9 KG	18	aliases {
	19	ethernet0 = &enet0;
	20	ethernet1 = &enet1;
	21	serial0 = &serial0;
	22	serial1 = &serial1;
	23	pci0 = &pci0;
	24	pci1 = &pci1;
	25	};
	26
2654d638	27	cpus {
2654d638 AF	28	#address-cells = <1>;
2654d638 AF	29	#size-cells = <0>;
2654d638 AF	30
	31	PowerPC,8541@0 {
	32	device_type = "cpu";
32f960e9 KG	33	reg = <0x0>;
	34	d-cache-line-size = <32>; // 32 bytes
	35	i-cache-line-size = <32>; // 32 bytes
	36	d-cache-size = <0x8000>; // L1, 32K
	37	i-cache-size = <0x8000>; // L1, 32K
2654d638 AF	38	timebase-frequency = <0>; // 33 MHz, from uboot
	39	bus-frequency = <0>; // 166 MHz
	40	clock-frequency = <0>; // 825 MHz, from uboot
c054065b	41	next-level-cache = <&L2>;
2654d638 AF	42	};
	43	};
	44
	45	memory {
	46	device_type = "memory";
32f960e9	47	reg = <0x0 0x8000000>; // 128M at 0x0
2654d638 AF	48	};
	49
	50	soc8541@e0000000 {
	51	#address-cells = <1>;
	52	#size-cells = <1>;
2654d638	53	device_type = "soc";
cf0d19fb	54	compatible = "simple-bus";
32f960e9	55	ranges = <0x0 0xe0000000 0x100000>;
2654d638 AF	56	bus-frequency = <0>;
2654d638 AF	57
e1a22897 KG	58	ecm-law@0 {
	59	compatible = "fsl,ecm-law";
	60	reg = <0x0 0x1000>;
	61	fsl,num-laws = <8>;
	62	};
	63
	64	ecm@1000 {
	65	compatible = "fsl,mpc8541-ecm", "fsl,ecm";
	66	reg = <0x1000 0x1000>;
	67	interrupts = <17 2>;
	68	interrupt-parent = <&mpic>;
	69	};
	70
4da421d6	71	memory-controller@2000 {
8a4ab218	72	compatible = "fsl,mpc8541-memory-controller";
32f960e9	73	reg = <0x2000 0x1000>;
4da421d6	74	interrupt-parent = <&mpic>;
32f960e9	75	interrupts = <18 2>;
4da421d6 KG	76	};
4da421d6 KG	77
c054065b	78	L2: l2-cache-controller@20000 {
8a4ab218	79	compatible = "fsl,mpc8541-l2-cache-controller";
32f960e9 KG	80	reg = <0x20000 0x1000>;
	81	cache-line-size = <32>; // 32 bytes
	82	cache-size = <0x40000>; // L2, 256K
4da421d6	83	interrupt-parent = <&mpic>;
32f960e9	84	interrupts = <16 2>;
4da421d6 KG	85	};
4da421d6 KG	86
2654d638	87	i2c@3000 {
ec9686c4 KG	88	#address-cells = <1>;
	89	#size-cells = <0>;
	90	cell-index = <0>;
2654d638	91	compatible = "fsl-i2c";
32f960e9 KG	92	reg = <0x3000 0x100>;
32f960e9 KG	93	interrupts = <43 2>;
52094879	94	interrupt-parent = <&mpic>;
2654d638 AF	95	dfsrr;
	96	};
	97
dee80553 KG	98	dma@21300 {
	99	#address-cells = <1>;
	100	#size-cells = <1>;
	101	compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
	102	reg = <0x21300 0x4>;
	103	ranges = <0x0 0x21100 0x200>;
	104	cell-index = <0>;
	105	dma-channel@0 {
	106	compatible = "fsl,mpc8541-dma-channel",
	107	"fsl,eloplus-dma-channel";
	108	reg = <0x0 0x80>;
	109	cell-index = <0>;
	110	interrupt-parent = <&mpic>;
	111	interrupts = <20 2>;
	112	};
	113	dma-channel@80 {
	114	compatible = "fsl,mpc8541-dma-channel",
	115	"fsl,eloplus-dma-channel";
	116	reg = <0x80 0x80>;
	117	cell-index = <1>;
	118	interrupt-parent = <&mpic>;
	119	interrupts = <21 2>;
	120	};
	121	dma-channel@100 {
	122	compatible = "fsl,mpc8541-dma-channel",
	123	"fsl,eloplus-dma-channel";
	124	reg = <0x100 0x80>;
	125	cell-index = <2>;
	126	interrupt-parent = <&mpic>;
	127	interrupts = <22 2>;
	128	};
	129	dma-channel@180 {
	130	compatible = "fsl,mpc8541-dma-channel",
	131	"fsl,eloplus-dma-channel";
	132	reg = <0x180 0x80>;
	133	cell-index = <3>;
	134	interrupt-parent = <&mpic>;
	135	interrupts = <23 2>;
	136	};
	137	};
	138
e77b28eb	139	enet0: ethernet@24000 {
84ba4a58 AV	140	#address-cells = <1>;
84ba4a58 AV	141	#size-cells = <1>;
e77b28eb	142	cell-index = <0>;
2654d638 AF	143	device_type = "network";
	144	model = "TSEC";
	145	compatible = "gianfar";
32f960e9	146	reg = <0x24000 0x1000>;
84ba4a58	147	ranges = <0x0 0x24000 0x1000>;
eae98266	148	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	149	interrupts = <29 2 30 2 34 2>;
52094879	150	interrupt-parent = <&mpic>;
b31a1d8b	151	tbi-handle = <&tbi0>;
52094879	152	phy-handle = <&phy0>;
84ba4a58 AV	153
	154	mdio@520 {
	155	#address-cells = <1>;
	156	#size-cells = <0>;
	157	compatible = "fsl,gianfar-mdio";
	158	reg = <0x520 0x20>;
	159
	160	phy0: ethernet-phy@0 {
	161	interrupt-parent = <&mpic>;
	162	interrupts = <5 1>;
	163	reg = <0x0>;
84ba4a58 AV	164	};
	165	phy1: ethernet-phy@1 {
	166	interrupt-parent = <&mpic>;
	167	interrupts = <5 1>;
	168	reg = <0x1>;
84ba4a58 AV	169	};
	170	tbi0: tbi-phy@11 {
	171	reg = <0x11>;
	172	device_type = "tbi-phy";
	173	};
	174	};
2654d638 AF	175	};
2654d638 AF	176
e77b28eb	177	enet1: ethernet@25000 {
84ba4a58 AV	178	#address-cells = <1>;
84ba4a58 AV	179	#size-cells = <1>;
e77b28eb	180	cell-index = <1>;
2654d638 AF	181	device_type = "network";
	182	model = "TSEC";
	183	compatible = "gianfar";
32f960e9	184	reg = <0x25000 0x1000>;
84ba4a58	185	ranges = <0x0 0x25000 0x1000>;
eae98266	186	local-mac-address = [ 00 00 00 00 00 00 ];
32f960e9	187	interrupts = <35 2 36 2 40 2>;
52094879	188	interrupt-parent = <&mpic>;
b31a1d8b	189	tbi-handle = <&tbi1>;
52094879	190	phy-handle = <&phy1>;
84ba4a58 AV	191
	192	mdio@520 {
	193	#address-cells = <1>;
	194	#size-cells = <0>;
	195	compatible = "fsl,gianfar-tbi";
	196	reg = <0x520 0x20>;
	197
	198	tbi1: tbi-phy@11 {
	199	reg = <0x11>;
	200	device_type = "tbi-phy";
	201	};
	202	};
2654d638 AF	203	};
2654d638 AF	204
ea082fa9 KG	205	serial0: serial@4500 {
ea082fa9 KG	206	cell-index = <0>;
2654d638	207	device_type = "serial";
f706bed1	208	compatible = "fsl,ns16550", "ns16550";
32f960e9	209	reg = <0x4500 0x100>; // reg base, size
2654d638	210	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	211	interrupts = <42 2>;
52094879	212	interrupt-parent = <&mpic>;
2654d638 AF	213	};
2654d638 AF	214
ea082fa9 KG	215	serial1: serial@4600 {
ea082fa9 KG	216	cell-index = <1>;
2654d638	217	device_type = "serial";
f706bed1	218	compatible = "fsl,ns16550", "ns16550";
32f960e9	219	reg = <0x4600 0x100>; // reg base, size
2654d638	220	clock-frequency = <0>; // should we fill in in uboot?
32f960e9	221	interrupts = <42 2>;
52094879	222	interrupt-parent = <&mpic>;
2654d638 AF	223	};
2654d638 AF	224
3fd44736 KP	225	crypto@30000 {
	226	compatible = "fsl,sec2.0";
	227	reg = <0x30000 0x10000>;
	228	interrupts = <45 2>;
	229	interrupt-parent = <&mpic>;
	230	fsl,num-channels = <4>;
	231	fsl,channel-fifo-len = <24>;
	232	fsl,exec-units-mask = <0x7e>;
	233	fsl,descriptor-types-mask = <0x01010ebf>;
	234	};
	235
52094879	236	mpic: pic@40000 {
2654d638 AF	237	interrupt-controller;
	238	#address-cells = <0>;
	239	#interrupt-cells = <2>;
32f960e9	240	reg = <0x40000 0x40000>;
2654d638 AF	241	compatible = "chrp,open-pic";
2654d638 AF	242	device_type = "open-pic";
2654d638	243	};
ab9683ca SW	244
	245	cpm@919c0 {
	246	#address-cells = <1>;
	247	#size-cells = <1>;
	248	compatible = "fsl,mpc8541-cpm", "fsl,cpm2";
32f960e9	249	reg = <0x919c0 0x30>;
ab9683ca SW	250	ranges;
	251
	252	muram@80000 {
	253	#address-cells = <1>;
	254	#size-cells = <1>;
32f960e9	255	ranges = <0x0 0x80000 0x10000>;
ab9683ca SW	256
	257	data@0 {
	258	compatible = "fsl,cpm-muram-data";
32f960e9	259	reg = <0x0 0x2000 0x9000 0x1000>;
ab9683ca SW	260	};
	261	};
	262
	263	brg@919f0 {
	264	compatible = "fsl,mpc8541-brg",
	265	"fsl,cpm2-brg",
	266	"fsl,cpm-brg";
32f960e9	267	reg = <0x919f0 0x10 0x915f0 0x10>;
ab9683ca SW	268	};
	269
	270	cpmpic: pic@90c00 {
	271	interrupt-controller;
	272	#address-cells = <0>;
	273	#interrupt-cells = <2>;
32f960e9	274	interrupts = <46 2>;
ab9683ca	275	interrupt-parent = <&mpic>;
32f960e9	276	reg = <0x90c00 0x80>;
ab9683ca SW	277	compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
	278	};
	279	};
2654d638	280	};
1b3c5cda	281
ea082fa9	282	pci0: pci@e0008000 {
32f960e9	283	interrupt-map-mask = <0x1f800 0x0 0x0 0x7>;
1b3c5cda KG	284	interrupt-map = <
	285
	286	/* IDSEL 0x10 */
32f960e9 KG	287	0x8000 0x0 0x0 0x1 &mpic 0x0 0x1
	288	0x8000 0x0 0x0 0x2 &mpic 0x1 0x1
	289	0x8000 0x0 0x0 0x3 &mpic 0x2 0x1
	290	0x8000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	291
1b3c5cda KG	292	/* IDSEL 0x11 */
32f960e9 KG	293	0x8800 0x0 0x0 0x1 &mpic 0x0 0x1
	294	0x8800 0x0 0x0 0x2 &mpic 0x1 0x1
	295	0x8800 0x0 0x0 0x3 &mpic 0x2 0x1
	296	0x8800 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	297
1b3c5cda KG	298	/* IDSEL 0x12 (Slot 1) */
32f960e9 KG	299	0x9000 0x0 0x0 0x1 &mpic 0x0 0x1
	300	0x9000 0x0 0x0 0x2 &mpic 0x1 0x1
	301	0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
	302	0x9000 0x0 0x0 0x4 &mpic 0x3 0x1
1b3c5cda KG	303
1b3c5cda KG	304	/* IDSEL 0x13 (Slot 2) */
32f960e9 KG	305	0x9800 0x0 0x0 0x1 &mpic 0x1 0x1
	306	0x9800 0x0 0x0 0x2 &mpic 0x2 0x1
	307	0x9800 0x0 0x0 0x3 &mpic 0x3 0x1
	308	0x9800 0x0 0x0 0x4 &mpic 0x0 0x1
1b3c5cda KG	309
1b3c5cda KG	310	/* IDSEL 0x14 (Slot 3) */
32f960e9 KG	311	0xa000 0x0 0x0 0x1 &mpic 0x2 0x1
	312	0xa000 0x0 0x0 0x2 &mpic 0x3 0x1
	313	0xa000 0x0 0x0 0x3 &mpic 0x0 0x1
	314	0xa000 0x0 0x0 0x4 &mpic 0x1 0x1
1b3c5cda KG	315
1b3c5cda KG	316	/* IDSEL 0x15 (Slot 4) */
32f960e9 KG	317	0xa800 0x0 0x0 0x1 &mpic 0x3 0x1
	318	0xa800 0x0 0x0 0x2 &mpic 0x0 0x1
	319	0xa800 0x0 0x0 0x3 &mpic 0x1 0x1
	320	0xa800 0x0 0x0 0x4 &mpic 0x2 0x1
1b3c5cda KG	321
	322	/* Bus 1 (Tundra Bridge) */
	323	/* IDSEL 0x12 (ISA bridge) */
32f960e9 KG	324	0x19000 0x0 0x0 0x1 &mpic 0x0 0x1
	325	0x19000 0x0 0x0 0x2 &mpic 0x1 0x1
	326	0x19000 0x0 0x0 0x3 &mpic 0x2 0x1
	327	0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>;
1b3c5cda	328	interrupt-parent = <&mpic>;
32f960e9	329	interrupts = <24 2>;
1b3c5cda	330	bus-range = <0 0>;
32f960e9 KG	331	ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
	332	0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
	333	clock-frequency = <66666666>;
1b3c5cda KG	334	#interrupt-cells = <1>;
	335	#size-cells = <2>;
	336	#address-cells = <3>;
32f960e9	337	reg = <0xe0008000 0x1000>;
1b3c5cda KG	338	compatible = "fsl,mpc8540-pci";
	339	device_type = "pci";
	340
	341	i8259@19000 {
	342	interrupt-controller;
	343	device_type = "interrupt-controller";
32f960e9	344	reg = <0x19000 0x0 0x0 0x0 0x1>;
1b3c5cda KG	345	#address-cells = <0>;
	346	#interrupt-cells = <2>;
	347	compatible = "chrp,iic";
	348	interrupts = <1>;
ea082fa9	349	interrupt-parent = <&pci0>;
1b3c5cda KG	350	};
	351	};
	352
ea082fa9	353	pci1: pci@e0009000 {
32f960e9	354	interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
1b3c5cda KG	355	interrupt-map = <
	356
	357	/* IDSEL 0x15 */
32f960e9 KG	358	0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
	359	0xa800 0x0 0x0 0x2 &mpic 0xb 0x1
	360	0xa800 0x0 0x0 0x3 &mpic 0xb 0x1
	361	0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>;
1b3c5cda	362	interrupt-parent = <&mpic>;
32f960e9	363	interrupts = <25 2>;
1b3c5cda	364	bus-range = <0 0>;
32f960e9 KG	365	ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
	366	0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
	367	clock-frequency = <66666666>;
1b3c5cda KG	368	#interrupt-cells = <1>;
	369	#size-cells = <2>;
	370	#address-cells = <3>;
32f960e9	371	reg = <0xe0009000 0x1000>;
1b3c5cda KG	372	compatible = "fsl,mpc8540-pci";
	373	device_type = "pci";
	374	};
2654d638	375	};