[linux-block.git] / arch / parisc / mm / fault.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 *
 * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
 * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
 * Copyright 1999 Hewlett Packard Co.
 *
 */

#include <linux/mm.h>
#include <linux/ptrace.h>
#include <linux/sched.h>
#include <linux/sched/debug.h>
#include <linux/interrupt.h>
#include <linux/extable.h>
#include <linux/uaccess.h>
#include <linux/hugetlb.h>
#include <linux/perf_event.h>

#include <asm/traps.h>

#define DEBUG_NATLB 0

/* Various important other fields */
#define bit22set(x)		(x & 0x00000200)
#define bits23_25set(x)		(x & 0x000001c0)
#define isGraphicsFlushRead(x)	((x & 0xfc003fdf) == 0x04001a80)
				/* extended opcode is 0x6a */

#define BITSSET		0x1c0	/* for identifying LDCW */


int show_unhandled_signals = 1;

/*
 * parisc_acctyp(unsigned int inst) --
 *    Given a PA-RISC memory access instruction, determine if the
 *    the instruction would perform a memory read or memory write
 *    operation.
 *
 *    This function assumes that the given instruction is a memory access
 *    instruction (i.e. you should really only call it if you know that
 *    the instruction has generated some sort of a memory access fault).
 *
 * Returns:
 *   VM_READ  if read operation
 *   VM_WRITE if write operation
 *   VM_EXEC  if execute operation
 */
unsigned long
parisc_acctyp(unsigned long code, unsigned int inst)
{
	if (code == 6 || code == 16)
	    return VM_EXEC;

	switch (inst & 0xf0000000) {
	case 0x40000000: /* load */
	case 0x50000000: /* new load */
		return VM_READ;

	case 0x60000000: /* store */
	case 0x70000000: /* new store */
		return VM_WRITE;

	case 0x20000000: /* coproc */
	case 0x30000000: /* coproc2 */
		if (bit22set(inst))
			return VM_WRITE;
		fallthrough;

	case 0x0: /* indexed/memory management */
		if (bit22set(inst)) {
			/*
			 * Check for the 'Graphics Flush Read' instruction.
			 * It resembles an FDC instruction, except for bits
			 * 20 and 21. Any combination other than zero will
			 * utilize the block mover functionality on some
			 * older PA-RISC platforms.  The case where a block
			 * move is performed from VM to graphics IO space
			 * should be treated as a READ.
			 *
			 * The significance of bits 20,21 in the FDC
			 * instruction is:
			 *
			 *   00  Flush data cache (normal instruction behavior)
			 *   01  Graphics flush write  (IO space -> VM)
			 *   10  Graphics flush read   (VM -> IO space)
			 *   11  Graphics flush read/write (VM <-> IO space)
			 */
			if (isGraphicsFlushRead(inst))
				return VM_READ;
			return VM_WRITE;
		} else {
			/*
			 * Check for LDCWX and LDCWS (semaphore instructions).
			 * If bits 23 through 25 are all 1's it is one of
			 * the above two instructions and is a write.
			 *
			 * Note: With the limited bits we are looking at,
			 * this will also catch PROBEW and PROBEWI. However,
			 * these should never get in here because they don't
			 * generate exceptions of the type:
			 *   Data TLB miss fault/data page fault
			 *   Data memory protection trap
			 */
			if (bits23_25set(inst) == BITSSET)
				return VM_WRITE;
		}
		return VM_READ; /* Default */
	}
	return VM_READ; /* Default */
}

#undef bit22set
#undef bits23_25set
#undef isGraphicsFlushRead
#undef BITSSET


#if 0
/* This is the treewalk to find a vma which is the highest that has
 * a start < addr.  We're using find_vma_prev instead right now, but
 * we might want to use this at some point in the future.  Probably
 * not, but I want it committed to CVS so I don't lose it :-)
 */
			while (tree != vm_avl_empty) {
				if (tree->vm_start > addr) {
					tree = tree->vm_avl_left;
				} else {
					prev = tree;
					if (prev->vm_next == NULL)
						break;
					if (prev->vm_next->vm_start > addr)
						break;
					tree = tree->vm_avl_right;
				}
			}
#endif

int fixup_exception(struct pt_regs *regs)
{
	const struct exception_table_entry *fix;

	fix = search_exception_tables(regs->iaoq[0]);
	if (fix) {
		/*
		 * Fix up get_user() and put_user().
		 * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant
		 * bit in the relative address of the fixup routine to indicate
		 * that gr[ASM_EXCEPTIONTABLE_REG] should be loaded with
		 * -EFAULT to report a userspace access error.
		 */
		if (fix->fixup & 1) {
			regs->gr[ASM_EXCEPTIONTABLE_REG] = -EFAULT;

			/* zero target register for get_user() */
			if (parisc_acctyp(0, regs->iir) == VM_READ) {
				int treg = regs->iir & 0x1f;
				BUG_ON(treg == 0);
				regs->gr[treg] = 0;
			}
		}

		regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup;
		regs->iaoq[0] &= ~3;
		/*
		 * NOTE: In some cases the faulting instruction
		 * may be in the delay slot of a branch. We
		 * don't want to take the branch, so we don't
		 * increment iaoq[1], instead we set it to be
		 * iaoq[0]+4, and clear the B bit in the PSW
		 */
		regs->iaoq[1] = regs->iaoq[0] + 4;
		regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */

		return 1;
	}

	return 0;
}

/*
 * parisc hardware trap list
 *
 * Documented in section 3 "Addressing and Access Control" of the
 * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
 * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf
 *
 * For implementation see handle_interruption() in traps.c
 */
static const char * const trap_description[] = {
	[1] "High-priority machine check (HPMC)",
	[2] "Power failure interrupt",
	[3] "Recovery counter trap",
	[5] "Low-priority machine check",
	[6] "Instruction TLB miss fault",
	[7] "Instruction access rights / protection trap",
	[8] "Illegal instruction trap",
	[9] "Break instruction trap",
	[10] "Privileged operation trap",
	[11] "Privileged register trap",
	[12] "Overflow trap",
	[13] "Conditional trap",
	[14] "FP Assist Exception trap",
	[15] "Data TLB miss fault",
	[16] "Non-access ITLB miss fault",
	[17] "Non-access DTLB miss fault",
	[18] "Data memory protection/unaligned access trap",
	[19] "Data memory break trap",
	[20] "TLB dirty bit trap",
	[21] "Page reference trap",
	[22] "Assist emulation trap",
	[25] "Taken branch trap",
	[26] "Data memory access rights trap",
	[27] "Data memory protection ID trap",
	[28] "Unaligned data reference trap",
};

const char *trap_name(unsigned long code)
{
	const char *t = NULL;

	if (code < ARRAY_SIZE(trap_description))
		t = trap_description[code];

	return t ? t : "Unknown trap";
}

/*
 * Print out info about fatal segfaults, if the show_unhandled_signals
 * sysctl is set:
 */
static inline void
show_signal_msg(struct pt_regs *regs, unsigned long code,
		unsigned long address, struct task_struct *tsk,
		struct vm_area_struct *vma)
{
	if (!unhandled_signal(tsk, SIGSEGV))
		return;

	if (!printk_ratelimit())
		return;

	pr_warn("\n");
	pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
	    tsk->comm, code, address);
	print_vma_addr(KERN_CONT " in ", regs->iaoq[0]);

	pr_cont("\ntrap #%lu: %s%c", code, trap_name(code),
		vma ? ',':'\n');

	if (vma)
		pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
			vma->vm_start, vma->vm_end);

	show_regs(regs);
}

void do_page_fault(struct pt_regs *regs, unsigned long code,
			      unsigned long address)
{
	struct vm_area_struct *vma, *prev_vma;
	struct task_struct *tsk;
	struct mm_struct *mm;
	unsigned long acc_type;
	vm_fault_t fault = 0;
	unsigned int flags;
	char *msg;

	tsk = current;
	mm = tsk->mm;
	if (!mm) {
		msg = "Page fault: no context";
		goto no_context;
	}

	flags = FAULT_FLAG_DEFAULT;
	if (user_mode(regs))
		flags |= FAULT_FLAG_USER;

	acc_type = parisc_acctyp(code, regs->iir);
	if (acc_type & VM_WRITE)
		flags |= FAULT_FLAG_WRITE;
	perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
retry:
	mmap_read_lock(mm);
	vma = find_vma_prev(mm, address, &prev_vma);
	if (!vma || address < vma->vm_start)
		goto check_expansion;
/*
 * Ok, we have a good vm_area for this memory access. We still need to
 * check the access permissions.
 */

good_area:

	if ((vma->vm_flags & acc_type) != acc_type)
		goto bad_area;

	/*
	 * If for any reason at all we couldn't handle the fault, make
	 * sure we exit gracefully rather than endlessly redo the
	 * fault.
	 */

	fault = handle_mm_fault(vma, address, flags, regs);

	if (fault_signal_pending(fault, regs))
		return;

	if (unlikely(fault & VM_FAULT_ERROR)) {
		/*
		 * We hit a shared mapping outside of the file, or some
		 * other thing happened to us that made us unable to
		 * handle the page fault gracefully.
		 */
		if (fault & VM_FAULT_OOM)
			goto out_of_memory;
		else if (fault & VM_FAULT_SIGSEGV)
			goto bad_area;
		else if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON|
				  VM_FAULT_HWPOISON_LARGE))
			goto bad_area;
		BUG();
	}
	if (fault & VM_FAULT_RETRY) {
		/*
		 * No need to mmap_read_unlock(mm) as we would
		 * have already released it in __lock_page_or_retry
		 * in mm/filemap.c.
		 */
		flags |= FAULT_FLAG_TRIED;
		goto retry;
	}
	mmap_read_unlock(mm);
	return;

check_expansion:
	vma = prev_vma;
	if (vma && (expand_stack(vma, address) == 0))
		goto good_area;

/*
 * Something tried to access memory that isn't in our memory map..
 */
bad_area:
	mmap_read_unlock(mm);

	if (user_mode(regs)) {
		int signo, si_code;

		switch (code) {
		case 15:	/* Data TLB miss fault/Data page fault */
			/* send SIGSEGV when outside of vma */
			if (!vma ||
			    address < vma->vm_start || address >= vma->vm_end) {
				signo = SIGSEGV;
				si_code = SEGV_MAPERR;
				break;
			}

			/* send SIGSEGV for wrong permissions */
			if ((vma->vm_flags & acc_type) != acc_type) {
				signo = SIGSEGV;
				si_code = SEGV_ACCERR;
				break;
			}

			/* probably address is outside of mapped file */
			fallthrough;
		case 17:	/* NA data TLB miss / page fault */
		case 18:	/* Unaligned access - PCXS only */
			signo = SIGBUS;
			si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
			break;
		case 16:	/* Non-access instruction TLB miss fault */
		case 26:	/* PCXL: Data memory access rights trap */
		default:
			signo = SIGSEGV;
			si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
			break;
		}
#ifdef CONFIG_MEMORY_FAILURE
		if (fault & (VM_FAULT_HWPOISON|VM_FAULT_HWPOISON_LARGE)) {
			unsigned int lsb = 0;
			printk(KERN_ERR
	"MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n",
			tsk->comm, tsk->pid, address);
			/*
			 * Either small page or large page may be poisoned.
			 * In other words, VM_FAULT_HWPOISON_LARGE and
			 * VM_FAULT_HWPOISON are mutually exclusive.
			 */
			if (fault & VM_FAULT_HWPOISON_LARGE)
				lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
			else if (fault & VM_FAULT_HWPOISON)
				lsb = PAGE_SHIFT;

			force_sig_mceerr(BUS_MCEERR_AR, (void __user *) address,
					 lsb);
			return;
		}
#endif
		show_signal_msg(regs, code, address, tsk, vma);

		force_sig_fault(signo, si_code, (void __user *) address);
		return;
	}
	msg = "Page fault: bad address";

no_context:

	if (!user_mode(regs) && fixup_exception(regs)) {
		return;
	}

	parisc_terminate(msg, regs, code, address);

out_of_memory:
	mmap_read_unlock(mm);
	if (!user_mode(regs)) {
		msg = "Page fault: out of memory";
		goto no_context;
	}
	pagefault_out_of_memory();
}

/* Handle non-access data TLB miss faults.
 *
 * For probe instructions, accesses to userspace are considered allowed
 * if they lie in a valid VMA and the access type matches. We are not
 * allowed to handle MM faults here so there may be situations where an
 * actual access would fail even though a probe was successful.
 */
int
handle_nadtlb_fault(struct pt_regs *regs)
{
	unsigned long insn = regs->iir;
	int breg, treg, xreg, val = 0;
	struct vm_area_struct *vma, *prev_vma;
	struct task_struct *tsk;
	struct mm_struct *mm;
	unsigned long address;
	unsigned long acc_type;

	switch (insn & 0x380) {
	case 0x280:
		/* FDC instruction */
		fallthrough;
	case 0x380:
		/* PDC and FIC instructions */
		if (DEBUG_NATLB && printk_ratelimit()) {
			pr_warn("WARNING: nullifying cache flush/purge instruction\n");
			show_regs(regs);
		}
		if (insn & 0x20) {
			/* Base modification */
			breg = (insn >> 21) & 0x1f;
			xreg = (insn >> 16) & 0x1f;
			if (breg && xreg)
				regs->gr[breg] += regs->gr[xreg];
		}
		regs->gr[0] |= PSW_N;
		return 1;

	case 0x180:
		/* PROBE instruction */
		treg = insn & 0x1f;
		if (regs->isr) {
			tsk = current;
			mm = tsk->mm;
			if (mm) {
				/* Search for VMA */
				address = regs->ior;
				mmap_read_lock(mm);
				vma = find_vma_prev(mm, address, &prev_vma);
				mmap_read_unlock(mm);

				/*
				 * Check if access to the VMA is okay.
				 * We don't allow for stack expansion.
				 */
				acc_type = (insn & 0x40) ? VM_WRITE : VM_READ;
				if (vma
				    && address >= vma->vm_start
				    && (vma->vm_flags & acc_type) == acc_type)
					val = 1;
			}
		}
		if (treg)
			regs->gr[treg] = val;
		regs->gr[0] |= PSW_N;
		return 1;

	case 0x300:
		/* LPA instruction */
		if (insn & 0x20) {
			/* Base modification */
			breg = (insn >> 21) & 0x1f;
			xreg = (insn >> 16) & 0x1f;
			if (breg && xreg)
				regs->gr[breg] += regs->gr[xreg];
		}
		treg = insn & 0x1f;
		if (treg)
			regs->gr[treg] = 0;
		regs->gr[0] |= PSW_N;
		return 1;

	default:
		break;
	}

	return 0;
}
Commit	Line	Data
071327ec	1	/*
1da177e4 LT	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	*
	7	* Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
	8	* Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
	9	* Copyright 1999 Hewlett Packard Co.
	10	*
	11	*/
	12
	13	#include <linux/mm.h>
	14	#include <linux/ptrace.h>
	15	#include <linux/sched.h>
b17b0153	16	#include <linux/sched/debug.h>
1da177e4	17	#include <linux/interrupt.h>
a38671d6	18	#include <linux/extable.h>
70ffdb93	19	#include <linux/uaccess.h>
606f95e4	20	#include <linux/hugetlb.h>
af8a7926	21	#include <linux/perf_event.h>
1da177e4	22
1da177e4 LT	23	#include <asm/traps.h>
1da177e4 LT	24
67c35a3b JDA	25	#define DEBUG_NATLB 0
67c35a3b JDA	26
1da177e4 LT	27	/* Various important other fields */
	28	#define bit22set(x) (x & 0x00000200)
	29	#define bits23_25set(x) (x & 0x000001c0)
	30	#define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
	31	/* extended opcode is 0x6a */
	32
	33	#define BITSSET 0x1c0 /* for identifying LDCW */
	34
	35
fef47e2a HD	36	int show_unhandled_signals = 1;
fef47e2a HD	37
1da177e4 LT	38	/*
	39	* parisc_acctyp(unsigned int inst) --
	40	* Given a PA-RISC memory access instruction, determine if the
	41	* the instruction would perform a memory read or memory write
	42	* operation.
	43	*
	44	* This function assumes that the given instruction is a memory access
	45	* instruction (i.e. you should really only call it if you know that
	46	* the instruction has generated some sort of a memory access fault).
	47	*
	48	* Returns:
	49	* VM_READ if read operation
	50	* VM_WRITE if write operation
	51	* VM_EXEC if execute operation
	52	*/
a348eab3	53	unsigned long
1da177e4 LT	54	parisc_acctyp(unsigned long code, unsigned int inst)
	55	{
	56	if (code == 6 \|\| code == 16)
	57	return VM_EXEC;
	58
	59	switch (inst & 0xf0000000) {
	60	case 0x40000000: /* load */
	61	case 0x50000000: /* new load */
	62	return VM_READ;
	63
	64	case 0x60000000: /* store */
	65	case 0x70000000: /* new store */
	66	return VM_WRITE;
	67
	68	case 0x20000000: /* coproc */
	69	case 0x30000000: /* coproc2 */
	70	if (bit22set(inst))
	71	return VM_WRITE;
df561f66	72	fallthrough;
1da177e4 LT	73
	74	case 0x0: /* indexed/memory management */
	75	if (bit22set(inst)) {
	76	/*
	77	* Check for the 'Graphics Flush Read' instruction.
	78	* It resembles an FDC instruction, except for bits
	79	* 20 and 21. Any combination other than zero will
	80	* utilize the block mover functionality on some
	81	* older PA-RISC platforms. The case where a block
	82	* move is performed from VM to graphics IO space
	83	* should be treated as a READ.
	84	*
	85	* The significance of bits 20,21 in the FDC
	86	* instruction is:
	87	*
	88	* 00 Flush data cache (normal instruction behavior)
	89	* 01 Graphics flush write (IO space -> VM)
	90	* 10 Graphics flush read (VM -> IO space)
	91	* 11 Graphics flush read/write (VM <-> IO space)
	92	*/
	93	if (isGraphicsFlushRead(inst))
	94	return VM_READ;
	95	return VM_WRITE;
	96	} else {
	97	/*
	98	* Check for LDCWX and LDCWS (semaphore instructions).
	99	* If bits 23 through 25 are all 1's it is one of
	100	* the above two instructions and is a write.
	101	*
	102	* Note: With the limited bits we are looking at,
	103	* this will also catch PROBEW and PROBEWI. However,
	104	* these should never get in here because they don't
	105	* generate exceptions of the type:
	106	* Data TLB miss fault/data page fault
	107	* Data memory protection trap
	108	*/
	109	if (bits23_25set(inst) == BITSSET)
	110	return VM_WRITE;
	111	}
	112	return VM_READ; /* Default */
	113	}
	114	return VM_READ; /* Default */
	115	}
	116
	117	#undef bit22set
	118	#undef bits23_25set
	119	#undef isGraphicsFlushRead
	120	#undef BITSSET
	121
	122
	123	#if 0
	124	/* This is the treewalk to find a vma which is the highest that has
	125	* a start < addr. We're using find_vma_prev instead right now, but
	126	* we might want to use this at some point in the future. Probably
	127	* not, but I want it committed to CVS so I don't lose it :-)
	128	*/
	129	while (tree != vm_avl_empty) {
	130	if (tree->vm_start > addr) {
	131	tree = tree->vm_avl_left;
	132	} else {
	133	prev = tree;
	134	if (prev->vm_next == NULL)
	135	break;
	136	if (prev->vm_next->vm_start > addr)
137	break;
138	tree = tree->vm_avl_right;
139	}
140	}
141	#endif
142
c61c25eb KM	143	int fixup_exception(struct pt_regs *regs)
	144	{
	145	const struct exception_table_entry *fix;
	146
	147	fix = search_exception_tables(regs->iaoq[0]);
	148	if (fix) {
d19f5e41 HD	149	/*
	150	* Fix up get_user() and put_user().
	151	* ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant
	152	* bit in the relative address of the fixup routine to indicate
4b9d2a73 HD	153	* that gr[ASM_EXCEPTIONTABLE_REG] should be loaded with
4b9d2a73 HD	154	* -EFAULT to report a userspace access error.
d19f5e41 HD	155	*/
d19f5e41 HD	156	if (fix->fixup & 1) {
4b9d2a73	157	regs->gr[ASM_EXCEPTIONTABLE_REG] = -EFAULT;
d19f5e41 HD	158
	159	/* zero target register for get_user() */
	160	if (parisc_acctyp(0, regs->iir) == VM_READ) {
	161	int treg = regs->iir & 0x1f;
b752c7b2	162	BUG_ON(treg == 0);
d19f5e41 HD	163	regs->gr[treg] = 0;
	164	}
	165	}
	166
0de79858 HD	167	regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup;
0de79858 HD	168	regs->iaoq[0] &= ~3;
c61c25eb KM	169	/*
	170	* NOTE: In some cases the faulting instruction
	171	* may be in the delay slot of a branch. We
	172	* don't want to take the branch, so we don't
	173	* increment iaoq[1], instead we set it to be
	174	* iaoq[0]+4, and clear the B bit in the PSW
	175	*/
	176	regs->iaoq[1] = regs->iaoq[0] + 4;
	177	regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
	178
	179	return 1;
	180	}
	181
	182	return 0;
	183	}
	184
b391667e HD	185	/*
	186	* parisc hardware trap list
	187	*
	188	* Documented in section 3 "Addressing and Access Control" of the
	189	* "PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
	190	* https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf
	191	*
	192	* For implementation see handle_interruption() in traps.c
	193	*/
	194	static const char * const trap_description[] = {
	195	[1] "High-priority machine check (HPMC)",
	196	[2] "Power failure interrupt",
	197	[3] "Recovery counter trap",
	198	[5] "Low-priority machine check",
	199	[6] "Instruction TLB miss fault",
	200	[7] "Instruction access rights / protection trap",
	201	[8] "Illegal instruction trap",
	202	[9] "Break instruction trap",
	203	[10] "Privileged operation trap",
	204	[11] "Privileged register trap",
	205	[12] "Overflow trap",
	206	[13] "Conditional trap",
	207	[14] "FP Assist Exception trap",
	208	[15] "Data TLB miss fault",
	209	[16] "Non-access ITLB miss fault",
	210	[17] "Non-access DTLB miss fault",
	211	[18] "Data memory protection/unaligned access trap",
	212	[19] "Data memory break trap",
	213	[20] "TLB dirty bit trap",
	214	[21] "Page reference trap",
	215	[22] "Assist emulation trap",
	216	[25] "Taken branch trap",
	217	[26] "Data memory access rights trap",
	218	[27] "Data memory protection ID trap",
	219	[28] "Unaligned data reference trap",
	220	};
	221
0a862485 HD	222	const char *trap_name(unsigned long code)
	223	{
	224	const char *t = NULL;
	225
	226	if (code < ARRAY_SIZE(trap_description))
	227	t = trap_description[code];
	228
	229	return t ? t : "Unknown trap";
	230	}
	231
fef47e2a HD	232	/*
	233	* Print out info about fatal segfaults, if the show_unhandled_signals
	234	* sysctl is set:
	235	*/
	236	static inline void
	237	show_signal_msg(struct pt_regs *regs, unsigned long code,
	238	unsigned long address, struct task_struct *tsk,
	239	struct vm_area_struct *vma)
	240	{
	241	if (!unhandled_signal(tsk, SIGSEGV))
	242	return;
	243
	244	if (!printk_ratelimit())
	245	return;
	246
	247	pr_warn("\n");
	248	pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
	249	tsk->comm, code, address);
	250	print_vma_addr(KERN_CONT " in ", regs->iaoq[0]);
b391667e	251
b4a9eb4c	252	pr_cont("\ntrap #%lu: %s%c", code, trap_name(code),
b391667e HD	253	vma ? ',':'\n');
b391667e HD	254
fef47e2a	255	if (vma)
8351badf DC	256	pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
8351badf DC	257	vma->vm_start, vma->vm_end);
fef47e2a HD	258
	259	show_regs(regs);
	260	}
	261
1da177e4 LT	262	void do_page_fault(struct pt_regs *regs, unsigned long code,
	263	unsigned long address)
	264	{
	265	struct vm_area_struct vma, prev_vma;
2d8b22de JDA	266	struct task_struct *tsk;
2d8b22de JDA	267	struct mm_struct *mm;
1da177e4	268	unsigned long acc_type;
50a7ca3c	269	vm_fault_t fault = 0;
2d8b22de	270	unsigned int flags;
20dda87b	271	char *msg;
1da177e4	272
2d8b22de JDA	273	tsk = current;
2d8b22de JDA	274	mm = tsk->mm;
20dda87b JDA	275	if (!mm) {
20dda87b JDA	276	msg = "Page fault: no context";
2d8b22de	277	goto no_context;
20dda87b	278	}
2d8b22de	279
dde16072	280	flags = FAULT_FLAG_DEFAULT;
759496ba JW	281	if (user_mode(regs))
759496ba JW	282	flags \|= FAULT_FLAG_USER;
0772dac1 FP	283
0772dac1 FP	284	acc_type = parisc_acctyp(code, regs->iir);
759496ba JW	285	if (acc_type & VM_WRITE)
759496ba JW	286	flags \|= FAULT_FLAG_WRITE;
af8a7926	287	perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
38057477	288	retry:
d8ed45c5	289	mmap_read_lock(mm);
1da177e4 LT	290	vma = find_vma_prev(mm, address, &prev_vma);
	291	if (!vma \|\| address < vma->vm_start)
	292	goto check_expansion;
	293	/*
	294	* Ok, we have a good vm_area for this memory access. We still need to
	295	* check the access permissions.
	296	*/
	297
	298	good_area:
	299
1da177e4 LT	300	if ((vma->vm_flags & acc_type) != acc_type)
	301	goto bad_area;
	302
	303	/*
	304	* If for any reason at all we couldn't handle the fault, make
	305	* sure we exit gracefully rather than endlessly redo the
	306	* fault.
	307	*/
	308
af8a7926	309	fault = handle_mm_fault(vma, address, flags, regs);
38057477	310
4ef87322	311	if (fault_signal_pending(fault, regs))
38057477 KC	312	return;
38057477 KC	313
83c54070	314	if (unlikely(fault & VM_FAULT_ERROR)) {
1da177e4	315	/*
67a5a59d	316	* We hit a shared mapping outside of the file, or some
6e346228 LT	317	* other thing happened to us that made us unable to
6e346228 LT	318	* handle the page fault gracefully.
1da177e4	319	*/
83c54070 NP	320	if (fault & VM_FAULT_OOM)
83c54070 NP	321	goto out_of_memory;
33692f27 LT	322	else if (fault & VM_FAULT_SIGSEGV)
33692f27 LT	323	goto bad_area;
606f95e4 HD	324	else if (fault & (VM_FAULT_SIGBUS\|VM_FAULT_HWPOISON\|
606f95e4 HD	325	VM_FAULT_HWPOISON_LARGE))
83c54070 NP	326	goto bad_area;
83c54070 NP	327	BUG();
1da177e4	328	}
36ef159f QZ	329	if (fault & VM_FAULT_RETRY) {
	330	/*
	331	* No need to mmap_read_unlock(mm) as we would
	332	* have already released it in __lock_page_or_retry
	333	* in mm/filemap.c.
	334	*/
	335	flags \|= FAULT_FLAG_TRIED;
	336	goto retry;
38057477	337	}
d8ed45c5	338	mmap_read_unlock(mm);
1da177e4 LT	339	return;
	340
	341	check_expansion:
	342	vma = prev_vma;
	343	if (vma && (expand_stack(vma, address) == 0))
	344	goto good_area;
	345
	346	/*
	347	* Something tried to access memory that isn't in our memory map..
	348	*/
	349	bad_area:
d8ed45c5	350	mmap_read_unlock(mm);
1da177e4 LT	351
1da177e4 LT	352	if (user_mode(regs)) {
ccf75290	353	int signo, si_code;
fef47e2a	354
1f2048fd HD	355	switch (code) {
1f2048fd HD	356	case 15: /* Data TLB miss fault/Data page fault */
49d1cb2b HD	357	/* send SIGSEGV when outside of vma */
49d1cb2b HD	358	if (!vma \|\|
24746231	359	address < vma->vm_start \|\| address >= vma->vm_end) {
ccf75290 EB	360	signo = SIGSEGV;
ccf75290 EB	361	si_code = SEGV_MAPERR;
49d1cb2b HD	362	break;
	363	}
	364
	365	/* send SIGSEGV for wrong permissions */
	366	if ((vma->vm_flags & acc_type) != acc_type) {
ccf75290 EB	367	signo = SIGSEGV;
ccf75290 EB	368	si_code = SEGV_ACCERR;
49d1cb2b HD	369	break;
	370	}
	371
	372	/* probably address is outside of mapped file */
df561f66	373	fallthrough;
1f2048fd HD	374	case 17: /* NA data TLB miss / page fault */
1f2048fd HD	375	case 18: /* Unaligned access - PCXS only */
ccf75290 EB	376	signo = SIGBUS;
ccf75290 EB	377	si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
1f2048fd HD	378	break;
	379	case 16: /* Non-access instruction TLB miss fault */
	380	case 26: /* PCXL: Data memory access rights trap */
	381	default:
ccf75290 EB	382	signo = SIGSEGV;
ccf75290 EB	383	si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
49d1cb2b	384	break;
1f2048fd	385	}
606f95e4 HD	386	#ifdef CONFIG_MEMORY_FAILURE
606f95e4 HD	387	if (fault & (VM_FAULT_HWPOISON\|VM_FAULT_HWPOISON_LARGE)) {
c2b0e0d3	388	unsigned int lsb = 0;
606f95e4 HD	389	printk(KERN_ERR
	390	"MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n",
	391	tsk->comm, tsk->pid, address);
c2b0e0d3 EB	392	/*
	393	* Either small page or large page may be poisoned.
	394	* In other words, VM_FAULT_HWPOISON_LARGE and
	395	* VM_FAULT_HWPOISON are mutually exclusive.
	396	*/
	397	if (fault & VM_FAULT_HWPOISON_LARGE)
	398	lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
	399	else if (fault & VM_FAULT_HWPOISON)
	400	lsb = PAGE_SHIFT;
	401
	402	force_sig_mceerr(BUS_MCEERR_AR, (void __user *) address,
f8eac901	403	lsb);
c2b0e0d3	404	return;
606f95e4 HD	405	}
606f95e4 HD	406	#endif
c2b0e0d3	407	show_signal_msg(regs, code, address, tsk, vma);
606f95e4	408
2e1661d2	409	force_sig_fault(signo, si_code, (void __user *) address);
1da177e4 LT	410	return;
1da177e4 LT	411	}
20dda87b	412	msg = "Page fault: bad address";
1da177e4 LT	413
	414	no_context:
	415
c61c25eb KM	416	if (!user_mode(regs) && fixup_exception(regs)) {
c61c25eb KM	417	return;
1da177e4 LT	418	}
1da177e4 LT	419
20dda87b	420	parisc_terminate(msg, regs, code, address);
1da177e4	421
20dda87b	422	out_of_memory:
d8ed45c5	423	mmap_read_unlock(mm);
20dda87b JDA	424	if (!user_mode(regs)) {
20dda87b JDA	425	msg = "Page fault: out of memory";
53e30d02	426	goto no_context;
20dda87b	427	}
53e30d02	428	pagefault_out_of_memory();
1da177e4	429	}
e00b0a2a JDA	430
	431	/* Handle non-access data TLB miss faults.
	432	*
	433	* For probe instructions, accesses to userspace are considered allowed
	434	* if they lie in a valid VMA and the access type matches. We are not
	435	* allowed to handle MM faults here so there may be situations where an
	436	* actual access would fail even though a probe was successful.
	437	*/
	438	int
	439	handle_nadtlb_fault(struct pt_regs *regs)
	440	{
	441	unsigned long insn = regs->iir;
	442	int breg, treg, xreg, val = 0;
	443	struct vm_area_struct vma, prev_vma;
	444	struct task_struct *tsk;
	445	struct mm_struct *mm;
	446	unsigned long address;
	447	unsigned long acc_type;
	448
	449	switch (insn & 0x380) {
	450	case 0x280:
	451	/* FDC instruction */
	452	fallthrough;
	453	case 0x380:
	454	/* PDC and FIC instructions */
67c35a3b JDA	455	if (DEBUG_NATLB && printk_ratelimit()) {
67c35a3b JDA	456	pr_warn("WARNING: nullifying cache flush/purge instruction\n");
e00b0a2a JDA	457	show_regs(regs);
	458	}
	459	if (insn & 0x20) {
	460	/* Base modification */
	461	breg = (insn >> 21) & 0x1f;
	462	xreg = (insn >> 16) & 0x1f;
	463	if (breg && xreg)
	464	regs->gr[breg] += regs->gr[xreg];
	465	}
	466	regs->gr[0] \|= PSW_N;
	467	return 1;
	468
	469	case 0x180:
	470	/* PROBE instruction */
	471	treg = insn & 0x1f;
	472	if (regs->isr) {
	473	tsk = current;
	474	mm = tsk->mm;
	475	if (mm) {
	476	/* Search for VMA */
	477	address = regs->ior;
	478	mmap_read_lock(mm);
	479	vma = find_vma_prev(mm, address, &prev_vma);
	480	mmap_read_unlock(mm);
	481
	482	/*
	483	* Check if access to the VMA is okay.
	484	* We don't allow for stack expansion.
	485	*/
	486	acc_type = (insn & 0x40) ? VM_WRITE : VM_READ;
	487	if (vma
	488	&& address >= vma->vm_start
	489	&& (vma->vm_flags & acc_type) == acc_type)
	490	val = 1;
	491	}
	492	}
	493	if (treg)
	494	regs->gr[treg] = val;
	495	regs->gr[0] \|= PSW_N;
	496	return 1;
	497
	498	case 0x300:
	499	/* LPA instruction */
	500	if (insn & 0x20) {
	501	/* Base modification */
	502	breg = (insn >> 21) & 0x1f;
	503	xreg = (insn >> 16) & 0x1f;
	504	if (breg && xreg)
	505	regs->gr[breg] += regs->gr[xreg];
	506	}
	507	treg = insn & 0x1f;
	508	if (treg)
	509	regs->gr[treg] = 0;
	510	regs->gr[0] \|= PSW_N;
	511	return 1;
	512
	513	default:
	514	break;
	515	}
	516
	517	return 0;
	518	}