[linux-block.git] / arch / parisc / kernel / unaligned.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *    Unaligned memory access handler
 *
 *    Copyright (C) 2001 Randolph Chung <tausq@debian.org>
 *    Copyright (C) 2022 Helge Deller <deller@gmx.de>
 *    Significantly tweaked by LaMont Jones <lamont@debian.org>
 */

#include <linux/sched/signal.h>
#include <linux/signal.h>
#include <linux/ratelimit.h>
#include <linux/uaccess.h>
#include <linux/sysctl.h>
#include <asm/unaligned.h>
#include <asm/hardirq.h>
#include <asm/traps.h>

/* #define DEBUG_UNALIGNED 1 */

#ifdef DEBUG_UNALIGNED
#define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

#define RFMT "%#08lx"

/* 1111 1100 0000 0000 0001 0011 1100 0000 */
#define OPCODE1(a,b,c)	((a)<<26|(b)<<12|(c)<<6) 
#define OPCODE2(a,b)	((a)<<26|(b)<<1)
#define OPCODE3(a,b)	((a)<<26|(b)<<2)
#define OPCODE4(a)	((a)<<26)
#define OPCODE1_MASK	OPCODE1(0x3f,1,0xf)
#define OPCODE2_MASK 	OPCODE2(0x3f,1)
#define OPCODE3_MASK	OPCODE3(0x3f,1)
#define OPCODE4_MASK    OPCODE4(0x3f)

/* skip LDB - never unaligned (index) */
#define OPCODE_LDH_I	OPCODE1(0x03,0,0x1)
#define OPCODE_LDW_I	OPCODE1(0x03,0,0x2)
#define OPCODE_LDD_I	OPCODE1(0x03,0,0x3)
#define OPCODE_LDDA_I	OPCODE1(0x03,0,0x4)
#define OPCODE_LDCD_I	OPCODE1(0x03,0,0x5)
#define OPCODE_LDWA_I	OPCODE1(0x03,0,0x6)
#define OPCODE_LDCW_I	OPCODE1(0x03,0,0x7)
/* skip LDB - never unaligned (short) */
#define OPCODE_LDH_S	OPCODE1(0x03,1,0x1)
#define OPCODE_LDW_S	OPCODE1(0x03,1,0x2)
#define OPCODE_LDD_S	OPCODE1(0x03,1,0x3)
#define OPCODE_LDDA_S	OPCODE1(0x03,1,0x4)
#define OPCODE_LDCD_S	OPCODE1(0x03,1,0x5)
#define OPCODE_LDWA_S	OPCODE1(0x03,1,0x6)
#define OPCODE_LDCW_S	OPCODE1(0x03,1,0x7)
/* skip STB - never unaligned */
#define OPCODE_STH	OPCODE1(0x03,1,0x9)
#define OPCODE_STW	OPCODE1(0x03,1,0xa)
#define OPCODE_STD	OPCODE1(0x03,1,0xb)
/* skip STBY - never unaligned */
/* skip STDBY - never unaligned */
#define OPCODE_STWA	OPCODE1(0x03,1,0xe)
#define OPCODE_STDA	OPCODE1(0x03,1,0xf)

#define OPCODE_FLDWX	OPCODE1(0x09,0,0x0)
#define OPCODE_FLDWXR	OPCODE1(0x09,0,0x1)
#define OPCODE_FSTWX	OPCODE1(0x09,0,0x8)
#define OPCODE_FSTWXR	OPCODE1(0x09,0,0x9)
#define OPCODE_FLDWS	OPCODE1(0x09,1,0x0)
#define OPCODE_FLDWSR	OPCODE1(0x09,1,0x1)
#define OPCODE_FSTWS	OPCODE1(0x09,1,0x8)
#define OPCODE_FSTWSR	OPCODE1(0x09,1,0x9)
#define OPCODE_FLDDX	OPCODE1(0x0b,0,0x0)
#define OPCODE_FSTDX	OPCODE1(0x0b,0,0x8)
#define OPCODE_FLDDS	OPCODE1(0x0b,1,0x0)
#define OPCODE_FSTDS	OPCODE1(0x0b,1,0x8)

#define OPCODE_LDD_L	OPCODE2(0x14,0)
#define OPCODE_FLDD_L	OPCODE2(0x14,1)
#define OPCODE_STD_L	OPCODE2(0x1c,0)
#define OPCODE_FSTD_L	OPCODE2(0x1c,1)

#define OPCODE_LDW_M	OPCODE3(0x17,1)
#define OPCODE_FLDW_L	OPCODE3(0x17,0)
#define OPCODE_FSTW_L	OPCODE3(0x1f,0)
#define OPCODE_STW_M	OPCODE3(0x1f,1)

#define OPCODE_LDH_L    OPCODE4(0x11)
#define OPCODE_LDW_L    OPCODE4(0x12)
#define OPCODE_LDWM     OPCODE4(0x13)
#define OPCODE_STH_L    OPCODE4(0x19)
#define OPCODE_STW_L    OPCODE4(0x1A)
#define OPCODE_STWM     OPCODE4(0x1B)

#define MAJOR_OP(i) (((i)>>26)&0x3f)
#define R1(i) (((i)>>21)&0x1f)
#define R2(i) (((i)>>16)&0x1f)
#define R3(i) ((i)&0x1f)
#define FR3(i) ((((i)&0x1f)<<1)|(((i)>>6)&1))
#define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0))
#define IM5_2(i) IM((i)>>16,5)
#define IM5_3(i) IM((i),5)
#define IM14(i) IM((i),14)

#define ERR_NOTHANDLED	-1

int unaligned_enabled __read_mostly = 1;

static int emulate_ldh(struct pt_regs *regs, int toreg)
{
	unsigned long saddr = regs->ior;
	unsigned long val = 0, temp1;
	ASM_EXCEPTIONTABLE_VAR(ret);

	DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n", 
		regs->isr, regs->ior, toreg);

	__asm__ __volatile__  (
"	mtsp	%4, %%sr1\n"
"1:	ldbs	0(%%sr1,%3), %2\n"
"2:	ldbs	1(%%sr1,%3), %0\n"
"	depw	%2, 23, 24, %0\n"
"3:	\n"
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
	: "+r" (val), "+r" (ret), "=&r" (temp1)
	: "r" (saddr), "r" (regs->isr) );

	DPRINTF("val = " RFMT "\n", val);

	if (toreg)
		regs->gr[toreg] = val;

	return ret;
}

static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
{
	unsigned long saddr = regs->ior;
	unsigned long val = 0, temp1, temp2;
	ASM_EXCEPTIONTABLE_VAR(ret);

	DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n", 
		regs->isr, regs->ior, toreg);

	__asm__ __volatile__  (
"	zdep	%4,28,2,%2\n"		/* r19=(ofs&3)*8 */
"	mtsp	%5, %%sr1\n"
"	depw	%%r0,31,2,%4\n"
"1:	ldw	0(%%sr1,%4),%0\n"
"2:	ldw	4(%%sr1,%4),%3\n"
"	subi	32,%2,%2\n"
"	mtctl	%2,11\n"
"	vshd	%0,%3,%0\n"
"3:	\n"
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
	: "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
	: "r" (saddr), "r" (regs->isr) );

	DPRINTF("val = " RFMT "\n", val);

	if (flop)
		((__u32*)(regs->fr))[toreg] = val;
	else if (toreg)
		regs->gr[toreg] = val;

	return ret;
}
static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
{
	unsigned long saddr = regs->ior;
	__u64 val = 0;
	ASM_EXCEPTIONTABLE_VAR(ret);

	DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n", 
		regs->isr, regs->ior, toreg);

	if (!IS_ENABLED(CONFIG_64BIT) && !flop)
		return ERR_NOTHANDLED;

#ifdef CONFIG_64BIT
	__asm__ __volatile__  (
"	depd,z	%3,60,3,%%r19\n"		/* r19=(ofs&7)*8 */
"	mtsp	%4, %%sr1\n"
"	depd	%%r0,63,3,%3\n"
"1:	ldd	0(%%sr1,%3),%0\n"
"2:	ldd	8(%%sr1,%3),%%r20\n"
"	subi	64,%%r19,%%r19\n"
"	mtsar	%%r19\n"
"	shrpd	%0,%%r20,%%sar,%0\n"
"3:	\n"
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
	: "=r" (val), "+r" (ret)
	: "0" (val), "r" (saddr), "r" (regs->isr)
	: "r19", "r20" );
#else
    {
	unsigned long shift, temp1;
	__asm__ __volatile__  (
"	zdep	%2,29,2,%3\n"		/* r19=(ofs&3)*8 */
"	mtsp	%5, %%sr1\n"
"	dep	%%r0,31,2,%2\n"
"1:	ldw	0(%%sr1,%2),%0\n"
"2:	ldw	4(%%sr1,%2),%R0\n"
"3:	ldw	8(%%sr1,%2),%4\n"
"	subi	32,%3,%3\n"
"	mtsar	%3\n"
"	vshd	%0,%R0,%0\n"
"	vshd	%R0,%4,%R0\n"
"4:	\n"
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
	: "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
	: "r" (regs->isr) );
    }
#endif

	DPRINTF("val = 0x%llx\n", val);

	if (flop)
		regs->fr[toreg] = val;
	else if (toreg)
		regs->gr[toreg] = val;

	return ret;
}

static int emulate_sth(struct pt_regs *regs, int frreg)
{
	unsigned long val = regs->gr[frreg], temp1;
	ASM_EXCEPTIONTABLE_VAR(ret);

	if (!frreg)
		val = 0;

	DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
		val, regs->isr, regs->ior);

	__asm__ __volatile__ (
"	mtsp %4, %%sr1\n"
"	extrw,u %2, 23, 8, %1\n"
"1:	stb %1, 0(%%sr1, %3)\n"
"2:	stb %2, 1(%%sr1, %3)\n"
"3:	\n"
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
	: "+r" (ret), "=&r" (temp1)
	: "r" (val), "r" (regs->ior), "r" (regs->isr) );

	return ret;
}

static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
{
	unsigned long val;
	ASM_EXCEPTIONTABLE_VAR(ret);

	if (flop)
		val = ((__u32*)(regs->fr))[frreg];
	else if (frreg)
		val = regs->gr[frreg];
	else
		val = 0;

	DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
		val, regs->isr, regs->ior);


	__asm__ __volatile__ (
"	mtsp %3, %%sr1\n"
"	zdep	%2, 28, 2, %%r19\n"
"	dep	%%r0, 31, 2, %2\n"
"	mtsar	%%r19\n"
"	depwi,z	-2, %%sar, 32, %%r19\n"
"1:	ldw	0(%%sr1,%2),%%r20\n"
"2:	ldw	4(%%sr1,%2),%%r21\n"
"	vshd	%%r0, %1, %%r22\n"
"	vshd	%1, %%r0, %%r1\n"
"	and	%%r20, %%r19, %%r20\n"
"	andcm	%%r21, %%r19, %%r21\n"
"	or	%%r22, %%r20, %%r20\n"
"	or	%%r1, %%r21, %%r21\n"
"	stw	%%r20,0(%%sr1,%2)\n"
"	stw	%%r21,4(%%sr1,%2)\n"
"3:	\n"
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
	: "+r" (ret)
	: "r" (val), "r" (regs->ior), "r" (regs->isr)
	: "r19", "r20", "r21", "r22", "r1" );

	return ret;
}
static int emulate_std(struct pt_regs *regs, int frreg, int flop)
{
	__u64 val;
	ASM_EXCEPTIONTABLE_VAR(ret);

	if (flop)
		val = regs->fr[frreg];
	else if (frreg)
		val = regs->gr[frreg];
	else
		val = 0;

	DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg, 
		val,  regs->isr, regs->ior);

	if (!IS_ENABLED(CONFIG_64BIT) && !flop)
		return ERR_NOTHANDLED;

#ifdef CONFIG_64BIT
	__asm__ __volatile__ (
"	mtsp %3, %%sr1\n"
"	depd,z	%2, 60, 3, %%r19\n"
"	depd	%%r0, 63, 3, %2\n"
"	mtsar	%%r19\n"
"	depdi,z	-2, %%sar, 64, %%r19\n"
"1:	ldd	0(%%sr1,%2),%%r20\n"
"2:	ldd	8(%%sr1,%2),%%r21\n"
"	shrpd	%%r0, %1, %%sar, %%r22\n"
"	shrpd	%1, %%r0, %%sar, %%r1\n"
"	and	%%r20, %%r19, %%r20\n"
"	andcm	%%r21, %%r19, %%r21\n"
"	or	%%r22, %%r20, %%r20\n"
"	or	%%r1, %%r21, %%r21\n"
"3:	std	%%r20,0(%%sr1,%2)\n"
"4:	std	%%r21,8(%%sr1,%2)\n"
"5:	\n"
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
	: "+r" (ret)
	: "r" (val), "r" (regs->ior), "r" (regs->isr)
	: "r19", "r20", "r21", "r22", "r1" );
#else
    {
	__asm__ __volatile__ (
"	mtsp	%3, %%sr1\n"
"	zdep	%R1, 29, 2, %%r19\n"
"	dep	%%r0, 31, 2, %2\n"
"	mtsar	%%r19\n"
"	zvdepi	-2, 32, %%r19\n"
"1:	ldw	0(%%sr1,%2),%%r20\n"
"2:	ldw	8(%%sr1,%2),%%r21\n"
"	vshd	%1, %R1, %%r1\n"
"	vshd	%%r0, %1, %1\n"
"	vshd	%R1, %%r0, %R1\n"
"	and	%%r20, %%r19, %%r20\n"
"	andcm	%%r21, %%r19, %%r21\n"
"	or	%1, %%r20, %1\n"
"	or	%R1, %%r21, %R1\n"
"3:	stw	%1,0(%%sr1,%2)\n"
"4:	stw	%%r1,4(%%sr1,%2)\n"
"5:	stw	%R1,8(%%sr1,%2)\n"
"6:	\n"
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
	: "+r" (ret)
	: "r" (val), "r" (regs->ior), "r" (regs->isr)
	: "r19", "r20", "r21", "r1" );
    }
#endif

	return ret;
}

void handle_unaligned(struct pt_regs *regs)
{
	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
	unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
	int modify = 0;
	int ret = ERR_NOTHANDLED;

	__inc_irq_stat(irq_unaligned_count);

	/* log a message with pacing */
	if (user_mode(regs)) {
		if (current->thread.flags & PARISC_UAC_SIGBUS) {
			goto force_sigbus;
		}

		if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
			__ratelimit(&ratelimit)) {
			printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
				" at ip " RFMT " (iir " RFMT ")\n",
				current->comm, task_pid_nr(current), regs->ior,
				regs->iaoq[0], regs->iir);
#ifdef DEBUG_UNALIGNED
			show_regs(regs);
#endif		
		}

		if (!unaligned_enabled)
			goto force_sigbus;
	}

	/* handle modification - OK, it's ugly, see the instruction manual */
	switch (MAJOR_OP(regs->iir))
	{
	case 0x03:
	case 0x09:
	case 0x0b:
		if (regs->iir&0x20)
		{
			modify = 1;
			if (regs->iir&0x1000)		/* short loads */
				if (regs->iir&0x200)
					newbase += IM5_3(regs->iir);
				else
					newbase += IM5_2(regs->iir);
			else if (regs->iir&0x2000)	/* scaled indexed */
			{
				int shift=0;
				switch (regs->iir & OPCODE1_MASK)
				{
				case OPCODE_LDH_I:
					shift= 1; break;
				case OPCODE_LDW_I:
					shift= 2; break;
				case OPCODE_LDD_I:
				case OPCODE_LDDA_I:
					shift= 3; break;
				}
				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
			} else				/* simple indexed */
				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
		}
		break;
	case 0x13:
	case 0x1b:
		modify = 1;
		newbase += IM14(regs->iir);
		break;
	case 0x14:
	case 0x1c:
		if (regs->iir&8)
		{
			modify = 1;
			newbase += IM14(regs->iir&~0xe);
		}
		break;
	case 0x16:
	case 0x1e:
		modify = 1;
		newbase += IM14(regs->iir&6);
		break;
	case 0x17:
	case 0x1f:
		if (regs->iir&4)
		{
			modify = 1;
			newbase += IM14(regs->iir&~4);
		}
		break;
	}

	/* TODO: make this cleaner... */
	switch (regs->iir & OPCODE1_MASK)
	{
	case OPCODE_LDH_I:
	case OPCODE_LDH_S:
		ret = emulate_ldh(regs, R3(regs->iir));
		break;

	case OPCODE_LDW_I:
	case OPCODE_LDWA_I:
	case OPCODE_LDW_S:
	case OPCODE_LDWA_S:
		ret = emulate_ldw(regs, R3(regs->iir), 0);
		break;

	case OPCODE_STH:
		ret = emulate_sth(regs, R2(regs->iir));
		break;

	case OPCODE_STW:
	case OPCODE_STWA:
		ret = emulate_stw(regs, R2(regs->iir), 0);
		break;

#ifdef CONFIG_64BIT
	case OPCODE_LDD_I:
	case OPCODE_LDDA_I:
	case OPCODE_LDD_S:
	case OPCODE_LDDA_S:
		ret = emulate_ldd(regs, R3(regs->iir), 0);
		break;

	case OPCODE_STD:
	case OPCODE_STDA:
		ret = emulate_std(regs, R2(regs->iir), 0);
		break;
#endif

	case OPCODE_FLDWX:
	case OPCODE_FLDWS:
	case OPCODE_FLDWXR:
	case OPCODE_FLDWSR:
		ret = emulate_ldw(regs, FR3(regs->iir), 1);
		break;

	case OPCODE_FLDDX:
	case OPCODE_FLDDS:
		ret = emulate_ldd(regs, R3(regs->iir), 1);
		break;

	case OPCODE_FSTWX:
	case OPCODE_FSTWS:
	case OPCODE_FSTWXR:
	case OPCODE_FSTWSR:
		ret = emulate_stw(regs, FR3(regs->iir), 1);
		break;

	case OPCODE_FSTDX:
	case OPCODE_FSTDS:
		ret = emulate_std(regs, R3(regs->iir), 1);
		break;

	case OPCODE_LDCD_I:
	case OPCODE_LDCW_I:
	case OPCODE_LDCD_S:
	case OPCODE_LDCW_S:
		ret = ERR_NOTHANDLED;	/* "undefined", but lets kill them. */
		break;
	}
	switch (regs->iir & OPCODE2_MASK)
	{
	case OPCODE_FLDD_L:
		ret = emulate_ldd(regs,R2(regs->iir),1);
		break;
	case OPCODE_FSTD_L:
		ret = emulate_std(regs, R2(regs->iir),1);
		break;
#ifdef CONFIG_64BIT
	case OPCODE_LDD_L:
		ret = emulate_ldd(regs, R2(regs->iir),0);
		break;
	case OPCODE_STD_L:
		ret = emulate_std(regs, R2(regs->iir),0);
		break;
#endif
	}
	switch (regs->iir & OPCODE3_MASK)
	{
	case OPCODE_FLDW_L:
		ret = emulate_ldw(regs, R2(regs->iir), 1);
		break;
	case OPCODE_LDW_M:
		ret = emulate_ldw(regs, R2(regs->iir), 0);
		break;

	case OPCODE_FSTW_L:
		ret = emulate_stw(regs, R2(regs->iir),1);
		break;
	case OPCODE_STW_M:
		ret = emulate_stw(regs, R2(regs->iir),0);
		break;
	}
	switch (regs->iir & OPCODE4_MASK)
	{
	case OPCODE_LDH_L:
		ret = emulate_ldh(regs, R2(regs->iir));
		break;
	case OPCODE_LDW_L:
	case OPCODE_LDWM:
		ret = emulate_ldw(regs, R2(regs->iir),0);
		break;
	case OPCODE_STH_L:
		ret = emulate_sth(regs, R2(regs->iir));
		break;
	case OPCODE_STW_L:
	case OPCODE_STWM:
		ret = emulate_stw(regs, R2(regs->iir),0);
		break;
	}

	if (ret == 0 && modify && R1(regs->iir))
		regs->gr[R1(regs->iir)] = newbase;


	if (ret == ERR_NOTHANDLED)
		printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);

	DPRINTF("ret = %d\n", ret);

	if (ret)
	{
		/*
		 * The unaligned handler failed.
		 * If we were called by __get_user() or __put_user() jump
		 * to it's exception fixup handler instead of crashing.
		 */
		if (!user_mode(regs) && fixup_exception(regs))
			return;

		printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
		die_if_kernel("Unaligned data reference", regs, 28);

		if (ret == -EFAULT)
		{
			force_sig_fault(SIGSEGV, SEGV_MAPERR,
					(void __user *)regs->ior);
		}
		else
		{
force_sigbus:
			/* couldn't handle it ... */
			force_sig_fault(SIGBUS, BUS_ADRALN,
					(void __user *)regs->ior);
		}
		
		return;
	}

	/* else we handled it, let life go on. */
	regs->gr[0]|=PSW_N;
}

/*
 * NB: check_unaligned() is only used for PCXS processors right
 * now, so we only check for PA1.1 encodings at this point.
 */

int
check_unaligned(struct pt_regs *regs)
{
	unsigned long align_mask;

	/* Get alignment mask */

	align_mask = 0UL;
	switch (regs->iir & OPCODE1_MASK) {

	case OPCODE_LDH_I:
	case OPCODE_LDH_S:
	case OPCODE_STH:
		align_mask = 1UL;
		break;

	case OPCODE_LDW_I:
	case OPCODE_LDWA_I:
	case OPCODE_LDW_S:
	case OPCODE_LDWA_S:
	case OPCODE_STW:
	case OPCODE_STWA:
		align_mask = 3UL;
		break;

	default:
		switch (regs->iir & OPCODE4_MASK) {
		case OPCODE_LDH_L:
		case OPCODE_STH_L:
			align_mask = 1UL;
			break;
		case OPCODE_LDW_L:
		case OPCODE_LDWM:
		case OPCODE_STW_L:
		case OPCODE_STWM:
			align_mask = 3UL;
			break;
		}
		break;
	}

	return (int)(regs->ior & align_mask);
}
Commit	Line	Data
de6cc651	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* Unaligned memory access handler
	4	*
	5	* Copyright (C) 2001 Randolph Chung <tausq@debian.org>
e5e9e7f2	6	* Copyright (C) 2022 Helge Deller <deller@gmx.de>
1da177e4	7	* Significantly tweaked by LaMont Jones <lamont@debian.org>
1da177e4 LT	8	*/
1da177e4 LT	9
3f07c014	10	#include <linux/sched/signal.h>
e6fc0449	11	#include <linux/signal.h>
6ee77658	12	#include <linux/ratelimit.h>
7c0f6ba6	13	#include <linux/uaccess.h>
66f80386	14	#include <linux/sysctl.h>
646d0746	15	#include <asm/unaligned.h>
d0c3be80	16	#include <asm/hardirq.h>
58f1c654	17	#include <asm/traps.h>
1da177e4 LT	18
	19	/* #define DEBUG_UNALIGNED 1 */
	20
	21	#ifdef DEBUG_UNALIGNED
91bae23c	22	#define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0)
1da177e4 LT	23	#else
	24	#define DPRINTF(fmt, args...)
	25	#endif
	26
e5e9e7f2	27	#define RFMT "%#08lx"
1da177e4	28
1da177e4 LT	29	/* 1111 1100 0000 0000 0001 0011 1100 0000 */
	30	#define OPCODE1(a,b,c) ((a)<<26\|(b)<<12\|(c)<<6)
	31	#define OPCODE2(a,b) ((a)<<26\|(b)<<1)
	32	#define OPCODE3(a,b) ((a)<<26\|(b)<<2)
	33	#define OPCODE4(a) ((a)<<26)
	34	#define OPCODE1_MASK OPCODE1(0x3f,1,0xf)
	35	#define OPCODE2_MASK OPCODE2(0x3f,1)
	36	#define OPCODE3_MASK OPCODE3(0x3f,1)
	37	#define OPCODE4_MASK OPCODE4(0x3f)
	38
	39	/* skip LDB - never unaligned (index) */
	40	#define OPCODE_LDH_I OPCODE1(0x03,0,0x1)
	41	#define OPCODE_LDW_I OPCODE1(0x03,0,0x2)
	42	#define OPCODE_LDD_I OPCODE1(0x03,0,0x3)
	43	#define OPCODE_LDDA_I OPCODE1(0x03,0,0x4)
	44	#define OPCODE_LDCD_I OPCODE1(0x03,0,0x5)
	45	#define OPCODE_LDWA_I OPCODE1(0x03,0,0x6)
	46	#define OPCODE_LDCW_I OPCODE1(0x03,0,0x7)
	47	/* skip LDB - never unaligned (short) */
	48	#define OPCODE_LDH_S OPCODE1(0x03,1,0x1)
	49	#define OPCODE_LDW_S OPCODE1(0x03,1,0x2)
	50	#define OPCODE_LDD_S OPCODE1(0x03,1,0x3)
	51	#define OPCODE_LDDA_S OPCODE1(0x03,1,0x4)
	52	#define OPCODE_LDCD_S OPCODE1(0x03,1,0x5)
	53	#define OPCODE_LDWA_S OPCODE1(0x03,1,0x6)
	54	#define OPCODE_LDCW_S OPCODE1(0x03,1,0x7)
	55	/* skip STB - never unaligned */
	56	#define OPCODE_STH OPCODE1(0x03,1,0x9)
	57	#define OPCODE_STW OPCODE1(0x03,1,0xa)
	58	#define OPCODE_STD OPCODE1(0x03,1,0xb)
	59	/* skip STBY - never unaligned */
	60	/* skip STDBY - never unaligned */
	61	#define OPCODE_STWA OPCODE1(0x03,1,0xe)
	62	#define OPCODE_STDA OPCODE1(0x03,1,0xf)
	63
	64	#define OPCODE_FLDWX OPCODE1(0x09,0,0x0)
	65	#define OPCODE_FLDWXR OPCODE1(0x09,0,0x1)
	66	#define OPCODE_FSTWX OPCODE1(0x09,0,0x8)
	67	#define OPCODE_FSTWXR OPCODE1(0x09,0,0x9)
	68	#define OPCODE_FLDWS OPCODE1(0x09,1,0x0)
	69	#define OPCODE_FLDWSR OPCODE1(0x09,1,0x1)
	70	#define OPCODE_FSTWS OPCODE1(0x09,1,0x8)
	71	#define OPCODE_FSTWSR OPCODE1(0x09,1,0x9)
	72	#define OPCODE_FLDDX OPCODE1(0x0b,0,0x0)
	73	#define OPCODE_FSTDX OPCODE1(0x0b,0,0x8)
	74	#define OPCODE_FLDDS OPCODE1(0x0b,1,0x0)
	75	#define OPCODE_FSTDS OPCODE1(0x0b,1,0x8)
	76
	77	#define OPCODE_LDD_L OPCODE2(0x14,0)
	78	#define OPCODE_FLDD_L OPCODE2(0x14,1)
	79	#define OPCODE_STD_L OPCODE2(0x1c,0)
	80	#define OPCODE_FSTD_L OPCODE2(0x1c,1)
	81
	82	#define OPCODE_LDW_M OPCODE3(0x17,1)
	83	#define OPCODE_FLDW_L OPCODE3(0x17,0)
	84	#define OPCODE_FSTW_L OPCODE3(0x1f,0)
	85	#define OPCODE_STW_M OPCODE3(0x1f,1)
	86
	87	#define OPCODE_LDH_L OPCODE4(0x11)
	88	#define OPCODE_LDW_L OPCODE4(0x12)
	89	#define OPCODE_LDWM OPCODE4(0x13)
	90	#define OPCODE_STH_L OPCODE4(0x19)
	91	#define OPCODE_STW_L OPCODE4(0x1A)
	92	#define OPCODE_STWM OPCODE4(0x1B)
93
94	#define MAJOR_OP(i) (((i)>>26)&0x3f)
95	#define R1(i) (((i)>>21)&0x1f)
96	#define R2(i) (((i)>>16)&0x1f)
97	#define R3(i) ((i)&0x1f)
7ae1f550	98	#define FR3(i) ((((i)&0x1f)<<1)\|(((i)>>6)&1))
1da177e4 LT	99	#define IM(i,n) (((i)>>1&((1<<(n-1))-1))\|((i)&1?((0-1L)<<(n-1)):0))
	100	#define IM5_2(i) IM((i)>>16,5)
	101	#define IM5_3(i) IM((i),5)
	102	#define IM14(i) IM((i),14)
	103
	104	#define ERR_NOTHANDLED -1
1da177e4	105
8039de10	106	int unaligned_enabled __read_mostly = 1;
1da177e4	107
1da177e4 LT	108	static int emulate_ldh(struct pt_regs *regs, int toreg)
	109	{
	110	unsigned long saddr = regs->ior;
f85b2af1	111	unsigned long val = 0, temp1;
d1434e03	112	ASM_EXCEPTIONTABLE_VAR(ret);
1da177e4 LT	113
	114	DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n",
	115	regs->isr, regs->ior, toreg);
	116
	117	__asm__ __volatile__ (
	118	" mtsp %4, %%sr1\n"
f85b2af1	119	"1: ldbs 0(%%sr1,%3), %2\n"
1da177e4	120	"2: ldbs 1(%%sr1,%3), %0\n"
f85b2af1	121	" depw %2, 23, 24, %0\n"
1da177e4	122	"3: \n"
8b1d7239 HD	123	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
8b1d7239 HD	124	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
f85b2af1 HD	125	: "+r" (val), "+r" (ret), "=&r" (temp1)
f85b2af1 HD	126	: "r" (saddr), "r" (regs->isr) );
1da177e4	127
e5e9e7f2	128	DPRINTF("val = " RFMT "\n", val);
1da177e4 LT	129
	130	if (toreg)
	131	regs->gr[toreg] = val;
	132
	133	return ret;
	134	}
	135
	136	static int emulate_ldw(struct pt_regs *regs, int toreg, int flop)
	137	{
	138	unsigned long saddr = regs->ior;
e8aa7b17	139	unsigned long val = 0, temp1, temp2;
d1434e03	140	ASM_EXCEPTIONTABLE_VAR(ret);
1da177e4 LT	141
	142	DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n",
	143	regs->isr, regs->ior, toreg);
	144
	145	__asm__ __volatile__ (
e8aa7b17 HD	146	" zdep %4,28,2,%2\n" /* r19=(ofs&3)8 /
	147	" mtsp %5, %%sr1\n"
	148	" depw %%r0,31,2,%4\n"
	149	"1: ldw 0(%%sr1,%4),%0\n"
	150	"2: ldw 4(%%sr1,%4),%3\n"
96b80fcd	151	" subi 32,%2,%2\n"
e8aa7b17 HD	152	" mtctl %2,11\n"
e8aa7b17 HD	153	" vshd %0,%3,%0\n"
1da177e4	154	"3: \n"
8b1d7239 HD	155	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
8b1d7239 HD	156	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
e8aa7b17 HD	157	: "+r" (val), "+r" (ret), "=&r" (temp1), "=&r" (temp2)
e8aa7b17 HD	158	: "r" (saddr), "r" (regs->isr) );
1da177e4	159
e5e9e7f2	160	DPRINTF("val = " RFMT "\n", val);
1da177e4 LT	161
	162	if (flop)
	163	((__u32*)(regs->fr))[toreg] = val;
	164	else if (toreg)
	165	regs->gr[toreg] = val;
	166
	167	return ret;
	168	}
	169	static int emulate_ldd(struct pt_regs *regs, int toreg, int flop)
	170	{
	171	unsigned long saddr = regs->ior;
	172	__u64 val = 0;
d1434e03	173	ASM_EXCEPTIONTABLE_VAR(ret);
1da177e4 LT	174
	175	DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n",
	176	regs->isr, regs->ior, toreg);
1da177e4	177
d1434e03 HD	178	if (!IS_ENABLED(CONFIG_64BIT) && !flop)
	179	return ERR_NOTHANDLED;
	180
	181	#ifdef CONFIG_64BIT
1da177e4 LT	182	__asm__ __volatile__ (
	183	" depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)8 /
	184	" mtsp %4, %%sr1\n"
	185	" depd %%r0,63,3,%3\n"
	186	"1: ldd 0(%%sr1,%3),%0\n"
	187	"2: ldd 8(%%sr1,%3),%%r20\n"
	188	" subi 64,%%r19,%%r19\n"
	189	" mtsar %%r19\n"
	190	" shrpd %0,%%r20,%%sar,%0\n"
1da177e4	191	"3: \n"
8b1d7239 HD	192	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1")
8b1d7239 HD	193	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1")
d1434e03	194	: "=r" (val), "+r" (ret)
1da177e4	195	: "0" (val), "r" (saddr), "r" (regs->isr)
d1434e03	196	: "r19", "r20" );
1da177e4 LT	197	#else
1da177e4 LT	198	{
427c1073	199	unsigned long shift, temp1;
1da177e4	200	__asm__ __volatile__ (
427c1073 HD	201	" zdep %2,29,2,%3\n" /* r19=(ofs&3)8 /
	202	" mtsp %5, %%sr1\n"
	203	" dep %%r0,31,2,%2\n"
	204	"1: ldw 0(%%sr1,%2),%0\n"
	205	"2: ldw 4(%%sr1,%2),%R0\n"
	206	"3: ldw 8(%%sr1,%2),%4\n"
	207	" subi 32,%3,%3\n"
	208	" mtsar %3\n"
	209	" vshd %0,%R0,%0\n"
	210	" vshd %R0,%4,%R0\n"
1da177e4	211	"4: \n"
8b1d7239 HD	212	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 4b, "%1")
	213	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 4b, "%1")
	214	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1")
427c1073 HD	215	: "+r" (val), "+r" (ret), "+r" (saddr), "=&r" (shift), "=&r" (temp1)
427c1073 HD	216	: "r" (regs->isr) );
1da177e4 LT	217	}
	218	#endif
	219
	220	DPRINTF("val = 0x%llx\n", val);
	221
	222	if (flop)
	223	regs->fr[toreg] = val;
	224	else if (toreg)
	225	regs->gr[toreg] = val;
	226
	227	return ret;
	228	}
	229
	230	static int emulate_sth(struct pt_regs *regs, int frreg)
	231	{
3029ce31	232	unsigned long val = regs->gr[frreg], temp1;
d1434e03	233	ASM_EXCEPTIONTABLE_VAR(ret);
1da177e4 LT	234
	235	if (!frreg)
	236	val = 0;
	237
e5e9e7f2	238	DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg,
1da177e4 LT	239	val, regs->isr, regs->ior);
	240
	241	__asm__ __volatile__ (
3029ce31 HD	242	" mtsp %4, %%sr1\n"
	243	" extrw,u %2, 23, 8, %1\n"
	244	"1: stb %1, 0(%%sr1, %3)\n"
	245	"2: stb %2, 1(%%sr1, %3)\n"
1da177e4	246	"3: \n"
8b1d7239 HD	247	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
8b1d7239 HD	248	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
3029ce31 HD	249	: "+r" (ret), "=&r" (temp1)
3029ce31 HD	250	: "r" (val), "r" (regs->ior), "r" (regs->isr) );
1da177e4 LT	251
	252	return ret;
	253	}
	254
	255	static int emulate_stw(struct pt_regs *regs, int frreg, int flop)
	256	{
	257	unsigned long val;
d1434e03	258	ASM_EXCEPTIONTABLE_VAR(ret);
1da177e4 LT	259
	260	if (flop)
	261	val = ((__u32*)(regs->fr))[frreg];
	262	else if (frreg)
	263	val = regs->gr[frreg];
	264	else
	265	val = 0;
	266
e5e9e7f2	267	DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg,
1da177e4 LT	268	val, regs->isr, regs->ior);
	269
	270
	271	__asm__ __volatile__ (
	272	" mtsp %3, %%sr1\n"
	273	" zdep %2, 28, 2, %%r19\n"
	274	" dep %%r0, 31, 2, %2\n"
	275	" mtsar %%r19\n"
	276	" depwi,z -2, %%sar, 32, %%r19\n"
	277	"1: ldw 0(%%sr1,%2),%%r20\n"
	278	"2: ldw 4(%%sr1,%2),%%r21\n"
	279	" vshd %%r0, %1, %%r22\n"
	280	" vshd %1, %%r0, %%r1\n"
	281	" and %%r20, %%r19, %%r20\n"
	282	" andcm %%r21, %%r19, %%r21\n"
	283	" or %%r22, %%r20, %%r20\n"
	284	" or %%r1, %%r21, %%r21\n"
	285	" stw %%r20,0(%%sr1,%2)\n"
	286	" stw %%r21,4(%%sr1,%2)\n"
1da177e4	287	"3: \n"
8b1d7239 HD	288	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0")
8b1d7239 HD	289	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0")
d1434e03	290	: "+r" (ret)
1da177e4	291	: "r" (val), "r" (regs->ior), "r" (regs->isr)
d1434e03	292	: "r19", "r20", "r21", "r22", "r1" );
1da177e4	293
a9727983	294	return ret;
1da177e4 LT	295	}
	296	static int emulate_std(struct pt_regs *regs, int frreg, int flop)
	297	{
	298	__u64 val;
d1434e03	299	ASM_EXCEPTIONTABLE_VAR(ret);
1da177e4 LT	300
	301	if (flop)
	302	val = regs->fr[frreg];
	303	else if (frreg)
	304	val = regs->gr[frreg];
	305	else
	306	val = 0;
	307
	308	DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg,
	309	val, regs->isr, regs->ior);
	310
d1434e03 HD	311	if (!IS_ENABLED(CONFIG_64BIT) && !flop)
	312	return ERR_NOTHANDLED;
	313
	314	#ifdef CONFIG_64BIT
1da177e4 LT	315	__asm__ __volatile__ (
	316	" mtsp %3, %%sr1\n"
	317	" depd,z %2, 60, 3, %%r19\n"
	318	" depd %%r0, 63, 3, %2\n"
	319	" mtsar %%r19\n"
	320	" depdi,z -2, %%sar, 64, %%r19\n"
	321	"1: ldd 0(%%sr1,%2),%%r20\n"
	322	"2: ldd 8(%%sr1,%2),%%r21\n"
	323	" shrpd %%r0, %1, %%sar, %%r22\n"
	324	" shrpd %1, %%r0, %%sar, %%r1\n"
	325	" and %%r20, %%r19, %%r20\n"
	326	" andcm %%r21, %%r19, %%r21\n"
	327	" or %%r22, %%r20, %%r20\n"
	328	" or %%r1, %%r21, %%r21\n"
	329	"3: std %%r20,0(%%sr1,%2)\n"
	330	"4: std %%r21,8(%%sr1,%2)\n"
1da177e4	331	"5: \n"
8b1d7239 HD	332	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 5b, "%0")
	333	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 5b, "%0")
	334	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0")
	335	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 5b, "%0")
d1434e03	336	: "+r" (ret)
1da177e4	337	: "r" (val), "r" (regs->ior), "r" (regs->isr)
d1434e03	338	: "r19", "r20", "r21", "r22", "r1" );
1da177e4 LT	339	#else
1da177e4 LT	340	{
1da177e4	341	__asm__ __volatile__ (
98a9d5f0 HD	342	" mtsp %3, %%sr1\n"
	343	" zdep %R1, 29, 2, %%r19\n"
	344	" dep %%r0, 31, 2, %2\n"
1da177e4 LT	345	" mtsar %%r19\n"
1da177e4 LT	346	" zvdepi -2, 32, %%r19\n"
98a9d5f0 HD	347	"1: ldw 0(%%sr1,%2),%%r20\n"
	348	"2: ldw 8(%%sr1,%2),%%r21\n"
	349	" vshd %1, %R1, %%r1\n"
1da177e4	350	" vshd %%r0, %1, %1\n"
98a9d5f0	351	" vshd %R1, %%r0, %R1\n"
1da177e4 LT	352	" and %%r20, %%r19, %%r20\n"
	353	" andcm %%r21, %%r19, %%r21\n"
	354	" or %1, %%r20, %1\n"
98a9d5f0 HD	355	" or %R1, %%r21, %R1\n"
	356	"3: stw %1,0(%%sr1,%2)\n"
	357	"4: stw %%r1,4(%%sr1,%2)\n"
	358	"5: stw %R1,8(%%sr1,%2)\n"
1da177e4	359	"6: \n"
8b1d7239 HD	360	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 6b, "%0")
	361	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 6b, "%0")
	362	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0")
	363	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(4b, 6b, "%0")
	364	ASM_EXCEPTIONTABLE_ENTRY_EFAULT(5b, 6b, "%0")
d1434e03	365	: "+r" (ret)
98a9d5f0	366	: "r" (val), "r" (regs->ior), "r" (regs->isr)
d1434e03	367	: "r19", "r20", "r21", "r1" );
1da177e4 LT	368	}
	369	#endif
	370
	371	return ret;
	372	}
	373
	374	void handle_unaligned(struct pt_regs *regs)
	375	{
6ee77658	376	static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
1da177e4 LT	377	unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;
	378	int modify = 0;
	379	int ret = ERR_NOTHANDLED;
1da177e4	380
d0c3be80 HD	381	__inc_irq_stat(irq_unaligned_count);
d0c3be80 HD	382
1da177e4	383	/* log a message with pacing */
f053725b KM	384	if (user_mode(regs)) {
	385	if (current->thread.flags & PARISC_UAC_SIGBUS) {
	386	goto force_sigbus;
	387	}
	388
6ee77658 AM	389	if (!(current->thread.flags & PARISC_UAC_NOPRINT) &&
6ee77658 AM	390	__ratelimit(&ratelimit)) {
e5e9e7f2 HD	391	printk(KERN_WARNING "%s(%d): unaligned access to " RFMT
	392	" at ip " RFMT " (iir " RFMT ")\n",
	393	current->comm, task_pid_nr(current), regs->ior,
	394	regs->iaoq[0], regs->iir);
1da177e4 LT	395	#ifdef DEBUG_UNALIGNED
	396	show_regs(regs);
	397	#endif
	398	}
f053725b	399
1da177e4 LT	400	if (!unaligned_enabled)
	401	goto force_sigbus;
	402	}
	403
	404	/* handle modification - OK, it's ugly, see the instruction manual */
	405	switch (MAJOR_OP(regs->iir))
	406	{
	407	case 0x03:
	408	case 0x09:
	409	case 0x0b:
	410	if (regs->iir&0x20)
	411	{
	412	modify = 1;
	413	if (regs->iir&0x1000) /* short loads */
	414	if (regs->iir&0x200)
	415	newbase += IM5_3(regs->iir);
	416	else
	417	newbase += IM5_2(regs->iir);
	418	else if (regs->iir&0x2000) /* scaled indexed */
	419	{
	420	int shift=0;
	421	switch (regs->iir & OPCODE1_MASK)
	422	{
	423	case OPCODE_LDH_I:
	424	shift= 1; break;
	425	case OPCODE_LDW_I:
	426	shift= 2; break;
	427	case OPCODE_LDD_I:
	428	case OPCODE_LDDA_I:
	429	shift= 3; break;
	430	}
	431	newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;
	432	} else /* simple indexed */
	433	newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);
	434	}
	435	break;
	436	case 0x13:
	437	case 0x1b:
	438	modify = 1;
	439	newbase += IM14(regs->iir);
	440	break;
	441	case 0x14:
	442	case 0x1c:
	443	if (regs->iir&8)
	444	{
	445	modify = 1;
	446	newbase += IM14(regs->iir&~0xe);
	447	}
	448	break;
	449	case 0x16:
	450	case 0x1e:
	451	modify = 1;
	452	newbase += IM14(regs->iir&6);
	453	break;
	454	case 0x17:
	455	case 0x1f:
	456	if (regs->iir&4)
	457	{
	458	modify = 1;
	459	newbase += IM14(regs->iir&~4);
	460	}
	461	break;
	462	}
	463
464	/* TODO: make this cleaner... */
465	switch (regs->iir & OPCODE1_MASK)
466	{
467	case OPCODE_LDH_I:
468	case OPCODE_LDH_S:
469	ret = emulate_ldh(regs, R3(regs->iir));
470	break;
471
472	case OPCODE_LDW_I:
473	case OPCODE_LDWA_I:
474	case OPCODE_LDW_S:
475	case OPCODE_LDWA_S:
99b2f159	476	ret = emulate_ldw(regs, R3(regs->iir), 0);
1da177e4 LT	477	break;
	478
	479	case OPCODE_STH:
	480	ret = emulate_sth(regs, R2(regs->iir));
	481	break;
	482
	483	case OPCODE_STW:
	484	case OPCODE_STWA:
99b2f159	485	ret = emulate_stw(regs, R2(regs->iir), 0);
1da177e4 LT	486	break;
1da177e4 LT	487
d1434e03	488	#ifdef CONFIG_64BIT
1da177e4 LT	489	case OPCODE_LDD_I:
	490	case OPCODE_LDDA_I:
	491	case OPCODE_LDD_S:
	492	case OPCODE_LDDA_S:
99b2f159	493	ret = emulate_ldd(regs, R3(regs->iir), 0);
1da177e4 LT	494	break;
	495
	496	case OPCODE_STD:
	497	case OPCODE_STDA:
99b2f159	498	ret = emulate_std(regs, R2(regs->iir), 0);
1da177e4 LT	499	break;
	500	#endif
	501
	502	case OPCODE_FLDWX:
	503	case OPCODE_FLDWS:
	504	case OPCODE_FLDWXR:
	505	case OPCODE_FLDWSR:
99b2f159	506	ret = emulate_ldw(regs, FR3(regs->iir), 1);
1da177e4 LT	507	break;
	508
	509	case OPCODE_FLDDX:
	510	case OPCODE_FLDDS:
99b2f159	511	ret = emulate_ldd(regs, R3(regs->iir), 1);
1da177e4 LT	512	break;
	513
	514	case OPCODE_FSTWX:
	515	case OPCODE_FSTWS:
	516	case OPCODE_FSTWXR:
	517	case OPCODE_FSTWSR:
99b2f159	518	ret = emulate_stw(regs, FR3(regs->iir), 1);
1da177e4 LT	519	break;
	520
	521	case OPCODE_FSTDX:
	522	case OPCODE_FSTDS:
99b2f159	523	ret = emulate_std(regs, R3(regs->iir), 1);
1da177e4 LT	524	break;
	525
	526	case OPCODE_LDCD_I:
	527	case OPCODE_LDCW_I:
	528	case OPCODE_LDCD_S:
	529	case OPCODE_LDCW_S:
	530	ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */
	531	break;
	532	}
1da177e4 LT	533	switch (regs->iir & OPCODE2_MASK)
	534	{
	535	case OPCODE_FLDD_L:
1da177e4 LT	536	ret = emulate_ldd(regs,R2(regs->iir),1);
	537	break;
	538	case OPCODE_FSTD_L:
1da177e4 LT	539	ret = emulate_std(regs, R2(regs->iir),1);
1da177e4 LT	540	break;
d1434e03	541	#ifdef CONFIG_64BIT
1da177e4 LT	542	case OPCODE_LDD_L:
	543	ret = emulate_ldd(regs, R2(regs->iir),0);
	544	break;
	545	case OPCODE_STD_L:
	546	ret = emulate_std(regs, R2(regs->iir),0);
	547	break;
1da177e4	548	#endif
dd2288f4	549	}
1da177e4 LT	550	switch (regs->iir & OPCODE3_MASK)
	551	{
	552	case OPCODE_FLDW_L:
a9727983	553	ret = emulate_ldw(regs, R2(regs->iir), 1);
1da177e4 LT	554	break;
1da177e4 LT	555	case OPCODE_LDW_M:
a9727983	556	ret = emulate_ldw(regs, R2(regs->iir), 0);
1da177e4 LT	557	break;
	558
	559	case OPCODE_FSTW_L:
1da177e4 LT	560	ret = emulate_stw(regs, R2(regs->iir),1);
	561	break;
	562	case OPCODE_STW_M:
	563	ret = emulate_stw(regs, R2(regs->iir),0);
	564	break;
	565	}
	566	switch (regs->iir & OPCODE4_MASK)
	567	{
	568	case OPCODE_LDH_L:
	569	ret = emulate_ldh(regs, R2(regs->iir));
	570	break;
	571	case OPCODE_LDW_L:
	572	case OPCODE_LDWM:
	573	ret = emulate_ldw(regs, R2(regs->iir),0);
	574	break;
	575	case OPCODE_STH_L:
	576	ret = emulate_sth(regs, R2(regs->iir));
	577	break;
	578	case OPCODE_STW_L:
	579	case OPCODE_STWM:
	580	ret = emulate_stw(regs, R2(regs->iir),0);
	581	break;
	582	}
	583
8b78f260	584	if (ret == 0 && modify && R1(regs->iir))
1da177e4 LT	585	regs->gr[R1(regs->iir)] = newbase;
	586
	587
	588	if (ret == ERR_NOTHANDLED)
	589	printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);
	590
	591	DPRINTF("ret = %d\n", ret);
	592
	593	if (ret)
	594	{
8b78f260 HD	595	/*
	596	* The unaligned handler failed.
	597	* If we were called by __get_user() or __put_user() jump
	598	* to it's exception fixup handler instead of crashing.
	599	*/
	600	if (!user_mode(regs) && fixup_exception(regs))
	601	return;
	602
1da177e4 LT	603	printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret);
	604	die_if_kernel("Unaligned data reference", regs, 28);
	605
d1434e03	606	if (ret == -EFAULT)
1da177e4	607	{
ccf75290	608	force_sig_fault(SIGSEGV, SEGV_MAPERR,
2e1661d2	609	(void __user *)regs->ior);
1da177e4 LT	610	}
	611	else
	612	{
	613	force_sigbus:
	614	/* couldn't handle it ... */
ccf75290	615	force_sig_fault(SIGBUS, BUS_ADRALN,
2e1661d2	616	(void __user *)regs->ior);
1da177e4 LT	617	}
	618
	619	return;
	620	}
	621
	622	/* else we handled it, let life go on. */
	623	regs->gr[0]\|=PSW_N;
	624	}
	625
	626	/*
	627	* NB: check_unaligned() is only used for PCXS processors right
	628	* now, so we only check for PA1.1 encodings at this point.
	629	*/
	630
	631	int
	632	check_unaligned(struct pt_regs *regs)
	633	{
	634	unsigned long align_mask;
	635
	636	/* Get alignment mask */
	637
	638	align_mask = 0UL;
	639	switch (regs->iir & OPCODE1_MASK) {
	640
	641	case OPCODE_LDH_I:
	642	case OPCODE_LDH_S:
	643	case OPCODE_STH:
	644	align_mask = 1UL;
	645	break;
	646
	647	case OPCODE_LDW_I:
	648	case OPCODE_LDWA_I:
	649	case OPCODE_LDW_S:
	650	case OPCODE_LDWA_S:
	651	case OPCODE_STW:
	652	case OPCODE_STWA:
	653	align_mask = 3UL;
	654	break;
	655
	656	default:
	657	switch (regs->iir & OPCODE4_MASK) {
	658	case OPCODE_LDH_L:
	659	case OPCODE_STH_L:
	660	align_mask = 1UL;
	661	break;
	662	case OPCODE_LDW_L:
	663	case OPCODE_LDWM:
	664	case OPCODE_STW_L:
	665	case OPCODE_STWM:
	666	align_mask = 3UL;
	667	break;
	668	}
	669	break;
	670	}
	671
	672	return (int)(regs->ior & align_mask);
	673	}
	674