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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * linux/arch/parisc/kernel/time.c | |
4 | * | |
5 | * Copyright (C) 1991, 1992, 1995 Linus Torvalds | |
6 | * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King | |
7 | * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org) | |
8 | * | |
9 | * 1994-07-02 Alan Modra | |
10 | * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime | |
11 | * 1998-12-20 Updated NTP code according to technical memorandum Jan '96 | |
12 | * "A Kernel Model for Precision Timekeeping" by Dave Mills | |
13 | */ | |
1da177e4 LT |
14 | #include <linux/errno.h> |
15 | #include <linux/module.h> | |
ca6da801 | 16 | #include <linux/rtc.h> |
1da177e4 | 17 | #include <linux/sched.h> |
e6017571 | 18 | #include <linux/sched/clock.h> |
43b1f6ab | 19 | #include <linux/sched_clock.h> |
1da177e4 LT |
20 | #include <linux/kernel.h> |
21 | #include <linux/param.h> | |
22 | #include <linux/string.h> | |
23 | #include <linux/mm.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/time.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/smp.h> | |
28 | #include <linux/profile.h> | |
12df29b6 | 29 | #include <linux/clocksource.h> |
9eb16864 | 30 | #include <linux/platform_device.h> |
d75f054a | 31 | #include <linux/ftrace.h> |
1da177e4 | 32 | |
7c0f6ba6 | 33 | #include <linux/uaccess.h> |
1da177e4 LT |
34 | #include <asm/io.h> |
35 | #include <asm/irq.h> | |
4a8a0788 | 36 | #include <asm/page.h> |
1da177e4 LT |
37 | #include <asm/param.h> |
38 | #include <asm/pdc.h> | |
39 | #include <asm/led.h> | |
40 | ||
41 | #include <linux/timex.h> | |
42 | ||
bed583f7 | 43 | static unsigned long clocktick __read_mostly; /* timer cycles per tick */ |
1da177e4 | 44 | |
1604f318 MW |
45 | /* |
46 | * We keep time on PA-RISC Linux by using the Interval Timer which is | |
47 | * a pair of registers; one is read-only and one is write-only; both | |
48 | * accessed through CR16. The read-only register is 32 or 64 bits wide, | |
49 | * and increments by 1 every CPU clock tick. The architecture only | |
50 | * guarantees us a rate between 0.5 and 2, but all implementations use a | |
51 | * rate of 1. The write-only register is 32-bits wide. When the lowest | |
52 | * 32 bits of the read-only register compare equal to the write-only | |
53 | * register, it raises a maskable external interrupt. Each processor has | |
54 | * an Interval Timer of its own and they are not synchronised. | |
55 | * | |
56 | * We want to generate an interrupt every 1/HZ seconds. So we program | |
57 | * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data | |
58 | * is programmed with the intended time of the next tick. We can be | |
59 | * held off for an arbitrarily long period of time by interrupts being | |
60 | * disabled, so we may miss one or more ticks. | |
61 | */ | |
d75f054a | 62 | irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id) |
1da177e4 | 63 | { |
160494d3 | 64 | unsigned long now; |
bed583f7 | 65 | unsigned long next_tick; |
160494d3 | 66 | unsigned long ticks_elapsed = 0; |
6e5dc42b | 67 | unsigned int cpu = smp_processor_id(); |
ef017beb | 68 | struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); |
1da177e4 | 69 | |
6b799d92 | 70 | /* gcc can optimize for "read-only" case with a local clocktick */ |
6e5dc42b | 71 | unsigned long cpt = clocktick; |
6b799d92 | 72 | |
be577a52 | 73 | profile_tick(CPU_PROFILING); |
1da177e4 | 74 | |
160494d3 | 75 | /* Initialize next_tick to the old expected tick time. */ |
c7753f18 | 76 | next_tick = cpuinfo->it_value; |
1da177e4 | 77 | |
160494d3 | 78 | /* Calculate how many ticks have elapsed. */ |
636a415b | 79 | now = mfctl(16); |
160494d3 HD |
80 | do { |
81 | ++ticks_elapsed; | |
82 | next_tick += cpt; | |
160494d3 | 83 | } while (next_tick - now > cpt); |
6e5dc42b | 84 | |
160494d3 | 85 | /* Store (in CR16 cycles) up to when we are accounting right now. */ |
c7753f18 | 86 | cpuinfo->it_value = next_tick; |
6b799d92 | 87 | |
160494d3 HD |
88 | /* Go do system house keeping. */ |
89 | if (cpu == 0) | |
90 | xtime_update(ticks_elapsed); | |
91 | ||
92 | update_process_times(user_mode(get_irq_regs())); | |
1da177e4 | 93 | |
160494d3 | 94 | /* Skip clockticks on purpose if we know we would miss those. |
84be31be GG |
95 | * The new CR16 must be "later" than current CR16 otherwise |
96 | * itimer would not fire until CR16 wrapped - e.g 4 seconds | |
97 | * later on a 1Ghz processor. We'll account for the missed | |
160494d3 HD |
98 | * ticks on the next timer interrupt. |
99 | * We want IT to fire modulo clocktick even if we miss/skip some. | |
100 | * But those interrupts don't in fact get delivered that regularly. | |
84be31be GG |
101 | * |
102 | * "next_tick - now" will always give the difference regardless | |
103 | * if one or the other wrapped. If "now" is "bigger" we'll end up | |
104 | * with a very large unsigned number. | |
105 | */ | |
636a415b HD |
106 | now = mfctl(16); |
107 | while (next_tick - now > cpt) | |
160494d3 | 108 | next_tick += cpt; |
84be31be | 109 | |
160494d3 HD |
110 | /* Program the IT when to deliver the next interrupt. |
111 | * Only bottom 32-bits of next_tick are writable in CR16! | |
112 | * Timer interrupt will be delivered at least a few hundred cycles | |
636a415b | 113 | * after the IT fires, so if we are too close (<= 8000 cycles) to the |
160494d3 | 114 | * next cycle, simply skip it. |
bed583f7 | 115 | */ |
636a415b | 116 | if (next_tick - now <= 8000) |
160494d3 HD |
117 | next_tick += cpt; |
118 | mtctl(next_tick, 16); | |
6e5dc42b | 119 | |
1da177e4 LT |
120 | return IRQ_HANDLED; |
121 | } | |
122 | ||
5cd55b0e RC |
123 | |
124 | unsigned long profile_pc(struct pt_regs *regs) | |
125 | { | |
126 | unsigned long pc = instruction_pointer(regs); | |
127 | ||
128 | if (regs->gr[0] & PSW_N) | |
129 | pc -= 4; | |
130 | ||
131 | #ifdef CONFIG_SMP | |
132 | if (in_lock_functions(pc)) | |
133 | pc = regs->gr[2]; | |
134 | #endif | |
135 | ||
136 | return pc; | |
137 | } | |
138 | EXPORT_SYMBOL(profile_pc); | |
139 | ||
140 | ||
12df29b6 | 141 | /* clock source code */ |
1da177e4 | 142 | |
a5a1d1c2 | 143 | static u64 notrace read_cr16(struct clocksource *cs) |
1da177e4 | 144 | { |
12df29b6 | 145 | return get_cycles(); |
1da177e4 | 146 | } |
bed583f7 | 147 | |
12df29b6 HD |
148 | static struct clocksource clocksource_cr16 = { |
149 | .name = "cr16", | |
150 | .rating = 300, | |
151 | .read = read_cr16, | |
152 | .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), | |
87c81747 | 153 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
12df29b6 | 154 | }; |
bed583f7 | 155 | |
56f335c8 GG |
156 | void __init start_cpu_itimer(void) |
157 | { | |
158 | unsigned int cpu = smp_processor_id(); | |
159 | unsigned long next_tick = mfctl(16) + clocktick; | |
160 | ||
161 | mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ | |
162 | ||
ef017beb | 163 | per_cpu(cpu_data, cpu).it_value = next_tick; |
56f335c8 GG |
164 | } |
165 | ||
ca6da801 AB |
166 | #if IS_ENABLED(CONFIG_RTC_DRV_GENERIC) |
167 | static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm) | |
168 | { | |
169 | struct pdc_tod tod_data; | |
170 | ||
171 | memset(tm, 0, sizeof(*tm)); | |
172 | if (pdc_tod_read(&tod_data) < 0) | |
173 | return -EOPNOTSUPP; | |
174 | ||
175 | /* we treat tod_sec as unsigned, so this can work until year 2106 */ | |
176 | rtc_time64_to_tm(tod_data.tod_sec, tm); | |
f6b1a3a4 | 177 | return 0; |
ca6da801 AB |
178 | } |
179 | ||
180 | static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm) | |
181 | { | |
182 | time64_t secs = rtc_tm_to_time64(tm); | |
183 | ||
184 | if (pdc_tod_set(secs, 0) < 0) | |
185 | return -EOPNOTSUPP; | |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
190 | static const struct rtc_class_ops rtc_generic_ops = { | |
191 | .read_time = rtc_generic_get_time, | |
192 | .set_time = rtc_generic_set_time, | |
193 | }; | |
194 | ||
9eb16864 KM |
195 | static int __init rtc_init(void) |
196 | { | |
6dc0dcde | 197 | struct platform_device *pdev; |
9eb16864 | 198 | |
ca6da801 AB |
199 | pdev = platform_device_register_data(NULL, "rtc-generic", -1, |
200 | &rtc_generic_ops, | |
201 | sizeof(rtc_generic_ops)); | |
202 | ||
6dc0dcde | 203 | return PTR_ERR_OR_ZERO(pdev); |
9eb16864 | 204 | } |
6dc0dcde | 205 | device_initcall(rtc_init); |
ca6da801 | 206 | #endif |
9eb16864 | 207 | |
f76cdd00 | 208 | void read_persistent_clock64(struct timespec64 *ts) |
1da177e4 | 209 | { |
1da177e4 | 210 | static struct pdc_tod tod_data; |
c6018524 | 211 | if (pdc_tod_read(&tod_data) == 0) { |
212 | ts->tv_sec = tod_data.tod_sec; | |
213 | ts->tv_nsec = tod_data.tod_usec * 1000; | |
214 | } else { | |
215 | printk(KERN_ERR "Error reading tod clock\n"); | |
216 | ts->tv_sec = 0; | |
217 | ts->tv_nsec = 0; | |
218 | } | |
219 | } | |
220 | ||
54b66800 | 221 | |
43b1f6ab | 222 | static u64 notrace read_cr16_sched_clock(void) |
54b66800 | 223 | { |
43b1f6ab | 224 | return get_cycles(); |
54b66800 HD |
225 | } |
226 | ||
227 | ||
228 | /* | |
229 | * timer interrupt and sched_clock() initialization | |
230 | */ | |
231 | ||
c6018524 | 232 | void __init time_init(void) |
233 | { | |
43b1f6ab | 234 | unsigned long cr16_hz; |
1da177e4 LT |
235 | |
236 | clocktick = (100 * PAGE0->mem_10msec) / HZ; | |
56f335c8 | 237 | start_cpu_itimer(); /* get CPU 0 started */ |
1da177e4 | 238 | |
43b1f6ab HD |
239 | cr16_hz = 100 * PAGE0->mem_10msec; /* Hz */ |
240 | ||
43b1f6ab HD |
241 | /* register as sched_clock source */ |
242 | sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz); | |
1da177e4 | 243 | } |
41744213 HD |
244 | |
245 | static int __init init_cr16_clocksource(void) | |
246 | { | |
247 | /* | |
c8c37359 HD |
248 | * The cr16 interval timers are not syncronized across CPUs on |
249 | * different sockets, so mark them unstable and lower rating on | |
250 | * multi-socket SMP systems. | |
41744213 | 251 | */ |
5ffa8518 | 252 | if (num_online_cpus() > 1 && !running_on_qemu) { |
c8c37359 HD |
253 | int cpu; |
254 | unsigned long cpu0_loc; | |
255 | cpu0_loc = per_cpu(cpu_data, 0).cpu_loc; | |
256 | ||
257 | for_each_online_cpu(cpu) { | |
8642b31b HD |
258 | if (cpu == 0) |
259 | continue; | |
260 | if ((cpu0_loc != 0) && | |
261 | (cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc)) | |
c8c37359 HD |
262 | continue; |
263 | ||
264 | clocksource_cr16.name = "cr16_unstable"; | |
265 | clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE; | |
266 | clocksource_cr16.rating = 0; | |
267 | break; | |
268 | } | |
41744213 HD |
269 | } |
270 | ||
c8c37359 HD |
271 | /* XXX: We may want to mark sched_clock stable here if cr16 clocks are |
272 | * in sync: | |
273 | * (clocksource_cr16.flags == CLOCK_SOURCE_IS_CONTINUOUS) */ | |
274 | ||
41744213 HD |
275 | /* register at clocksource framework */ |
276 | clocksource_register_hz(&clocksource_cr16, | |
277 | 100 * PAGE0->mem_10msec); | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | device_initcall(init_cr16_clocksource); |