parisc: Mark cr16 clocksource unstable on SMP systems
[linux-2.6-block.git] / arch / parisc / kernel / time.c
CommitLineData
1da177e4
LT
1/*
2 * linux/arch/parisc/kernel/time.c
3 *
4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
5 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
6 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org)
7 *
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96
11 * "A Kernel Model for Precision Timekeeping" by Dave Mills
12 */
1da177e4
LT
13#include <linux/errno.h>
14#include <linux/module.h>
ca6da801 15#include <linux/rtc.h>
1da177e4 16#include <linux/sched.h>
43b1f6ab 17#include <linux/sched_clock.h>
1da177e4
LT
18#include <linux/kernel.h>
19#include <linux/param.h>
20#include <linux/string.h>
21#include <linux/mm.h>
22#include <linux/interrupt.h>
23#include <linux/time.h>
24#include <linux/init.h>
25#include <linux/smp.h>
26#include <linux/profile.h>
12df29b6 27#include <linux/clocksource.h>
9eb16864 28#include <linux/platform_device.h>
d75f054a 29#include <linux/ftrace.h>
1da177e4 30
7c0f6ba6 31#include <linux/uaccess.h>
1da177e4
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32#include <asm/io.h>
33#include <asm/irq.h>
4a8a0788 34#include <asm/page.h>
1da177e4
LT
35#include <asm/param.h>
36#include <asm/pdc.h>
37#include <asm/led.h>
38
39#include <linux/timex.h>
40
bed583f7 41static unsigned long clocktick __read_mostly; /* timer cycles per tick */
1da177e4 42
1604f318
MW
43/*
44 * We keep time on PA-RISC Linux by using the Interval Timer which is
45 * a pair of registers; one is read-only and one is write-only; both
46 * accessed through CR16. The read-only register is 32 or 64 bits wide,
47 * and increments by 1 every CPU clock tick. The architecture only
48 * guarantees us a rate between 0.5 and 2, but all implementations use a
49 * rate of 1. The write-only register is 32-bits wide. When the lowest
50 * 32 bits of the read-only register compare equal to the write-only
51 * register, it raises a maskable external interrupt. Each processor has
52 * an Interval Timer of its own and they are not synchronised.
53 *
54 * We want to generate an interrupt every 1/HZ seconds. So we program
55 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data
56 * is programmed with the intended time of the next tick. We can be
57 * held off for an arbitrarily long period of time by interrupts being
58 * disabled, so we may miss one or more ticks.
59 */
d75f054a 60irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
1da177e4 61{
160494d3 62 unsigned long now;
bed583f7 63 unsigned long next_tick;
160494d3 64 unsigned long ticks_elapsed = 0;
6e5dc42b 65 unsigned int cpu = smp_processor_id();
ef017beb 66 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
1da177e4 67
6b799d92 68 /* gcc can optimize for "read-only" case with a local clocktick */
6e5dc42b 69 unsigned long cpt = clocktick;
6b799d92 70
be577a52 71 profile_tick(CPU_PROFILING);
1da177e4 72
160494d3 73 /* Initialize next_tick to the old expected tick time. */
c7753f18 74 next_tick = cpuinfo->it_value;
1da177e4 75
160494d3
HD
76 /* Calculate how many ticks have elapsed. */
77 do {
78 ++ticks_elapsed;
79 next_tick += cpt;
80 now = mfctl(16);
81 } while (next_tick - now > cpt);
6e5dc42b 82
160494d3 83 /* Store (in CR16 cycles) up to when we are accounting right now. */
c7753f18 84 cpuinfo->it_value = next_tick;
6b799d92 85
160494d3
HD
86 /* Go do system house keeping. */
87 if (cpu == 0)
88 xtime_update(ticks_elapsed);
89
90 update_process_times(user_mode(get_irq_regs()));
1da177e4 91
160494d3 92 /* Skip clockticks on purpose if we know we would miss those.
84be31be
GG
93 * The new CR16 must be "later" than current CR16 otherwise
94 * itimer would not fire until CR16 wrapped - e.g 4 seconds
95 * later on a 1Ghz processor. We'll account for the missed
160494d3
HD
96 * ticks on the next timer interrupt.
97 * We want IT to fire modulo clocktick even if we miss/skip some.
98 * But those interrupts don't in fact get delivered that regularly.
84be31be
GG
99 *
100 * "next_tick - now" will always give the difference regardless
101 * if one or the other wrapped. If "now" is "bigger" we'll end up
102 * with a very large unsigned number.
103 */
160494d3
HD
104 while (next_tick - mfctl(16) > cpt)
105 next_tick += cpt;
84be31be 106
160494d3
HD
107 /* Program the IT when to deliver the next interrupt.
108 * Only bottom 32-bits of next_tick are writable in CR16!
109 * Timer interrupt will be delivered at least a few hundred cycles
110 * after the IT fires, so if we are too close (<= 500 cycles) to the
111 * next cycle, simply skip it.
bed583f7 112 */
160494d3
HD
113 if (next_tick - mfctl(16) <= 500)
114 next_tick += cpt;
115 mtctl(next_tick, 16);
6e5dc42b 116
1da177e4
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117 return IRQ_HANDLED;
118}
119
5cd55b0e
RC
120
121unsigned long profile_pc(struct pt_regs *regs)
122{
123 unsigned long pc = instruction_pointer(regs);
124
125 if (regs->gr[0] & PSW_N)
126 pc -= 4;
127
128#ifdef CONFIG_SMP
129 if (in_lock_functions(pc))
130 pc = regs->gr[2];
131#endif
132
133 return pc;
134}
135EXPORT_SYMBOL(profile_pc);
136
137
12df29b6 138/* clock source code */
1da177e4 139
a5a1d1c2 140static u64 notrace read_cr16(struct clocksource *cs)
1da177e4 141{
12df29b6 142 return get_cycles();
1da177e4 143}
bed583f7 144
12df29b6
HD
145static struct clocksource clocksource_cr16 = {
146 .name = "cr16",
147 .rating = 300,
148 .read = read_cr16,
149 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
87c81747 150 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
12df29b6 151};
bed583f7 152
56f335c8
GG
153void __init start_cpu_itimer(void)
154{
155 unsigned int cpu = smp_processor_id();
156 unsigned long next_tick = mfctl(16) + clocktick;
157
158 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */
159
ef017beb 160 per_cpu(cpu_data, cpu).it_value = next_tick;
56f335c8
GG
161}
162
ca6da801
AB
163#if IS_ENABLED(CONFIG_RTC_DRV_GENERIC)
164static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm)
165{
166 struct pdc_tod tod_data;
167
168 memset(tm, 0, sizeof(*tm));
169 if (pdc_tod_read(&tod_data) < 0)
170 return -EOPNOTSUPP;
171
172 /* we treat tod_sec as unsigned, so this can work until year 2106 */
173 rtc_time64_to_tm(tod_data.tod_sec, tm);
174 return rtc_valid_tm(tm);
175}
176
177static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm)
178{
179 time64_t secs = rtc_tm_to_time64(tm);
180
181 if (pdc_tod_set(secs, 0) < 0)
182 return -EOPNOTSUPP;
183
184 return 0;
185}
186
187static const struct rtc_class_ops rtc_generic_ops = {
188 .read_time = rtc_generic_get_time,
189 .set_time = rtc_generic_set_time,
190};
191
9eb16864
KM
192static int __init rtc_init(void)
193{
6dc0dcde 194 struct platform_device *pdev;
9eb16864 195
ca6da801
AB
196 pdev = platform_device_register_data(NULL, "rtc-generic", -1,
197 &rtc_generic_ops,
198 sizeof(rtc_generic_ops));
199
6dc0dcde 200 return PTR_ERR_OR_ZERO(pdev);
9eb16864 201}
6dc0dcde 202device_initcall(rtc_init);
ca6da801 203#endif
9eb16864 204
c6018524 205void read_persistent_clock(struct timespec *ts)
1da177e4 206{
1da177e4 207 static struct pdc_tod tod_data;
c6018524 208 if (pdc_tod_read(&tod_data) == 0) {
209 ts->tv_sec = tod_data.tod_sec;
210 ts->tv_nsec = tod_data.tod_usec * 1000;
211 } else {
212 printk(KERN_ERR "Error reading tod clock\n");
213 ts->tv_sec = 0;
214 ts->tv_nsec = 0;
215 }
216}
217
54b66800 218
43b1f6ab 219static u64 notrace read_cr16_sched_clock(void)
54b66800 220{
43b1f6ab 221 return get_cycles();
54b66800
HD
222}
223
224
225/*
226 * timer interrupt and sched_clock() initialization
227 */
228
c6018524 229void __init time_init(void)
230{
43b1f6ab 231 unsigned long cr16_hz;
1da177e4
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232
233 clocktick = (100 * PAGE0->mem_10msec) / HZ;
56f335c8 234 start_cpu_itimer(); /* get CPU 0 started */
1da177e4 235
43b1f6ab
HD
236 cr16_hz = 100 * PAGE0->mem_10msec; /* Hz */
237
43b1f6ab
HD
238 /* register as sched_clock source */
239 sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz);
1da177e4 240}
41744213
HD
241
242static int __init init_cr16_clocksource(void)
243{
244 /*
245 * The cr16 interval timers are not syncronized across CPUs, so mark
246 * them unstable and lower rating on SMP systems.
247 */
248 if (num_online_cpus() > 1) {
249 clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
250 clocksource_cr16.rating = 0;
251 }
252
253 /* register at clocksource framework */
254 clocksource_register_hz(&clocksource_cr16,
255 100 * PAGE0->mem_10msec);
256
257 return 0;
258}
259
260device_initcall(init_cr16_clocksource);