[linux-2.6-block.git] / arch / parisc / kernel / cache.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
 * Copyright (C) 1999 SuSE GmbH Nuernberg
 * Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
 *
 * Cache and TLB management
 *
 */
 
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/seq_file.h>
#include <linux/pagemap.h>
#include <linux/sched.h>
#include <asm/pdc.h>
#include <asm/cache.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#include <asm/page.h>
#include <asm/pgalloc.h>
#include <asm/processor.h>
#include <asm/sections.h>
#include <asm/shmparam.h>

int split_tlb __read_mostly;
int dcache_stride __read_mostly;
int icache_stride __read_mostly;
EXPORT_SYMBOL(dcache_stride);

void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
EXPORT_SYMBOL(flush_dcache_page_asm);
void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);


/* On some machines (e.g. ones with the Merced bus), there can be
 * only a single PxTLB broadcast at a time; this must be guaranteed
 * by software.  We put a spinlock around all TLB flushes  to
 * ensure this.
 */
DEFINE_SPINLOCK(pa_tlb_lock);

struct pdc_cache_info cache_info __read_mostly;
#ifndef CONFIG_PA20
static struct pdc_btlb_info btlb_info __read_mostly;
#endif

#ifdef CONFIG_SMP
void
flush_data_cache(void)
{
	on_each_cpu(flush_data_cache_local, NULL, 1);
}
void 
flush_instruction_cache(void)
{
	on_each_cpu(flush_instruction_cache_local, NULL, 1);
}
#endif

void
flush_cache_all_local(void)
{
	flush_instruction_cache_local(NULL);
	flush_data_cache_local(NULL);
}
EXPORT_SYMBOL(flush_cache_all_local);

void
update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
{
	struct page *page = pte_page(*ptep);

	if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
	    test_bit(PG_dcache_dirty, &page->flags)) {

		flush_kernel_dcache_page(page);
		clear_bit(PG_dcache_dirty, &page->flags);
	} else if (parisc_requires_coherency())
		flush_kernel_dcache_page(page);
}

void
show_cache_info(struct seq_file *m)
{
	char buf[32];

	seq_printf(m, "I-cache\t\t: %ld KB\n", 
		cache_info.ic_size/1024 );
	if (cache_info.dc_loop != 1)
		snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
		cache_info.dc_size/1024,
		(cache_info.dc_conf.cc_wt ? "WT":"WB"),
		(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
		((cache_info.dc_loop == 1) ? "direct mapped" : buf));
	seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
		cache_info.it_size,
		cache_info.dt_size,
		cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
	);
		
#ifndef CONFIG_PA20
	/* BTLB - Block TLB */
	if (btlb_info.max_size==0) {
		seq_printf(m, "BTLB\t\t: not supported\n" );
	} else {
		seq_printf(m, 
		"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
		"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
		"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
		btlb_info.max_size, (int)4096,
		btlb_info.max_size>>8,
		btlb_info.fixed_range_info.num_i,
		btlb_info.fixed_range_info.num_d,
		btlb_info.fixed_range_info.num_comb, 
		btlb_info.variable_range_info.num_i,
		btlb_info.variable_range_info.num_d,
		btlb_info.variable_range_info.num_comb
		);
	}
#endif
}

void __init 
parisc_cache_init(void)
{
	if (pdc_cache_info(&cache_info) < 0)
		panic("parisc_cache_init: pdc_cache_info failed");

#if 0
	printk("ic_size %lx dc_size %lx it_size %lx\n",
		cache_info.ic_size,
		cache_info.dc_size,
		cache_info.it_size);

	printk("DC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
		cache_info.dc_base,
		cache_info.dc_stride,
		cache_info.dc_count,
		cache_info.dc_loop);

	printk("dc_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
		*(unsigned long *) (&cache_info.dc_conf),
		cache_info.dc_conf.cc_alias,
		cache_info.dc_conf.cc_block,
		cache_info.dc_conf.cc_line,
		cache_info.dc_conf.cc_shift);
	printk("	wt %d sh %d cst %d hv %d\n",
		cache_info.dc_conf.cc_wt,
		cache_info.dc_conf.cc_sh,
		cache_info.dc_conf.cc_cst,
		cache_info.dc_conf.cc_hv);

	printk("IC  base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
		cache_info.ic_base,
		cache_info.ic_stride,
		cache_info.ic_count,
		cache_info.ic_loop);

	printk("ic_conf = 0x%lx  alias %d blk %d line %d shift %d\n",
		*(unsigned long *) (&cache_info.ic_conf),
		cache_info.ic_conf.cc_alias,
		cache_info.ic_conf.cc_block,
		cache_info.ic_conf.cc_line,
		cache_info.ic_conf.cc_shift);
	printk("	wt %d sh %d cst %d hv %d\n",
		cache_info.ic_conf.cc_wt,
		cache_info.ic_conf.cc_sh,
		cache_info.ic_conf.cc_cst,
		cache_info.ic_conf.cc_hv);

	printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
		cache_info.dt_conf.tc_sh,
		cache_info.dt_conf.tc_page,
		cache_info.dt_conf.tc_cst,
		cache_info.dt_conf.tc_aid,
		cache_info.dt_conf.tc_pad1);

	printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
		cache_info.it_conf.tc_sh,
		cache_info.it_conf.tc_page,
		cache_info.it_conf.tc_cst,
		cache_info.it_conf.tc_aid,
		cache_info.it_conf.tc_pad1);
#endif

	split_tlb = 0;
	if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
		if (cache_info.dt_conf.tc_sh == 2)
			printk(KERN_WARNING "Unexpected TLB configuration. "
			"Will flush I/D separately (could be optimized).\n");

		split_tlb = 1;
	}

	/* "New and Improved" version from Jim Hull 
	 *	(1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
	 * The following CAFL_STRIDE is an optimized version, see
	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
	 */
#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
	dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
	icache_stride = CAFL_STRIDE(cache_info.ic_conf);
#undef CAFL_STRIDE

#ifndef CONFIG_PA20
	if (pdc_btlb_info(&btlb_info) < 0) {
		memset(&btlb_info, 0, sizeof btlb_info);
	}
#endif

	if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
						PDC_MODEL_NVA_UNSUPPORTED) {
		printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
#if 0
		panic("SMP kernel required to avoid non-equivalent aliasing");
#endif
	}
}

void disable_sr_hashing(void)
{
	int srhash_type, retval;
	unsigned long space_bits;

	switch (boot_cpu_data.cpu_type) {
	case pcx: /* We shouldn't get this far.  setup.c should prevent it. */
		BUG();
		return;

	case pcxs:
	case pcxt:
	case pcxt_:
		srhash_type = SRHASH_PCXST;
		break;

	case pcxl:
		srhash_type = SRHASH_PCXL;
		break;

	case pcxl2: /* pcxl2 doesn't support space register hashing */
		return;

	default: /* Currently all PA2.0 machines use the same ins. sequence */
		srhash_type = SRHASH_PA20;
		break;
	}

	disable_sr_hashing_asm(srhash_type);

	retval = pdc_spaceid_bits(&space_bits);
	/* If this procedure isn't implemented, don't panic. */
	if (retval < 0 && retval != PDC_BAD_OPTION)
		panic("pdc_spaceid_bits call failed.\n");
	if (space_bits != 0)
		panic("SpaceID hashing is still on!\n");
}

static inline void
__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
		   unsigned long physaddr)
{
	flush_dcache_page_asm(physaddr, vmaddr);
	if (vma->vm_flags & VM_EXEC)
		flush_icache_page_asm(physaddr, vmaddr);
}

void flush_dcache_page(struct page *page)
{
	struct address_space *mapping = page_mapping(page);
	struct vm_area_struct *mpnt;
	unsigned long offset;
	unsigned long addr, old_addr = 0;
	pgoff_t pgoff;

	if (mapping && !mapping_mapped(mapping)) {
		set_bit(PG_dcache_dirty, &page->flags);
		return;
	}

	flush_kernel_dcache_page(page);

	if (!mapping)
		return;

	pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);

	/* We have carefully arranged in arch_get_unmapped_area() that
	 * *any* mappings of a file are always congruently mapped (whether
	 * declared as MAP_PRIVATE or MAP_SHARED), so we only need
	 * to flush one address here for them all to become coherent */

	flush_dcache_mmap_lock(mapping);
	vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
		addr = mpnt->vm_start + offset;

		/* The TLB is the engine of coherence on parisc: The
		 * CPU is entitled to speculate any page with a TLB
		 * mapping, so here we kill the mapping then flush the
		 * page along a special flush only alias mapping.
		 * This guarantees that the page is no-longer in the
		 * cache for any process and nor may it be
		 * speculatively read in (until the user or kernel
		 * specifically accesses it, of course) */

		flush_tlb_page(mpnt, addr);
		if (old_addr == 0 || (old_addr & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
			__flush_cache_page(mpnt, addr, page_to_phys(page));
			if (old_addr)
				printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
			old_addr = addr;
		}
	}
	flush_dcache_mmap_unlock(mapping);
}
EXPORT_SYMBOL(flush_dcache_page);

/* Defined in arch/parisc/kernel/pacache.S */
EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
EXPORT_SYMBOL(flush_data_cache_local);
EXPORT_SYMBOL(flush_kernel_icache_range_asm);

void clear_user_page_asm(void *page, unsigned long vaddr)
{
	unsigned long flags;
	/* This function is implemented in assembly in pacache.S */
	extern void __clear_user_page_asm(void *page, unsigned long vaddr);

	purge_tlb_start(flags);
	__clear_user_page_asm(page, vaddr);
	purge_tlb_end(flags);
}

#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;

void __init parisc_setup_cache_timing(void)
{
	unsigned long rangetime, alltime;
	unsigned long size;

	alltime = mfctl(16);
	flush_data_cache();
	alltime = mfctl(16) - alltime;

	size = (unsigned long)(_end - _text);
	rangetime = mfctl(16);
	flush_kernel_dcache_range((unsigned long)_text, size);
	rangetime = mfctl(16) - rangetime;

	printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
		alltime, size, rangetime);

	/* Racy, but if we see an intermediate value, it's ok too... */
	parisc_cache_flush_threshold = size * alltime / rangetime;

	parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1); 
	if (!parisc_cache_flush_threshold)
		parisc_cache_flush_threshold = FLUSH_THRESHOLD;

	if (parisc_cache_flush_threshold > cache_info.dc_size)
		parisc_cache_flush_threshold = cache_info.dc_size;

	printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
}

extern void purge_kernel_dcache_page(unsigned long);
extern void clear_user_page_asm(void *page, unsigned long vaddr);

void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
{
	unsigned long flags;

	purge_kernel_dcache_page((unsigned long)page);
	purge_tlb_start(flags);
	pdtlb_kernel(page);
	purge_tlb_end(flags);
	clear_user_page_asm(page, vaddr);
}
EXPORT_SYMBOL(clear_user_page);

void flush_kernel_dcache_page_addr(void *addr)
{
	unsigned long flags;

	flush_kernel_dcache_page_asm(addr);
	purge_tlb_start(flags);
	pdtlb_kernel(addr);
	purge_tlb_end(flags);
}
EXPORT_SYMBOL(flush_kernel_dcache_page_addr);

void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
		    struct page *pg)
{
	/* no coherency needed (all in kmap/kunmap) */
	copy_user_page_asm(vto, vfrom);
	if (!parisc_requires_coherency())
		flush_kernel_dcache_page_asm(vto);
}
EXPORT_SYMBOL(copy_user_page);

#ifdef CONFIG_PA8X00

void kunmap_parisc(void *addr)
{
	if (parisc_requires_coherency())
		flush_kernel_dcache_page_addr(addr);
}
EXPORT_SYMBOL(kunmap_parisc);
#endif

void __flush_tlb_range(unsigned long sid, unsigned long start,
		       unsigned long end)
{
	unsigned long npages;

	npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	if (npages >= 512)  /* 2MB of space: arbitrary, should be tuned */
		flush_tlb_all();
	else {
		unsigned long flags;

		mtsp(sid, 1);
		purge_tlb_start(flags);
		if (split_tlb) {
			while (npages--) {
				pdtlb(start);
				pitlb(start);
				start += PAGE_SIZE;
			}
		} else {
			while (npages--) {
				pdtlb(start);
				start += PAGE_SIZE;
			}
		}
		purge_tlb_end(flags);
	}
}

static void cacheflush_h_tmp_function(void *dummy)
{
	flush_cache_all_local();
}

void flush_cache_all(void)
{
	on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
}

void flush_cache_mm(struct mm_struct *mm)
{
#ifdef CONFIG_SMP
	flush_cache_all();
#else
	flush_cache_all_local();
#endif
}

void
flush_user_dcache_range(unsigned long start, unsigned long end)
{
	if ((end - start) < parisc_cache_flush_threshold)
		flush_user_dcache_range_asm(start,end);
	else
		flush_data_cache();
}

void
flush_user_icache_range(unsigned long start, unsigned long end)
{
	if ((end - start) < parisc_cache_flush_threshold)
		flush_user_icache_range_asm(start,end);
	else
		flush_instruction_cache();
}


void flush_cache_range(struct vm_area_struct *vma,
		unsigned long start, unsigned long end)
{
	int sr3;

	BUG_ON(!vma->vm_mm->context);

	sr3 = mfsp(3);
	if (vma->vm_mm->context == sr3) {
		flush_user_dcache_range(start,end);
		flush_user_icache_range(start,end);
	} else {
		flush_cache_all();
	}
}

void
flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
{
	BUG_ON(!vma->vm_mm->context);

	flush_tlb_page(vma, vmaddr);
	__flush_cache_page(vma, vmaddr, page_to_phys(pfn_to_page(pfn)));

}
Commit	Line	Data
071327ec	1	/*
1da177e4 LT	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
67a5a59d	6	* Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
1da177e4 LT	7	* Copyright (C) 1999 SuSE GmbH Nuernberg
	8	* Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
	9	*
	10	* Cache and TLB management
	11	*
	12	*/
	13
	14	#include <linux/init.h>
	15	#include <linux/kernel.h>
	16	#include <linux/mm.h>
	17	#include <linux/module.h>
	18	#include <linux/seq_file.h>
	19	#include <linux/pagemap.h>
e8edc6e0	20	#include <linux/sched.h>
1da177e4 LT	21	#include <asm/pdc.h>
	22	#include <asm/cache.h>
	23	#include <asm/cacheflush.h>
	24	#include <asm/tlbflush.h>
1da177e4 LT	25	#include <asm/page.h>
	26	#include <asm/pgalloc.h>
	27	#include <asm/processor.h>
2464212f	28	#include <asm/sections.h>
f311847c	29	#include <asm/shmparam.h>
1da177e4	30
8039de10 HD	31	int split_tlb __read_mostly;
	32	int dcache_stride __read_mostly;
	33	int icache_stride __read_mostly;
1da177e4 LT	34	EXPORT_SYMBOL(dcache_stride);
1da177e4 LT	35
f311847c JB	36	void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
	37	EXPORT_SYMBOL(flush_dcache_page_asm);
	38	void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
	39
1da177e4	40
1da177e4 LT	41	/* On some machines (e.g. ones with the Merced bus), there can be
	42	* only a single PxTLB broadcast at a time; this must be guaranteed
	43	* by software. We put a spinlock around all TLB flushes to
	44	* ensure this.
	45	*/
	46	DEFINE_SPINLOCK(pa_tlb_lock);
1da177e4	47
8039de10	48	struct pdc_cache_info cache_info __read_mostly;
1da177e4	49	#ifndef CONFIG_PA20
8039de10	50	static struct pdc_btlb_info btlb_info __read_mostly;
1da177e4 LT	51	#endif
	52
	53	#ifdef CONFIG_SMP
	54	void
	55	flush_data_cache(void)
	56	{
15c8b6c1	57	on_each_cpu(flush_data_cache_local, NULL, 1);
1da177e4 LT	58	}
	59	void
	60	flush_instruction_cache(void)
	61	{
15c8b6c1	62	on_each_cpu(flush_instruction_cache_local, NULL, 1);
1da177e4 LT	63	}
	64	#endif
	65
	66	void
	67	flush_cache_all_local(void)
	68	{
1b2425e3 MW	69	flush_instruction_cache_local(NULL);
1b2425e3 MW	70	flush_data_cache_local(NULL);
1da177e4 LT	71	}
	72	EXPORT_SYMBOL(flush_cache_all_local);
	73
1da177e4	74	void
4b3073e1	75	update_mmu_cache(struct vm_area_struct vma, unsigned long address, pte_t ptep)
1da177e4	76	{
4b3073e1	77	struct page page = pte_page(ptep);
1da177e4 LT	78
	79	if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
	80	test_bit(PG_dcache_dirty, &page->flags)) {
	81
ba575833	82	flush_kernel_dcache_page(page);
1da177e4	83	clear_bit(PG_dcache_dirty, &page->flags);
20f4d3cb JB	84	} else if (parisc_requires_coherency())
20f4d3cb JB	85	flush_kernel_dcache_page(page);
1da177e4 LT	86	}
	87
	88	void
	89	show_cache_info(struct seq_file *m)
	90	{
e5a2e7fd KM	91	char buf[32];
e5a2e7fd KM	92
1da177e4 LT	93	seq_printf(m, "I-cache\t\t: %ld KB\n",
1da177e4 LT	94	cache_info.ic_size/1024 );
2f75c12c	95	if (cache_info.dc_loop != 1)
e5a2e7fd KM	96	snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);
e5a2e7fd KM	97	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s)\n",
1da177e4 LT	98	cache_info.dc_size/1024,
	99	(cache_info.dc_conf.cc_wt ? "WT":"WB"),
	100	(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
e5a2e7fd	101	((cache_info.dc_loop == 1) ? "direct mapped" : buf));
1da177e4 LT	102	seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
	103	cache_info.it_size,
	104	cache_info.dt_size,
	105	cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
	106	);
	107
	108	#ifndef CONFIG_PA20
	109	/* BTLB - Block TLB */
	110	if (btlb_info.max_size==0) {
	111	seq_printf(m, "BTLB\t\t: not supported\n" );
	112	} else {
	113	seq_printf(m,
	114	"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
	115	"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
	116	"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
	117	btlb_info.max_size, (int)4096,
	118	btlb_info.max_size>>8,
	119	btlb_info.fixed_range_info.num_i,
	120	btlb_info.fixed_range_info.num_d,
	121	btlb_info.fixed_range_info.num_comb,
	122	btlb_info.variable_range_info.num_i,
	123	btlb_info.variable_range_info.num_d,
	124	btlb_info.variable_range_info.num_comb
	125	);
	126	}
	127	#endif
	128	}
	129
	130	void __init
	131	parisc_cache_init(void)
	132	{
	133	if (pdc_cache_info(&cache_info) < 0)
	134	panic("parisc_cache_init: pdc_cache_info failed");
	135
	136	#if 0
	137	printk("ic_size %lx dc_size %lx it_size %lx\n",
	138	cache_info.ic_size,
	139	cache_info.dc_size,
	140	cache_info.it_size);
	141
	142	printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
	143	cache_info.dc_base,
	144	cache_info.dc_stride,
	145	cache_info.dc_count,
	146	cache_info.dc_loop);
	147
	148	printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
	149	(unsigned long ) (&cache_info.dc_conf),
	150	cache_info.dc_conf.cc_alias,
	151	cache_info.dc_conf.cc_block,
	152	cache_info.dc_conf.cc_line,
	153	cache_info.dc_conf.cc_shift);
e5a2e7fd	154	printk(" wt %d sh %d cst %d hv %d\n",
1da177e4 LT	155	cache_info.dc_conf.cc_wt,
	156	cache_info.dc_conf.cc_sh,
	157	cache_info.dc_conf.cc_cst,
e5a2e7fd	158	cache_info.dc_conf.cc_hv);
1da177e4 LT	159
	160	printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
	161	cache_info.ic_base,
	162	cache_info.ic_stride,
	163	cache_info.ic_count,
	164	cache_info.ic_loop);
	165
	166	printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
	167	(unsigned long ) (&cache_info.ic_conf),
	168	cache_info.ic_conf.cc_alias,
	169	cache_info.ic_conf.cc_block,
	170	cache_info.ic_conf.cc_line,
	171	cache_info.ic_conf.cc_shift);
e5a2e7fd	172	printk(" wt %d sh %d cst %d hv %d\n",
1da177e4 LT	173	cache_info.ic_conf.cc_wt,
	174	cache_info.ic_conf.cc_sh,
	175	cache_info.ic_conf.cc_cst,
e5a2e7fd	176	cache_info.ic_conf.cc_hv);
1da177e4	177
a3bee03e	178	printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
1da177e4 LT	179	cache_info.dt_conf.tc_sh,
	180	cache_info.dt_conf.tc_page,
	181	cache_info.dt_conf.tc_cst,
	182	cache_info.dt_conf.tc_aid,
	183	cache_info.dt_conf.tc_pad1);
	184
a3bee03e	185	printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d\n",
1da177e4 LT	186	cache_info.it_conf.tc_sh,
	187	cache_info.it_conf.tc_page,
	188	cache_info.it_conf.tc_cst,
	189	cache_info.it_conf.tc_aid,
	190	cache_info.it_conf.tc_pad1);
	191	#endif
	192
	193	split_tlb = 0;
	194	if (cache_info.dt_conf.tc_sh == 0 \|\| cache_info.dt_conf.tc_sh == 2) {
	195	if (cache_info.dt_conf.tc_sh == 2)
	196	printk(KERN_WARNING "Unexpected TLB configuration. "
	197	"Will flush I/D separately (could be optimized).\n");
	198
	199	split_tlb = 1;
	200	}
	201
	202	/* "New and Improved" version from Jim Hull
	203	* (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
2464212f SB	204	* The following CAFL_STRIDE is an optimized version, see
	205	* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
	206	* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
1da177e4 LT	207	*/
	208	#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
	209	dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
	210	icache_stride = CAFL_STRIDE(cache_info.ic_conf);
	211	#undef CAFL_STRIDE
	212
	213	#ifndef CONFIG_PA20
	214	if (pdc_btlb_info(&btlb_info) < 0) {
	215	memset(&btlb_info, 0, sizeof btlb_info);
	216	}
	217	#endif
	218
	219	if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
	220	PDC_MODEL_NVA_UNSUPPORTED) {
	221	printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
	222	#if 0
	223	panic("SMP kernel required to avoid non-equivalent aliasing");
	224	#endif
	225	}
	226	}
	227
	228	void disable_sr_hashing(void)
	229	{
a9d2d386 KM	230	int srhash_type, retval;
a9d2d386 KM	231	unsigned long space_bits;
1da177e4 LT	232
	233	switch (boot_cpu_data.cpu_type) {
	234	case pcx: /* We shouldn't get this far. setup.c should prevent it. */
	235	BUG();
	236	return;
	237
	238	case pcxs:
	239	case pcxt:
	240	case pcxt_:
	241	srhash_type = SRHASH_PCXST;
	242	break;
	243
	244	case pcxl:
	245	srhash_type = SRHASH_PCXL;
	246	break;
	247
	248	case pcxl2: /* pcxl2 doesn't support space register hashing */
	249	return;
	250
	251	default: /* Currently all PA2.0 machines use the same ins. sequence */
	252	srhash_type = SRHASH_PA20;
	253	break;
	254	}
	255
	256	disable_sr_hashing_asm(srhash_type);
a9d2d386 KM	257
	258	retval = pdc_spaceid_bits(&space_bits);
	259	/* If this procedure isn't implemented, don't panic. */
	260	if (retval < 0 && retval != PDC_BAD_OPTION)
	261	panic("pdc_spaceid_bits call failed.\n");
	262	if (space_bits != 0)
	263	panic("SpaceID hashing is still on!\n");
1da177e4 LT	264	}
1da177e4 LT	265
d6ce8626	266	static inline void
f311847c JB	267	__flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
f311847c JB	268	unsigned long physaddr)
d6ce8626	269	{
f311847c JB	270	flush_dcache_page_asm(physaddr, vmaddr);
	271	if (vma->vm_flags & VM_EXEC)
	272	flush_icache_page_asm(physaddr, vmaddr);
d6ce8626 RC	273	}
d6ce8626 RC	274
1da177e4 LT	275	void flush_dcache_page(struct page *page)
	276	{
	277	struct address_space *mapping = page_mapping(page);
	278	struct vm_area_struct *mpnt;
1da177e4	279	unsigned long offset;
f311847c	280	unsigned long addr, old_addr = 0;
1da177e4	281	pgoff_t pgoff;
1da177e4 LT	282
	283	if (mapping && !mapping_mapped(mapping)) {
	284	set_bit(PG_dcache_dirty, &page->flags);
	285	return;
	286	}
	287
ba575833	288	flush_kernel_dcache_page(page);
1da177e4 LT	289
	290	if (!mapping)
	291	return;
	292
	293	pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
	294
	295	/* We have carefully arranged in arch_get_unmapped_area() that
	296	* any mappings of a file are always congruently mapped (whether
	297	* declared as MAP_PRIVATE or MAP_SHARED), so we only need
	298	* to flush one address here for them all to become coherent */
	299
	300	flush_dcache_mmap_lock(mapping);
6b2dbba8	301	vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) {
1da177e4 LT	302	offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
	303	addr = mpnt->vm_start + offset;
	304
b7d45818 JB	305	/* The TLB is the engine of coherence on parisc: The
	306	* CPU is entitled to speculate any page with a TLB
	307	* mapping, so here we kill the mapping then flush the
	308	* page along a special flush only alias mapping.
	309	* This guarantees that the page is no-longer in the
	310	* cache for any process and nor may it be
	311	* speculatively read in (until the user or kernel
	312	* specifically accesses it, of course) */
	313
	314	flush_tlb_page(mpnt, addr);
f311847c JB	315	if (old_addr == 0 \|\| (old_addr & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {
	316	__flush_cache_page(mpnt, addr, page_to_phys(page));
	317	if (old_addr)
b7d45818	318	printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");
f311847c	319	old_addr = addr;
92dc6fcc	320	}
1da177e4 LT	321	}
	322	flush_dcache_mmap_unlock(mapping);
	323	}
	324	EXPORT_SYMBOL(flush_dcache_page);
	325
	326	/* Defined in arch/parisc/kernel/pacache.S */
	327	EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
ba575833	328	EXPORT_SYMBOL(flush_kernel_dcache_page_asm);
1da177e4 LT	329	EXPORT_SYMBOL(flush_data_cache_local);
	330	EXPORT_SYMBOL(flush_kernel_icache_range_asm);
	331
	332	void clear_user_page_asm(void *page, unsigned long vaddr)
	333	{
e82a3b75	334	unsigned long flags;
1da177e4 LT	335	/* This function is implemented in assembly in pacache.S */
	336	extern void __clear_user_page_asm(void *page, unsigned long vaddr);
	337
e82a3b75	338	purge_tlb_start(flags);
1da177e4	339	__clear_user_page_asm(page, vaddr);
e82a3b75	340	purge_tlb_end(flags);
1da177e4 LT	341	}
	342
	343	#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
8039de10	344	int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
1da177e4	345
d6ce8626	346	void __init parisc_setup_cache_timing(void)
1da177e4 LT	347	{
1da177e4 LT	348	unsigned long rangetime, alltime;
1da177e4 LT	349	unsigned long size;
	350
	351	alltime = mfctl(16);
	352	flush_data_cache();
	353	alltime = mfctl(16) - alltime;
	354
2464212f	355	size = (unsigned long)(_end - _text);
1da177e4	356	rangetime = mfctl(16);
2464212f	357	flush_kernel_dcache_range((unsigned long)_text, size);
1da177e4 LT	358	rangetime = mfctl(16) - rangetime;
	359
	360	printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
	361	alltime, size, rangetime);
	362
	363	/* Racy, but if we see an intermediate value, it's ok too... */
	364	parisc_cache_flush_threshold = size * alltime / rangetime;
	365
	366	parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
	367	if (!parisc_cache_flush_threshold)
	368	parisc_cache_flush_threshold = FLUSH_THRESHOLD;
	369
d6ce8626 RC	370	if (parisc_cache_flush_threshold > cache_info.dc_size)
	371	parisc_cache_flush_threshold = cache_info.dc_size;
	372
67a5a59d	373	printk(KERN_INFO "Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
1da177e4	374	}
20f4d3cb JB	375
	376	extern void purge_kernel_dcache_page(unsigned long);
	377	extern void clear_user_page_asm(void *page, unsigned long vaddr);
	378
8d0b7d10	379	void clear_user_page(void page, unsigned long vaddr, struct page pg)
20f4d3cb	380	{
e82a3b75 HD	381	unsigned long flags;
e82a3b75 HD	382
20f4d3cb	383	purge_kernel_dcache_page((unsigned long)page);
e82a3b75	384	purge_tlb_start(flags);
20f4d3cb	385	pdtlb_kernel(page);
e82a3b75	386	purge_tlb_end(flags);
20f4d3cb JB	387	clear_user_page_asm(page, vaddr);
20f4d3cb JB	388	}
8d0b7d10	389	EXPORT_SYMBOL(clear_user_page);
20f4d3cb JB	390
	391	void flush_kernel_dcache_page_addr(void *addr)
	392	{
e82a3b75 HD	393	unsigned long flags;
e82a3b75 HD	394
20f4d3cb	395	flush_kernel_dcache_page_asm(addr);
e82a3b75	396	purge_tlb_start(flags);
20f4d3cb	397	pdtlb_kernel(addr);
e82a3b75	398	purge_tlb_end(flags);
20f4d3cb JB	399	}
	400	EXPORT_SYMBOL(flush_kernel_dcache_page_addr);
	401
	402	void copy_user_page(void vto, void vfrom, unsigned long vaddr,
	403	struct page *pg)
	404	{
	405	/* no coherency needed (all in kmap/kunmap) */
	406	copy_user_page_asm(vto, vfrom);
	407	if (!parisc_requires_coherency())
	408	flush_kernel_dcache_page_asm(vto);
	409	}
	410	EXPORT_SYMBOL(copy_user_page);
	411
	412	#ifdef CONFIG_PA8X00
	413
	414	void kunmap_parisc(void *addr)
	415	{
	416	if (parisc_requires_coherency())
	417	flush_kernel_dcache_page_addr(addr);
	418	}
	419	EXPORT_SYMBOL(kunmap_parisc);
	420	#endif
d6ce8626 RC	421
	422	void __flush_tlb_range(unsigned long sid, unsigned long start,
	423	unsigned long end)
	424	{
	425	unsigned long npages;
	426
	427	npages = ((end - (start & PAGE_MASK)) + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
	428	if (npages >= 512) /* 2MB of space: arbitrary, should be tuned */
	429	flush_tlb_all();
	430	else {
e82a3b75 HD	431	unsigned long flags;
e82a3b75 HD	432
d6ce8626	433	mtsp(sid, 1);
e82a3b75	434	purge_tlb_start(flags);
d6ce8626 RC	435	if (split_tlb) {
	436	while (npages--) {
	437	pdtlb(start);
	438	pitlb(start);
	439	start += PAGE_SIZE;
	440	}
	441	} else {
	442	while (npages--) {
	443	pdtlb(start);
	444	start += PAGE_SIZE;
	445	}
	446	}
e82a3b75	447	purge_tlb_end(flags);
d6ce8626 RC	448	}
	449	}
	450
	451	static void cacheflush_h_tmp_function(void *dummy)
	452	{
	453	flush_cache_all_local();
	454	}
	455
	456	void flush_cache_all(void)
	457	{
15c8b6c1	458	on_each_cpu(cacheflush_h_tmp_function, NULL, 1);
d6ce8626 RC	459	}
	460
	461	void flush_cache_mm(struct mm_struct *mm)
	462	{
	463	#ifdef CONFIG_SMP
	464	flush_cache_all();
	465	#else
	466	flush_cache_all_local();
	467	#endif
	468	}
	469
	470	void
	471	flush_user_dcache_range(unsigned long start, unsigned long end)
	472	{
	473	if ((end - start) < parisc_cache_flush_threshold)
	474	flush_user_dcache_range_asm(start,end);
	475	else
	476	flush_data_cache();
	477	}
	478
	479	void
	480	flush_user_icache_range(unsigned long start, unsigned long end)
	481	{
	482	if ((end - start) < parisc_cache_flush_threshold)
	483	flush_user_icache_range_asm(start,end);
	484	else
	485	flush_instruction_cache();
	486	}
	487
	488
	489	void flush_cache_range(struct vm_area_struct *vma,
	490	unsigned long start, unsigned long end)
	491	{
	492	int sr3;
	493
8980a7ba	494	BUG_ON(!vma->vm_mm->context);
d6ce8626 RC	495
	496	sr3 = mfsp(3);
	497	if (vma->vm_mm->context == sr3) {
	498	flush_user_dcache_range(start,end);
	499	flush_user_icache_range(start,end);
	500	} else {
	501	flush_cache_all();
	502	}
	503	}
	504
	505	void
	506	flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
	507	{
	508	BUG_ON(!vma->vm_mm->context);
	509
b7d45818	510	flush_tlb_page(vma, vmaddr);
f311847c	511	__flush_cache_page(vma, vmaddr, page_to_phys(pfn_to_page(pfn)));
d6ce8626 RC	512
d6ce8626 RC	513	}