[linux-block.git] / arch / parisc / include / asm / pci.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_PARISC_PCI_H
#define __ASM_PARISC_PCI_H

#include <linux/scatterlist.h>


/*
** HP PCI platforms generally support multiple bus adapters.
**    (workstations 1-~4, servers 2-~32)
**
** Newer platforms number the busses across PCI bus adapters *sparsely*.
** E.g. 0, 8, 16, ...
**
** Under a PCI bus, most HP platforms support PPBs up to two or three
** levels deep. See "Bit3" product line. 
*/
#define PCI_MAX_BUSSES	256


/* To be used as: mdelay(pci_post_reset_delay);
 *
 * post_reset is the time the kernel should stall to prevent anyone from
 * accessing the PCI bus once #RESET is de-asserted. 
 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
 * this makes the boot time much longer than necessary.
 * 20ms seems to work for all the HP PCI implementations to date.
 */
#define pci_post_reset_delay 50


/*
** pci_hba_data (aka H2P_OBJECT in HP/UX)
**
** This is the "common" or "base" data structure which HBA drivers
** (eg Dino or LBA) are required to place at the top of their own
** platform_data structure.  I've heard this called "C inheritance" too.
**
** Data needed by pcibios layer belongs here.
*/
struct pci_hba_data {
	void __iomem   *base_addr;	/* aka Host Physical Address */
	const struct parisc_device *dev; /* device from PA bus walk */
	struct pci_bus *hba_bus;	/* primary PCI bus below HBA */
	int		hba_num;	/* I/O port space access "key" */
	struct resource bus_num;	/* PCI bus numbers */
	struct resource io_space;	/* PIOP */
	struct resource lmmio_space;	/* bus addresses < 4Gb */
	struct resource elmmio_space;	/* additional bus addresses < 4Gb */
	struct resource gmmio_space;	/* bus addresses > 4Gb */

	/* NOTE: Dino code assumes it can use *all* of the lmmio_space,
	 * elmmio_space and gmmio_space as a contiguous array of
	 * resources.  This #define represents the array size */
	#define DINO_MAX_LMMIO_RESOURCES	3

	unsigned long   lmmio_space_offset;  /* CPU view - PCI view */
	void *          iommu;          /* IOMMU this device is under */
	/* REVISIT - spinlock to protect resources? */

	#define HBA_NAME_SIZE 16
	char io_name[HBA_NAME_SIZE];
	char lmmio_name[HBA_NAME_SIZE];
	char elmmio_name[HBA_NAME_SIZE];
	char gmmio_name[HBA_NAME_SIZE];
};

#define HBA_DATA(d)		((struct pci_hba_data *) (d))

/* 
** We support 2^16 I/O ports per HBA.  These are set up in the form
** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
** space address.
*/
#define HBA_PORT_SPACE_BITS	16

#define HBA_PORT_BASE(h)	((h) << HBA_PORT_SPACE_BITS)
#define HBA_PORT_SPACE_SIZE	(1UL << HBA_PORT_SPACE_BITS)

#define PCI_PORT_HBA(a)		((a) >> HBA_PORT_SPACE_BITS)
#define PCI_PORT_ADDR(a)	((a) & (HBA_PORT_SPACE_SIZE - 1))

#ifdef CONFIG_64BIT
#define PCI_F_EXTEND		0xffffffff00000000UL
#else	/* !CONFIG_64BIT */
#define PCI_F_EXTEND		0UL
#endif /* !CONFIG_64BIT */

/*
** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
** (This eliminates some of the warnings).
*/
struct pci_bus;
struct pci_dev;

/*
 * If the PCI device's view of memory is the same as the CPU's view of memory,
 * PCI_DMA_BUS_IS_PHYS is true.  The networking and block device layers use
 * this boolean for bounce buffer decisions.
 */
#ifdef CONFIG_PA20
/* All PA-2.0 machines have an IOMMU. */
#define PCI_DMA_BUS_IS_PHYS	0
#define parisc_has_iommu()	do { } while (0)
#else

#if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA)
extern int parisc_bus_is_phys; 	/* in arch/parisc/kernel/setup.c */
#define PCI_DMA_BUS_IS_PHYS	parisc_bus_is_phys
#define parisc_has_iommu()	do { parisc_bus_is_phys = 0; } while (0)
#else
#define PCI_DMA_BUS_IS_PHYS	1
#define parisc_has_iommu()	do { } while (0)
#endif

#endif	/* !CONFIG_PA20 */


/*
** Most PCI devices (eg Tulip, NCR720) also export the same registers
** to both MMIO and I/O port space.  Due to poor performance of I/O Port
** access under HP PCI bus adapters, strongly recommend the use of MMIO
** address space.
**
** While I'm at it more PA programming notes:
**
** 1) MMIO stores (writes) are posted operations. This means the processor
**    gets an "ACK" before the write actually gets to the device. A read
**    to the same device (or typically the bus adapter above it) will
**    force in-flight write transaction(s) out to the targeted device
**    before the read can complete.
**
** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
**    respect to DMA on all platforms. Ie PIO data can reach the processor
**    before in-flight DMA reaches memory. Since most SMP PA platforms
**    are I/O coherent, it generally doesn't matter...but sometimes
**    it does.
**
** I've helped device driver writers debug both types of problems.
*/
struct pci_port_ops {
	  u8 (*inb)  (struct pci_hba_data *hba, u16 port);
	 u16 (*inw)  (struct pci_hba_data *hba, u16 port);
	 u32 (*inl)  (struct pci_hba_data *hba, u16 port);
	void (*outb) (struct pci_hba_data *hba, u16 port,  u8 data);
	void (*outw) (struct pci_hba_data *hba, u16 port, u16 data);
	void (*outl) (struct pci_hba_data *hba, u16 port, u32 data);
};


struct pci_bios_ops {
	void (*init)(void);
	void (*fixup_bus)(struct pci_bus *bus);
};

/*
** Stuff declared in arch/parisc/kernel/pci.c
*/
extern struct pci_port_ops *pci_port;
extern struct pci_bios_ops *pci_bios;

#ifdef CONFIG_PCI
extern void pcibios_register_hba(struct pci_hba_data *);
extern void pcibios_set_master(struct pci_dev *);
#else
static inline void pcibios_register_hba(struct pci_hba_data *x)
{
}
#endif
extern void pcibios_init_bridge(struct pci_dev *);

/*
 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
 *   0 == check if bridge is numbered before re-numbering.
 *   1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
 *
 *   We *should* set this to zero for "legacy" platforms and one
 *   for PAT platforms.
 *
 *   But legacy platforms also need to renumber the busses below a Host
 *   Bus controller.  Adding a 4-port Tulip card on the first PCI root
 *   bus of a C200 resulted in the secondary bus being numbered as 1.
 *   The second PCI host bus controller's root bus had already been
 *   assigned bus number 1 by firmware and sysfs complained.
 *
 *   Firmware isn't doing anything wrong here since each controller
 *   is its own PCI domain.  It's simpler and easier for us to renumber
 *   the busses rather than treat each Dino as a separate PCI domain.
 *   Eventually, we may want to introduce PCI domains for Superdome or
 *   rp7420/8420 boxes and then revisit this issue.
 */
#define pcibios_assign_all_busses()     (1)

#define PCIBIOS_MIN_IO          0x10
#define PCIBIOS_MIN_MEM         0x1000 /* NBPG - but pci/setup-res.c dies */

static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	return channel ? 15 : 14;
}

#define HAVE_PCI_MMAP
#define ARCH_GENERIC_PCI_MMAP_RESOURCE

#endif /* __ASM_PARISC_PCI_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	#ifndef __ASM_PARISC_PCI_H
	3	#define __ASM_PARISC_PCI_H
	4
84be456f	5	#include <linux/scatterlist.h>
1da177e4 LT	6
	7
	8
	9	/*
	10	** HP PCI platforms generally support multiple bus adapters.
	11	** (workstations 1-~4, servers 2-~32)
	12	**
	13	** Newer platforms number the busses across PCI bus adapters sparsely.
	14	** E.g. 0, 8, 16, ...
	15	**
	16	** Under a PCI bus, most HP platforms support PPBs up to two or three
	17	** levels deep. See "Bit3" product line.
	18	*/
	19	#define PCI_MAX_BUSSES 256
	20
cb6fc18e HD	21
	22	/* To be used as: mdelay(pci_post_reset_delay);
	23	*
	24	* post_reset is the time the kernel should stall to prevent anyone from
	25	* accessing the PCI bus once #RESET is de-asserted.
	26	* PCI spec somewhere says 1 second but with multi-PCI bus systems,
	27	* this makes the boot time much longer than necessary.
	28	* 20ms seems to work for all the HP PCI implementations to date.
	29	*/
	30	#define pci_post_reset_delay 50
	31
	32
1da177e4 LT	33	/*
	34	** pci_hba_data (aka H2P_OBJECT in HP/UX)
	35	**
	36	** This is the "common" or "base" data structure which HBA drivers
	37	** (eg Dino or LBA) are required to place at the top of their own
	38	** platform_data structure. I've heard this called "C inheritance" too.
	39	**
	40	** Data needed by pcibios layer belongs here.
	41	*/
	42	struct pci_hba_data {
	43	void __iomem base_addr; / aka Host Physical Address */
	44	const struct parisc_device dev; / device from PA bus walk */
	45	struct pci_bus hba_bus; / primary PCI bus below HBA */
	46	int hba_num; /* I/O port space access "key" */
	47	struct resource bus_num; /* PCI bus numbers */
	48	struct resource io_space; /* PIOP */
	49	struct resource lmmio_space; /* bus addresses < 4Gb */
	50	struct resource elmmio_space; /* additional bus addresses < 4Gb */
	51	struct resource gmmio_space; /* bus addresses > 4Gb */
	52
	53	/* NOTE: Dino code assumes it can use all of the lmmio_space,
	54	* elmmio_space and gmmio_space as a contiguous array of
	55	* resources. This #define represents the array size */
	56	#define DINO_MAX_LMMIO_RESOURCES 3
	57
	58	unsigned long lmmio_space_offset; /* CPU view - PCI view */
	59	void * iommu; /* IOMMU this device is under */
	60	/* REVISIT - spinlock to protect resources? */
	61
	62	#define HBA_NAME_SIZE 16
	63	char io_name[HBA_NAME_SIZE];
	64	char lmmio_name[HBA_NAME_SIZE];
	65	char elmmio_name[HBA_NAME_SIZE];
	66	char gmmio_name[HBA_NAME_SIZE];
	67	};
	68
	69	#define HBA_DATA(d) ((struct pci_hba_data *) (d))
	70
	71	/*
	72	** We support 2^16 I/O ports per HBA. These are set up in the form
	73	** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port
	74	** space address.
	75	*/
	76	#define HBA_PORT_SPACE_BITS 16
	77
	78	#define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS)
	79	#define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS)
	80
	81	#define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS)
	82	#define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1))
	83
74d13f84	84	#ifdef CONFIG_64BIT
1da177e4	85	#define PCI_F_EXTEND 0xffffffff00000000UL
1da177e4	86	#else /* !CONFIG_64BIT */
1da177e4	87	#define PCI_F_EXTEND 0UL
1da177e4 LT	88	#endif /* !CONFIG_64BIT */
	89
	90	/*
	91	** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus
	92	** (This eliminates some of the warnings).
	93	*/
	94	struct pci_bus;
	95	struct pci_dev;
	96
	97	/*
	98	* If the PCI device's view of memory is the same as the CPU's view of memory,
	99	* PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use
	100	* this boolean for bounce buffer decisions.
	101	*/
	102	#ifdef CONFIG_PA20
	103	/* All PA-2.0 machines have an IOMMU. */
	104	#define PCI_DMA_BUS_IS_PHYS 0
	105	#define parisc_has_iommu() do { } while (0)
	106	#else
	107
	108	#if defined(CONFIG_IOMMU_CCIO) \|\| defined(CONFIG_IOMMU_SBA)
	109	extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */
	110	#define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys
	111	#define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0)
	112	#else
	113	#define PCI_DMA_BUS_IS_PHYS 1
	114	#define parisc_has_iommu() do { } while (0)
	115	#endif
	116
	117	#endif /* !CONFIG_PA20 */
	118
	119
	120	/*
	121	** Most PCI devices (eg Tulip, NCR720) also export the same registers
	122	** to both MMIO and I/O port space. Due to poor performance of I/O Port
0779bf2d	123	** access under HP PCI bus adapters, strongly recommend the use of MMIO
1da177e4 LT	124	** address space.
	125	**
	126	** While I'm at it more PA programming notes:
	127	**
	128	** 1) MMIO stores (writes) are posted operations. This means the processor
	129	** gets an "ACK" before the write actually gets to the device. A read
	130	** to the same device (or typically the bus adapter above it) will
	131	** force in-flight write transaction(s) out to the targeted device
	132	** before the read can complete.
	133	**
	134	** 2) The Programmed I/O (PIO) data may not always be strongly ordered with
	135	** respect to DMA on all platforms. Ie PIO data can reach the processor
	136	** before in-flight DMA reaches memory. Since most SMP PA platforms
	137	** are I/O coherent, it generally doesn't matter...but sometimes
	138	** it does.
	139	**
	140	** I've helped device driver writers debug both types of problems.
	141	*/
	142	struct pci_port_ops {
	143	u8 (inb) (struct pci_hba_data hba, u16 port);
	144	u16 (inw) (struct pci_hba_data hba, u16 port);
	145	u32 (inl) (struct pci_hba_data hba, u16 port);
	146	void (outb) (struct pci_hba_data hba, u16 port, u8 data);
	147	void (outw) (struct pci_hba_data hba, u16 port, u16 data);
	148	void (outl) (struct pci_hba_data hba, u16 port, u32 data);
	149	};
	150
	151
	152	struct pci_bios_ops {
	153	void (*init)(void);
	154	void (fixup_bus)(struct pci_bus bus);
	155	};
	156
1da177e4 LT	157	/*
	158	** Stuff declared in arch/parisc/kernel/pci.c
	159	*/
	160	extern struct pci_port_ops *pci_port;
	161	extern struct pci_bios_ops *pci_bios;
1da177e4 LT	162
	163	#ifdef CONFIG_PCI
	164	extern void pcibios_register_hba(struct pci_hba_data *);
	165	extern void pcibios_set_master(struct pci_dev *);
	166	#else
f13cec84	167	static inline void pcibios_register_hba(struct pci_hba_data *x)
1da177e4 LT	168	{
	169	}
	170	#endif
602c9c9a	171	extern void pcibios_init_bridge(struct pci_dev *);
1da177e4 LT	172
	173	/*
	174	* pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus()
	175	* 0 == check if bridge is numbered before re-numbering.
	176	* 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges.
	177	*
	178	* We should set this to zero for "legacy" platforms and one
	179	* for PAT platforms.
	180	*
	181	* But legacy platforms also need to renumber the busses below a Host
	182	* Bus controller. Adding a 4-port Tulip card on the first PCI root
	183	* bus of a C200 resulted in the secondary bus being numbered as 1.
	184	* The second PCI host bus controller's root bus had already been
	185	* assigned bus number 1 by firmware and sysfs complained.
	186	*
	187	* Firmware isn't doing anything wrong here since each controller
	188	* is its own PCI domain. It's simpler and easier for us to renumber
	189	* the busses rather than treat each Dino as a separate PCI domain.
	190	* Eventually, we may want to introduce PCI domains for Superdome or
	191	* rp7420/8420 boxes and then revisit this issue.
	192	*/
	193	#define pcibios_assign_all_busses() (1)
1da177e4 LT	194
	195	#define PCIBIOS_MIN_IO 0x10
	196	#define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */
	197
f3120945 MW	198	static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
	199	{
	200	return channel ? 15 : 14;
	201	}
	202
2cc7138f	203	#define HAVE_PCI_MMAP
6a94ca14	204	#define ARCH_GENERIC_PCI_MMAP_RESOURCE
2cc7138f	205
1da177e4	206	#endif /* __ASM_PARISC_PCI_H */