mm: remove CONFIG_NO_BOOTMEM
[linux-2.6-block.git] / arch / openrisc / Kconfig
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b2441318 1# SPDX-License-Identifier: GPL-2.0
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2#
3# For a description of the syntax of this configuration file,
395cf969 4# see Documentation/kbuild/kconfig-language.txt.
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5#
6
7config OPENRISC
8 def_bool y
5600779e 9 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
bc3ec75d 10 select DMA_DIRECT_OPS
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11 select OF
12 select OF_EARLY_FLATTREE
b4c4c6ee 13 select IRQ_DOMAIN
d1f6f28f 14 select HANDLE_DOMAIN_IRQ
f8c4a270 15 select HAVE_MEMBLOCK
8636f344 16 select GPIOLIB
f8c4a270 17 select HAVE_ARCH_TRACEHOOK
c0fcaf55 18 select SPARSE_IRQ
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19 select GENERIC_IRQ_CHIP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_IOMAP
9f13a1fd 23 select GENERIC_CPU_DEVICES
04ea1e91 24 select HAVE_UID16
0662d33a 25 select GENERIC_ATOMIC64
5bf8f6bf 26 select GENERIC_CLOCKEVENTS
8e6d08e0 27 select GENERIC_CLOCKEVENTS_BROADCAST
603d6637 28 select GENERIC_STRNCPY_FROM_USER
b48b2c3e 29 select GENERIC_STRNLEN_USER
8e6d08e0 30 select GENERIC_SMP_IDLE_THREAD
786d35d4 31 select MODULES_USE_ELF_RELA
d1a1dc0b 32 select HAVE_DEBUG_STACKOVERFLOW
4db8e6d2 33 select OR1K_PIC
fff7fb0b 34 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
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35 select ARCH_USE_QUEUED_SPINLOCKS
36 select ARCH_USE_QUEUED_RWLOCKS
9b54470a 37 select OMPIC if SMP
eecac38b 38 select ARCH_WANT_FRAME_POINTERS
c5ca4560 39 select GENERIC_IRQ_MULTI_HANDLER
f8c4a270 40
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41config CPU_BIG_ENDIAN
42 def_bool y
43
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44config MMU
45 def_bool y
46
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47config RWSEM_GENERIC_SPINLOCK
48 def_bool y
49
50config RWSEM_XCHGADD_ALGORITHM
51 def_bool n
52
53config GENERIC_HWEIGHT
54 def_bool y
55
ce816fa8 56config NO_IOPORT_MAP
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57 def_bool y
58
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59config TRACE_IRQFLAGS_SUPPORT
60 def_bool y
61
62# For now, use generic checksum functions
63#These can be reimplemented in assembly later if so inclined
64config GENERIC_CSUM
65 def_bool y
66
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SH
67config STACKTRACE_SUPPORT
68 def_bool y
69
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70config LOCKDEP_SUPPORT
71 def_bool y
72
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73menu "Processor type and features"
74
75choice
76 prompt "Subarchitecture"
77 default OR1K_1200
78
79config OR1K_1200
80 bool "OR1200"
81 help
82 Generic OpenRISC 1200 architecture
83
84endchoice
85
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86config DCACHE_WRITETHROUGH
87 bool "Have write through data caches"
88 default n
89 help
90 Select this if your implementation features write through data caches.
91 Selecting 'N' here will allow the kernel to force flushing of data
92 caches at relevant times. Most OpenRISC implementations support write-
93 through data caches.
94
95 If unsure say N here
96
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97config OPENRISC_BUILTIN_DTB
98 string "Builtin DTB"
99 default ""
100
101menu "Class II Instructions"
102
103config OPENRISC_HAVE_INST_FF1
104 bool "Have instruction l.ff1"
105 default y
106 help
107 Select this if your implementation has the Class II instruction l.ff1
108
109config OPENRISC_HAVE_INST_FL1
110 bool "Have instruction l.fl1"
111 default y
112 help
113 Select this if your implementation has the Class II instruction l.fl1
114
115config OPENRISC_HAVE_INST_MUL
116 bool "Have instruction l.mul for hardware multiply"
117 default y
118 help
119 Select this if your implementation has a hardware multiply instruction
120
121config OPENRISC_HAVE_INST_DIV
122 bool "Have instruction l.div for hardware divide"
123 default y
124 help
125 Select this if your implementation has a hardware divide instruction
126endmenu
127
34bbdcdc 128config NR_CPUS
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129 int "Maximum number of CPUs (2-32)"
130 range 2 32
131 depends on SMP
132 default "2"
133
134config SMP
135 bool "Symmetric Multi-Processing support"
136 help
137 This enables support for systems with more than one CPU. If you have
138 a system with only one CPU, say N. If you have a system with more
139 than one CPU, say Y.
140
141 If you don't know what to do here, say N.
f8c4a270 142
f8c4a270 143source kernel/Kconfig.hz
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144
145config OPENRISC_NO_SPR_SR_DSX
146 bool "use SPR_SR_DSX software emulation" if OR1K_1200
147 default y
148 help
149 SPR_SR_DSX bit is status register bit indicating whether
150 the last exception has happened in delay slot.
151
152 OpenRISC architecture makes it optional to have it implemented
153 in hardware and the OR1200 does not have it.
154
155 Say N here if you know that your OpenRISC processor has
156 SPR_SR_DSX bit implemented. Say Y if you are unsure.
157
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SK
158config OPENRISC_HAVE_SHADOW_GPRS
159 bool "Support for shadow gpr files" if !SMP
160 default y if SMP
161 help
162 Say Y here if your OpenRISC processor features shadowed
163 register files. They will in such case be used as a
164 scratch reg storage on exception entry.
165
166 On SMP systems, this feature is mandatory.
167 On a unicore system it's safe to say N here if you are unsure.
168
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169config CMDLINE
170 string "Default kernel command string"
171 default ""
172 help
173 On some architectures there is currently no way for the boot loader
174 to pass arguments to the kernel. For these architectures, you should
175 supply some command-line options at build time by entering them
176 here.
177
178menu "Debugging options"
179
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180config JUMP_UPON_UNHANDLED_EXCEPTION
181 bool "Try to die gracefully"
182 default y
183 help
184 Now this puts kernel into infinite loop after first oops. Till
185 your kernel crashes this doesn't have any influence.
186
187 Say Y if you are unsure.
188
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189config OPENRISC_ESR_EXCEPTION_BUG_CHECK
190 bool "Check for possible ESR exception bug"
191 default n
192 help
193 This option enables some checks that might expose some problems
194 in kernel.
195
196 Say N if you are unsure.
197
198endmenu
199
200endmenu