Commit | Line | Data |
---|---|---|
f8c4a270 JB |
1 | # |
2 | # For a description of the syntax of this configuration file, | |
395cf969 | 3 | # see Documentation/kbuild/kconfig-language.txt. |
f8c4a270 JB |
4 | # |
5 | ||
6 | config OPENRISC | |
7 | def_bool y | |
8 | select OF | |
9 | select OF_EARLY_FLATTREE | |
b4c4c6ee | 10 | select IRQ_DOMAIN |
d1f6f28f | 11 | select HANDLE_DOMAIN_IRQ |
f8c4a270 | 12 | select HAVE_MEMBLOCK |
8636f344 | 13 | select GPIOLIB |
f8c4a270 | 14 | select HAVE_ARCH_TRACEHOOK |
c0fcaf55 | 15 | select SPARSE_IRQ |
f8c4a270 JB |
16 | select GENERIC_IRQ_CHIP |
17 | select GENERIC_IRQ_PROBE | |
18 | select GENERIC_IRQ_SHOW | |
19 | select GENERIC_IOMAP | |
9f13a1fd | 20 | select GENERIC_CPU_DEVICES |
04ea1e91 | 21 | select HAVE_UID16 |
0662d33a | 22 | select GENERIC_ATOMIC64 |
5bf8f6bf | 23 | select GENERIC_CLOCKEVENTS |
603d6637 | 24 | select GENERIC_STRNCPY_FROM_USER |
b48b2c3e | 25 | select GENERIC_STRNLEN_USER |
786d35d4 | 26 | select MODULES_USE_ELF_RELA |
d1a1dc0b | 27 | select HAVE_DEBUG_STACKOVERFLOW |
4db8e6d2 | 28 | select OR1K_PIC |
fff7fb0b | 29 | select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 |
266c7fad | 30 | select NO_BOOTMEM |
f8c4a270 | 31 | |
4c97a0c8 BM |
32 | config CPU_BIG_ENDIAN |
33 | def_bool y | |
34 | ||
f8c4a270 JB |
35 | config MMU |
36 | def_bool y | |
37 | ||
f8c4a270 JB |
38 | config RWSEM_GENERIC_SPINLOCK |
39 | def_bool y | |
40 | ||
41 | config RWSEM_XCHGADD_ALGORITHM | |
42 | def_bool n | |
43 | ||
44 | config GENERIC_HWEIGHT | |
45 | def_bool y | |
46 | ||
ce816fa8 | 47 | config NO_IOPORT_MAP |
f8c4a270 JB |
48 | def_bool y |
49 | ||
f8c4a270 JB |
50 | config TRACE_IRQFLAGS_SUPPORT |
51 | def_bool y | |
52 | ||
53 | # For now, use generic checksum functions | |
54 | #These can be reimplemented in assembly later if so inclined | |
55 | config GENERIC_CSUM | |
56 | def_bool y | |
57 | ||
f8c4a270 JB |
58 | source "init/Kconfig" |
59 | ||
57a1a197 | 60 | source "kernel/Kconfig.freezer" |
f8c4a270 JB |
61 | |
62 | menu "Processor type and features" | |
63 | ||
64 | choice | |
65 | prompt "Subarchitecture" | |
66 | default OR1K_1200 | |
67 | ||
68 | config OR1K_1200 | |
69 | bool "OR1200" | |
70 | help | |
71 | Generic OpenRISC 1200 architecture | |
72 | ||
73 | endchoice | |
74 | ||
75 | config OPENRISC_BUILTIN_DTB | |
76 | string "Builtin DTB" | |
77 | default "" | |
78 | ||
79 | menu "Class II Instructions" | |
80 | ||
81 | config OPENRISC_HAVE_INST_FF1 | |
82 | bool "Have instruction l.ff1" | |
83 | default y | |
84 | help | |
85 | Select this if your implementation has the Class II instruction l.ff1 | |
86 | ||
87 | config OPENRISC_HAVE_INST_FL1 | |
88 | bool "Have instruction l.fl1" | |
89 | default y | |
90 | help | |
91 | Select this if your implementation has the Class II instruction l.fl1 | |
92 | ||
93 | config OPENRISC_HAVE_INST_MUL | |
94 | bool "Have instruction l.mul for hardware multiply" | |
95 | default y | |
96 | help | |
97 | Select this if your implementation has a hardware multiply instruction | |
98 | ||
99 | config OPENRISC_HAVE_INST_DIV | |
100 | bool "Have instruction l.div for hardware divide" | |
101 | default y | |
102 | help | |
103 | Select this if your implementation has a hardware divide instruction | |
104 | endmenu | |
105 | ||
34bbdcdc SH |
106 | config NR_CPUS |
107 | int | |
108 | default "1" | |
f8c4a270 | 109 | |
f8c4a270 JB |
110 | source kernel/Kconfig.hz |
111 | source kernel/Kconfig.preempt | |
112 | source "mm/Kconfig" | |
113 | ||
114 | config OPENRISC_NO_SPR_SR_DSX | |
115 | bool "use SPR_SR_DSX software emulation" if OR1K_1200 | |
116 | default y | |
117 | help | |
118 | SPR_SR_DSX bit is status register bit indicating whether | |
119 | the last exception has happened in delay slot. | |
120 | ||
121 | OpenRISC architecture makes it optional to have it implemented | |
122 | in hardware and the OR1200 does not have it. | |
123 | ||
124 | Say N here if you know that your OpenRISC processor has | |
125 | SPR_SR_DSX bit implemented. Say Y if you are unsure. | |
126 | ||
91993c8c SK |
127 | config OPENRISC_HAVE_SHADOW_GPRS |
128 | bool "Support for shadow gpr files" if !SMP | |
129 | default y if SMP | |
130 | help | |
131 | Say Y here if your OpenRISC processor features shadowed | |
132 | register files. They will in such case be used as a | |
133 | scratch reg storage on exception entry. | |
134 | ||
135 | On SMP systems, this feature is mandatory. | |
136 | On a unicore system it's safe to say N here if you are unsure. | |
137 | ||
f8c4a270 JB |
138 | config CMDLINE |
139 | string "Default kernel command string" | |
140 | default "" | |
141 | help | |
142 | On some architectures there is currently no way for the boot loader | |
143 | to pass arguments to the kernel. For these architectures, you should | |
144 | supply some command-line options at build time by entering them | |
145 | here. | |
146 | ||
147 | menu "Debugging options" | |
148 | ||
f8c4a270 JB |
149 | config JUMP_UPON_UNHANDLED_EXCEPTION |
150 | bool "Try to die gracefully" | |
151 | default y | |
152 | help | |
153 | Now this puts kernel into infinite loop after first oops. Till | |
154 | your kernel crashes this doesn't have any influence. | |
155 | ||
156 | Say Y if you are unsure. | |
157 | ||
f8c4a270 JB |
158 | config OPENRISC_ESR_EXCEPTION_BUG_CHECK |
159 | bool "Check for possible ESR exception bug" | |
160 | default n | |
161 | help | |
162 | This option enables some checks that might expose some problems | |
163 | in kernel. | |
164 | ||
165 | Say N if you are unsure. | |
166 | ||
167 | endmenu | |
168 | ||
169 | endmenu | |
170 | ||
171 | menu "Executable file formats" | |
172 | ||
173 | source "fs/Kconfig.binfmt" | |
174 | ||
175 | endmenu | |
176 | ||
177 | source "net/Kconfig" | |
178 | ||
179 | source "drivers/Kconfig" | |
180 | ||
181 | source "fs/Kconfig" | |
182 | ||
183 | source "security/Kconfig" | |
184 | ||
185 | source "crypto/Kconfig" | |
186 | ||
187 | source "lib/Kconfig" | |
188 | ||
189 | menu "Kernel hacking" | |
190 | ||
191 | source "lib/Kconfig.debug" | |
192 | ||
193 | endmenu |