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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
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2 | # |
3 | # For a description of the syntax of this configuration file, | |
395cf969 | 4 | # see Documentation/kbuild/kconfig-language.txt. |
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5 | # |
6 | ||
7 | config OPENRISC | |
8 | def_bool y | |
9 | select OF | |
10 | select OF_EARLY_FLATTREE | |
b4c4c6ee | 11 | select IRQ_DOMAIN |
d1f6f28f | 12 | select HANDLE_DOMAIN_IRQ |
f8c4a270 | 13 | select HAVE_MEMBLOCK |
8636f344 | 14 | select GPIOLIB |
f8c4a270 | 15 | select HAVE_ARCH_TRACEHOOK |
c0fcaf55 | 16 | select SPARSE_IRQ |
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17 | select GENERIC_IRQ_CHIP |
18 | select GENERIC_IRQ_PROBE | |
19 | select GENERIC_IRQ_SHOW | |
20 | select GENERIC_IOMAP | |
9f13a1fd | 21 | select GENERIC_CPU_DEVICES |
04ea1e91 | 22 | select HAVE_UID16 |
0662d33a | 23 | select GENERIC_ATOMIC64 |
5bf8f6bf | 24 | select GENERIC_CLOCKEVENTS |
8e6d08e0 | 25 | select GENERIC_CLOCKEVENTS_BROADCAST |
603d6637 | 26 | select GENERIC_STRNCPY_FROM_USER |
b48b2c3e | 27 | select GENERIC_STRNLEN_USER |
8e6d08e0 | 28 | select GENERIC_SMP_IDLE_THREAD |
786d35d4 | 29 | select MODULES_USE_ELF_RELA |
83fbdf1c | 30 | select MULTI_IRQ_HANDLER |
d1a1dc0b | 31 | select HAVE_DEBUG_STACKOVERFLOW |
4db8e6d2 | 32 | select OR1K_PIC |
fff7fb0b | 33 | select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 |
266c7fad | 34 | select NO_BOOTMEM |
b5f82176 SH |
35 | select ARCH_USE_QUEUED_SPINLOCKS |
36 | select ARCH_USE_QUEUED_RWLOCKS | |
9b54470a | 37 | select OMPIC if SMP |
eecac38b | 38 | select ARCH_WANT_FRAME_POINTERS |
f8c4a270 | 39 | |
4c97a0c8 BM |
40 | config CPU_BIG_ENDIAN |
41 | def_bool y | |
42 | ||
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43 | config MMU |
44 | def_bool y | |
45 | ||
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46 | config RWSEM_GENERIC_SPINLOCK |
47 | def_bool y | |
48 | ||
49 | config RWSEM_XCHGADD_ALGORITHM | |
50 | def_bool n | |
51 | ||
52 | config GENERIC_HWEIGHT | |
53 | def_bool y | |
54 | ||
ce816fa8 | 55 | config NO_IOPORT_MAP |
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56 | def_bool y |
57 | ||
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58 | config TRACE_IRQFLAGS_SUPPORT |
59 | def_bool y | |
60 | ||
61 | # For now, use generic checksum functions | |
62 | #These can be reimplemented in assembly later if so inclined | |
63 | config GENERIC_CSUM | |
64 | def_bool y | |
65 | ||
eecac38b SH |
66 | config STACKTRACE_SUPPORT |
67 | def_bool y | |
68 | ||
78cdfb5c SH |
69 | config LOCKDEP_SUPPORT |
70 | def_bool y | |
71 | ||
83fbdf1c PD |
72 | config MULTI_IRQ_HANDLER |
73 | def_bool y | |
74 | ||
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75 | menu "Processor type and features" |
76 | ||
77 | choice | |
78 | prompt "Subarchitecture" | |
79 | default OR1K_1200 | |
80 | ||
81 | config OR1K_1200 | |
82 | bool "OR1200" | |
83 | help | |
84 | Generic OpenRISC 1200 architecture | |
85 | ||
86 | endchoice | |
87 | ||
4ee93d80 JHW |
88 | config DCACHE_WRITETHROUGH |
89 | bool "Have write through data caches" | |
90 | default n | |
91 | help | |
92 | Select this if your implementation features write through data caches. | |
93 | Selecting 'N' here will allow the kernel to force flushing of data | |
94 | caches at relevant times. Most OpenRISC implementations support write- | |
95 | through data caches. | |
96 | ||
97 | If unsure say N here | |
98 | ||
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99 | config OPENRISC_BUILTIN_DTB |
100 | string "Builtin DTB" | |
101 | default "" | |
102 | ||
103 | menu "Class II Instructions" | |
104 | ||
105 | config OPENRISC_HAVE_INST_FF1 | |
106 | bool "Have instruction l.ff1" | |
107 | default y | |
108 | help | |
109 | Select this if your implementation has the Class II instruction l.ff1 | |
110 | ||
111 | config OPENRISC_HAVE_INST_FL1 | |
112 | bool "Have instruction l.fl1" | |
113 | default y | |
114 | help | |
115 | Select this if your implementation has the Class II instruction l.fl1 | |
116 | ||
117 | config OPENRISC_HAVE_INST_MUL | |
118 | bool "Have instruction l.mul for hardware multiply" | |
119 | default y | |
120 | help | |
121 | Select this if your implementation has a hardware multiply instruction | |
122 | ||
123 | config OPENRISC_HAVE_INST_DIV | |
124 | bool "Have instruction l.div for hardware divide" | |
125 | default y | |
126 | help | |
127 | Select this if your implementation has a hardware divide instruction | |
128 | endmenu | |
129 | ||
34bbdcdc | 130 | config NR_CPUS |
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131 | int "Maximum number of CPUs (2-32)" |
132 | range 2 32 | |
133 | depends on SMP | |
134 | default "2" | |
135 | ||
136 | config SMP | |
137 | bool "Symmetric Multi-Processing support" | |
138 | help | |
139 | This enables support for systems with more than one CPU. If you have | |
140 | a system with only one CPU, say N. If you have a system with more | |
141 | than one CPU, say Y. | |
142 | ||
143 | If you don't know what to do here, say N. | |
f8c4a270 | 144 | |
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145 | source kernel/Kconfig.hz |
146 | source kernel/Kconfig.preempt | |
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147 | |
148 | config OPENRISC_NO_SPR_SR_DSX | |
149 | bool "use SPR_SR_DSX software emulation" if OR1K_1200 | |
150 | default y | |
151 | help | |
152 | SPR_SR_DSX bit is status register bit indicating whether | |
153 | the last exception has happened in delay slot. | |
154 | ||
155 | OpenRISC architecture makes it optional to have it implemented | |
156 | in hardware and the OR1200 does not have it. | |
157 | ||
158 | Say N here if you know that your OpenRISC processor has | |
159 | SPR_SR_DSX bit implemented. Say Y if you are unsure. | |
160 | ||
91993c8c SK |
161 | config OPENRISC_HAVE_SHADOW_GPRS |
162 | bool "Support for shadow gpr files" if !SMP | |
163 | default y if SMP | |
164 | help | |
165 | Say Y here if your OpenRISC processor features shadowed | |
166 | register files. They will in such case be used as a | |
167 | scratch reg storage on exception entry. | |
168 | ||
169 | On SMP systems, this feature is mandatory. | |
170 | On a unicore system it's safe to say N here if you are unsure. | |
171 | ||
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172 | config CMDLINE |
173 | string "Default kernel command string" | |
174 | default "" | |
175 | help | |
176 | On some architectures there is currently no way for the boot loader | |
177 | to pass arguments to the kernel. For these architectures, you should | |
178 | supply some command-line options at build time by entering them | |
179 | here. | |
180 | ||
181 | menu "Debugging options" | |
182 | ||
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183 | config JUMP_UPON_UNHANDLED_EXCEPTION |
184 | bool "Try to die gracefully" | |
185 | default y | |
186 | help | |
187 | Now this puts kernel into infinite loop after first oops. Till | |
188 | your kernel crashes this doesn't have any influence. | |
189 | ||
190 | Say Y if you are unsure. | |
191 | ||
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192 | config OPENRISC_ESR_EXCEPTION_BUG_CHECK |
193 | bool "Check for possible ESR exception bug" | |
194 | default n | |
195 | help | |
196 | This option enables some checks that might expose some problems | |
197 | in kernel. | |
198 | ||
199 | Say N if you are unsure. | |
200 | ||
201 | endmenu | |
202 | ||
203 | endmenu |