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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
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2 | # |
3 | # For a description of the syntax of this configuration file, | |
cd238eff | 4 | # see Documentation/kbuild/kconfig-language.rst. |
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5 | # |
6 | ||
7 | config OPENRISC | |
8 | def_bool y | |
942fa985 | 9 | select ARCH_32BIT_OFF_T |
a4a4d11a CH |
10 | select ARCH_HAS_DMA_SET_UNCACHED |
11 | select ARCH_HAS_DMA_CLEAR_UNCACHED | |
5600779e | 12 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
7f435e42 | 13 | select COMMON_CLK |
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14 | select OF |
15 | select OF_EARLY_FLATTREE | |
b4c4c6ee | 16 | select IRQ_DOMAIN |
8636f344 | 17 | select GPIOLIB |
0ecdcaa6 | 18 | select HAVE_ARCH_TRACEHOOK |
c0fcaf55 | 19 | select SPARSE_IRQ |
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20 | select GENERIC_IRQ_CHIP |
21 | select GENERIC_IRQ_PROBE | |
22 | select GENERIC_IRQ_SHOW | |
ded2ee36 | 23 | select GENERIC_PCI_IOMAP |
9f13a1fd | 24 | select GENERIC_CPU_DEVICES |
ded2ee36 | 25 | select HAVE_PCI |
04ea1e91 | 26 | select HAVE_UID16 |
0662d33a | 27 | select GENERIC_ATOMIC64 |
8e6d08e0 | 28 | select GENERIC_CLOCKEVENTS_BROADCAST |
8e6d08e0 | 29 | select GENERIC_SMP_IDLE_THREAD |
786d35d4 | 30 | select MODULES_USE_ELF_RELA |
d1a1dc0b | 31 | select HAVE_DEBUG_STACKOVERFLOW |
4db8e6d2 | 32 | select OR1K_PIC |
fff7fb0b | 33 | select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 |
b5f82176 | 34 | select ARCH_USE_QUEUED_RWLOCKS |
9b54470a | 35 | select OMPIC if SMP |
ded2ee36 SH |
36 | select PCI_DOMAINS_GENERIC if PCI |
37 | select PCI_MSI if PCI | |
eecac38b | 38 | select ARCH_WANT_FRAME_POINTERS |
c5ca4560 | 39 | select GENERIC_IRQ_MULTI_HANDLER |
6137fed0 | 40 | select MMU_GATHER_NO_RANGE if MMU |
4aae683f | 41 | select TRACE_IRQFLAGS_SUPPORT |
f8c4a270 | 42 | |
4c97a0c8 BM |
43 | config CPU_BIG_ENDIAN |
44 | def_bool y | |
45 | ||
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46 | config MMU |
47 | def_bool y | |
48 | ||
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49 | config GENERIC_HWEIGHT |
50 | def_bool y | |
51 | ||
ce816fa8 | 52 | config NO_IOPORT_MAP |
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53 | def_bool y |
54 | ||
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55 | # For now, use generic checksum functions |
56 | #These can be reimplemented in assembly later if so inclined | |
57 | config GENERIC_CSUM | |
0ecdcaa6 | 58 | def_bool y |
f8c4a270 | 59 | |
eecac38b SH |
60 | config STACKTRACE_SUPPORT |
61 | def_bool y | |
62 | ||
78cdfb5c SH |
63 | config LOCKDEP_SUPPORT |
64 | def_bool y | |
65 | ||
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66 | menu "Processor type and features" |
67 | ||
68 | choice | |
69 | prompt "Subarchitecture" | |
70 | default OR1K_1200 | |
71 | ||
72 | config OR1K_1200 | |
73 | bool "OR1200" | |
74 | help | |
75 | Generic OpenRISC 1200 architecture | |
76 | ||
77 | endchoice | |
78 | ||
4ee93d80 JHW |
79 | config DCACHE_WRITETHROUGH |
80 | bool "Have write through data caches" | |
81 | default n | |
82 | help | |
83 | Select this if your implementation features write through data caches. | |
84 | Selecting 'N' here will allow the kernel to force flushing of data | |
85 | caches at relevant times. Most OpenRISC implementations support write- | |
86 | through data caches. | |
87 | ||
88 | If unsure say N here | |
89 | ||
f8c4a270 | 90 | config OPENRISC_BUILTIN_DTB |
0ecdcaa6 KK |
91 | string "Builtin DTB" |
92 | default "" | |
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93 | |
94 | menu "Class II Instructions" | |
95 | ||
96 | config OPENRISC_HAVE_INST_FF1 | |
97 | bool "Have instruction l.ff1" | |
98 | default y | |
99 | help | |
100 | Select this if your implementation has the Class II instruction l.ff1 | |
101 | ||
102 | config OPENRISC_HAVE_INST_FL1 | |
103 | bool "Have instruction l.fl1" | |
104 | default y | |
105 | help | |
106 | Select this if your implementation has the Class II instruction l.fl1 | |
107 | ||
108 | config OPENRISC_HAVE_INST_MUL | |
109 | bool "Have instruction l.mul for hardware multiply" | |
110 | default y | |
111 | help | |
112 | Select this if your implementation has a hardware multiply instruction | |
113 | ||
114 | config OPENRISC_HAVE_INST_DIV | |
115 | bool "Have instruction l.div for hardware divide" | |
116 | default y | |
117 | help | |
118 | Select this if your implementation has a hardware divide instruction | |
87e387ac SH |
119 | |
120 | config OPENRISC_HAVE_INST_CMOV | |
121 | bool "Have instruction l.cmov for conditional move" | |
122 | default n | |
123 | help | |
124 | This config enables gcc to generate l.cmov instructions when compiling | |
125 | the kernel which in general will improve performance and reduce the | |
126 | binary size. | |
127 | ||
128 | Select this if your implementation has support for the Class II | |
129 | l.cmov conistional move instruction. | |
130 | ||
131 | Say N if you are unsure. | |
132 | ||
133 | config OPENRISC_HAVE_INST_ROR | |
134 | bool "Have instruction l.ror for rotate right" | |
135 | default n | |
136 | help | |
137 | This config enables gcc to generate l.ror instructions when compiling | |
138 | the kernel which in general will improve performance and reduce the | |
139 | binary size. | |
140 | ||
141 | Select this if your implementation has support for the Class II | |
142 | l.ror rotate right instruction. | |
143 | ||
144 | Say N if you are unsure. | |
145 | ||
146 | config OPENRISC_HAVE_INST_RORI | |
147 | bool "Have instruction l.rori for rotate right with immediate" | |
148 | default n | |
149 | help | |
150 | This config enables gcc to generate l.rori instructions when compiling | |
151 | the kernel which in general will improve performance and reduce the | |
152 | binary size. | |
153 | ||
154 | Select this if your implementation has support for the Class II | |
155 | l.rori rotate right with immediate instruction. | |
156 | ||
157 | Say N if you are unsure. | |
158 | ||
159 | config OPENRISC_HAVE_INST_SEXT | |
160 | bool "Have instructions l.ext* for sign extension" | |
161 | default n | |
162 | help | |
163 | This config enables gcc to generate l.ext* instructions when compiling | |
164 | the kernel which in general will improve performance and reduce the | |
165 | binary size. | |
166 | ||
167 | Select this if your implementation has support for the Class II | |
168 | l.exths, l.extbs, l.exthz and l.extbz size extend instructions. | |
169 | ||
170 | Say N if you are unsure. | |
171 | ||
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172 | endmenu |
173 | ||
34bbdcdc | 174 | config NR_CPUS |
8e6d08e0 SK |
175 | int "Maximum number of CPUs (2-32)" |
176 | range 2 32 | |
177 | depends on SMP | |
178 | default "2" | |
179 | ||
180 | config SMP | |
181 | bool "Symmetric Multi-Processing support" | |
182 | help | |
183 | This enables support for systems with more than one CPU. If you have | |
184 | a system with only one CPU, say N. If you have a system with more | |
185 | than one CPU, say Y. | |
186 | ||
187 | If you don't know what to do here, say N. | |
f8c4a270 | 188 | |
8636a1f9 | 189 | source "kernel/Kconfig.hz" |
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190 | |
191 | config OPENRISC_NO_SPR_SR_DSX | |
192 | bool "use SPR_SR_DSX software emulation" if OR1K_1200 | |
193 | default y | |
194 | help | |
195 | SPR_SR_DSX bit is status register bit indicating whether | |
196 | the last exception has happened in delay slot. | |
197 | ||
198 | OpenRISC architecture makes it optional to have it implemented | |
199 | in hardware and the OR1200 does not have it. | |
200 | ||
201 | Say N here if you know that your OpenRISC processor has | |
202 | SPR_SR_DSX bit implemented. Say Y if you are unsure. | |
203 | ||
91993c8c SK |
204 | config OPENRISC_HAVE_SHADOW_GPRS |
205 | bool "Support for shadow gpr files" if !SMP | |
206 | default y if SMP | |
207 | help | |
208 | Say Y here if your OpenRISC processor features shadowed | |
209 | register files. They will in such case be used as a | |
210 | scratch reg storage on exception entry. | |
211 | ||
212 | On SMP systems, this feature is mandatory. | |
213 | On a unicore system it's safe to say N here if you are unsure. | |
214 | ||
f8c4a270 | 215 | config CMDLINE |
0ecdcaa6 KK |
216 | string "Default kernel command string" |
217 | default "" | |
218 | help | |
219 | On some architectures there is currently no way for the boot loader | |
220 | to pass arguments to the kernel. For these architectures, you should | |
221 | supply some command-line options at build time by entering them | |
222 | here. | |
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223 | |
224 | menu "Debugging options" | |
225 | ||
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226 | config JUMP_UPON_UNHANDLED_EXCEPTION |
227 | bool "Try to die gracefully" | |
228 | default y | |
229 | help | |
230 | Now this puts kernel into infinite loop after first oops. Till | |
231 | your kernel crashes this doesn't have any influence. | |
232 | ||
233 | Say Y if you are unsure. | |
234 | ||
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235 | config OPENRISC_ESR_EXCEPTION_BUG_CHECK |
236 | bool "Check for possible ESR exception bug" | |
237 | default n | |
238 | help | |
239 | This option enables some checks that might expose some problems | |
0ecdcaa6 | 240 | in kernel. |
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241 | |
242 | Say N if you are unsure. | |
243 | ||
244 | endmenu | |
245 | ||
246 | endmenu |