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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
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2 | # |
3 | # For a description of the syntax of this configuration file, | |
cd238eff | 4 | # see Documentation/kbuild/kconfig-language.rst. |
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5 | # |
6 | ||
7 | config OPENRISC | |
8 | def_bool y | |
942fa985 | 9 | select ARCH_32BIT_OFF_T |
a4a4d11a CH |
10 | select ARCH_HAS_DMA_SET_UNCACHED |
11 | select ARCH_HAS_DMA_CLEAR_UNCACHED | |
5600779e | 12 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
7f435e42 | 13 | select COMMON_CLK |
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14 | select OF |
15 | select OF_EARLY_FLATTREE | |
b4c4c6ee | 16 | select IRQ_DOMAIN |
8636f344 | 17 | select GPIOLIB |
0ecdcaa6 | 18 | select HAVE_ARCH_TRACEHOOK |
c0fcaf55 | 19 | select SPARSE_IRQ |
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20 | select GENERIC_IRQ_CHIP |
21 | select GENERIC_IRQ_PROBE | |
22 | select GENERIC_IRQ_SHOW | |
ded2ee36 | 23 | select GENERIC_PCI_IOMAP |
9b994429 | 24 | select GENERIC_IOREMAP |
9f13a1fd | 25 | select GENERIC_CPU_DEVICES |
ded2ee36 | 26 | select HAVE_PCI |
04ea1e91 | 27 | select HAVE_UID16 |
5394f1e9 | 28 | select HAVE_PAGE_SIZE_8KB |
0662d33a | 29 | select GENERIC_ATOMIC64 |
8e6d08e0 | 30 | select GENERIC_CLOCKEVENTS_BROADCAST |
8e6d08e0 | 31 | select GENERIC_SMP_IDLE_THREAD |
786d35d4 | 32 | select MODULES_USE_ELF_RELA |
d1a1dc0b | 33 | select HAVE_DEBUG_STACKOVERFLOW |
4db8e6d2 | 34 | select OR1K_PIC |
fff7fb0b | 35 | select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 |
b5f82176 | 36 | select ARCH_USE_QUEUED_RWLOCKS |
9b54470a | 37 | select OMPIC if SMP |
ded2ee36 SH |
38 | select PCI_DOMAINS_GENERIC if PCI |
39 | select PCI_MSI if PCI | |
eecac38b | 40 | select ARCH_WANT_FRAME_POINTERS |
c5ca4560 | 41 | select GENERIC_IRQ_MULTI_HANDLER |
6137fed0 | 42 | select MMU_GATHER_NO_RANGE if MMU |
4aae683f | 43 | select TRACE_IRQFLAGS_SUPPORT |
f8c4a270 | 44 | |
4c97a0c8 BM |
45 | config CPU_BIG_ENDIAN |
46 | def_bool y | |
47 | ||
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48 | config MMU |
49 | def_bool y | |
50 | ||
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51 | config GENERIC_HWEIGHT |
52 | def_bool y | |
53 | ||
ce816fa8 | 54 | config NO_IOPORT_MAP |
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55 | def_bool y |
56 | ||
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57 | # For now, use generic checksum functions |
58 | #These can be reimplemented in assembly later if so inclined | |
59 | config GENERIC_CSUM | |
0ecdcaa6 | 60 | def_bool y |
f8c4a270 | 61 | |
eecac38b SH |
62 | config STACKTRACE_SUPPORT |
63 | def_bool y | |
64 | ||
78cdfb5c SH |
65 | config LOCKDEP_SUPPORT |
66 | def_bool y | |
67 | ||
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68 | menu "Processor type and features" |
69 | ||
70 | choice | |
71 | prompt "Subarchitecture" | |
72 | default OR1K_1200 | |
73 | ||
74 | config OR1K_1200 | |
75 | bool "OR1200" | |
76 | help | |
77 | Generic OpenRISC 1200 architecture | |
78 | ||
79 | endchoice | |
80 | ||
4ee93d80 JHW |
81 | config DCACHE_WRITETHROUGH |
82 | bool "Have write through data caches" | |
83 | default n | |
84 | help | |
85 | Select this if your implementation features write through data caches. | |
86 | Selecting 'N' here will allow the kernel to force flushing of data | |
87 | caches at relevant times. Most OpenRISC implementations support write- | |
88 | through data caches. | |
89 | ||
90 | If unsure say N here | |
91 | ||
f8c4a270 | 92 | config OPENRISC_BUILTIN_DTB |
0ecdcaa6 KK |
93 | string "Builtin DTB" |
94 | default "" | |
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95 | |
96 | menu "Class II Instructions" | |
97 | ||
98 | config OPENRISC_HAVE_INST_FF1 | |
99 | bool "Have instruction l.ff1" | |
100 | default y | |
101 | help | |
102 | Select this if your implementation has the Class II instruction l.ff1 | |
103 | ||
104 | config OPENRISC_HAVE_INST_FL1 | |
105 | bool "Have instruction l.fl1" | |
106 | default y | |
107 | help | |
108 | Select this if your implementation has the Class II instruction l.fl1 | |
109 | ||
110 | config OPENRISC_HAVE_INST_MUL | |
111 | bool "Have instruction l.mul for hardware multiply" | |
112 | default y | |
113 | help | |
114 | Select this if your implementation has a hardware multiply instruction | |
115 | ||
116 | config OPENRISC_HAVE_INST_DIV | |
117 | bool "Have instruction l.div for hardware divide" | |
118 | default y | |
119 | help | |
120 | Select this if your implementation has a hardware divide instruction | |
87e387ac SH |
121 | |
122 | config OPENRISC_HAVE_INST_CMOV | |
123 | bool "Have instruction l.cmov for conditional move" | |
124 | default n | |
125 | help | |
126 | This config enables gcc to generate l.cmov instructions when compiling | |
127 | the kernel which in general will improve performance and reduce the | |
128 | binary size. | |
129 | ||
130 | Select this if your implementation has support for the Class II | |
131 | l.cmov conistional move instruction. | |
132 | ||
133 | Say N if you are unsure. | |
134 | ||
135 | config OPENRISC_HAVE_INST_ROR | |
136 | bool "Have instruction l.ror for rotate right" | |
137 | default n | |
138 | help | |
139 | This config enables gcc to generate l.ror instructions when compiling | |
140 | the kernel which in general will improve performance and reduce the | |
141 | binary size. | |
142 | ||
143 | Select this if your implementation has support for the Class II | |
144 | l.ror rotate right instruction. | |
145 | ||
146 | Say N if you are unsure. | |
147 | ||
148 | config OPENRISC_HAVE_INST_RORI | |
149 | bool "Have instruction l.rori for rotate right with immediate" | |
150 | default n | |
151 | help | |
152 | This config enables gcc to generate l.rori instructions when compiling | |
153 | the kernel which in general will improve performance and reduce the | |
154 | binary size. | |
155 | ||
156 | Select this if your implementation has support for the Class II | |
157 | l.rori rotate right with immediate instruction. | |
158 | ||
159 | Say N if you are unsure. | |
160 | ||
161 | config OPENRISC_HAVE_INST_SEXT | |
162 | bool "Have instructions l.ext* for sign extension" | |
163 | default n | |
164 | help | |
165 | This config enables gcc to generate l.ext* instructions when compiling | |
166 | the kernel which in general will improve performance and reduce the | |
167 | binary size. | |
168 | ||
169 | Select this if your implementation has support for the Class II | |
170 | l.exths, l.extbs, l.exthz and l.extbz size extend instructions. | |
171 | ||
172 | Say N if you are unsure. | |
173 | ||
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174 | endmenu |
175 | ||
34bbdcdc | 176 | config NR_CPUS |
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177 | int "Maximum number of CPUs (2-32)" |
178 | range 2 32 | |
179 | depends on SMP | |
180 | default "2" | |
181 | ||
182 | config SMP | |
183 | bool "Symmetric Multi-Processing support" | |
184 | help | |
185 | This enables support for systems with more than one CPU. If you have | |
186 | a system with only one CPU, say N. If you have a system with more | |
187 | than one CPU, say Y. | |
188 | ||
189 | If you don't know what to do here, say N. | |
f8c4a270 | 190 | |
8636a1f9 | 191 | source "kernel/Kconfig.hz" |
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192 | |
193 | config OPENRISC_NO_SPR_SR_DSX | |
194 | bool "use SPR_SR_DSX software emulation" if OR1K_1200 | |
195 | default y | |
196 | help | |
197 | SPR_SR_DSX bit is status register bit indicating whether | |
198 | the last exception has happened in delay slot. | |
199 | ||
200 | OpenRISC architecture makes it optional to have it implemented | |
201 | in hardware and the OR1200 does not have it. | |
202 | ||
203 | Say N here if you know that your OpenRISC processor has | |
204 | SPR_SR_DSX bit implemented. Say Y if you are unsure. | |
205 | ||
91993c8c SK |
206 | config OPENRISC_HAVE_SHADOW_GPRS |
207 | bool "Support for shadow gpr files" if !SMP | |
208 | default y if SMP | |
209 | help | |
210 | Say Y here if your OpenRISC processor features shadowed | |
211 | register files. They will in such case be used as a | |
212 | scratch reg storage on exception entry. | |
213 | ||
214 | On SMP systems, this feature is mandatory. | |
215 | On a unicore system it's safe to say N here if you are unsure. | |
216 | ||
f8c4a270 | 217 | config CMDLINE |
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218 | string "Default kernel command string" |
219 | default "" | |
220 | help | |
221 | On some architectures there is currently no way for the boot loader | |
222 | to pass arguments to the kernel. For these architectures, you should | |
223 | supply some command-line options at build time by entering them | |
224 | here. | |
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225 | |
226 | menu "Debugging options" | |
227 | ||
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228 | config JUMP_UPON_UNHANDLED_EXCEPTION |
229 | bool "Try to die gracefully" | |
230 | default y | |
231 | help | |
232 | Now this puts kernel into infinite loop after first oops. Till | |
233 | your kernel crashes this doesn't have any influence. | |
234 | ||
235 | Say Y if you are unsure. | |
236 | ||
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237 | config OPENRISC_ESR_EXCEPTION_BUG_CHECK |
238 | bool "Check for possible ESR exception bug" | |
239 | default n | |
240 | help | |
241 | This option enables some checks that might expose some problems | |
0ecdcaa6 | 242 | in kernel. |
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243 | |
244 | Say N if you are unsure. | |
245 | ||
246 | endmenu | |
247 | ||
248 | endmenu |