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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
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2 | # |
3 | # For a description of the syntax of this configuration file, | |
395cf969 | 4 | # see Documentation/kbuild/kconfig-language.txt. |
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5 | # |
6 | ||
7 | config OPENRISC | |
8 | def_bool y | |
5600779e | 9 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE |
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10 | select OF |
11 | select OF_EARLY_FLATTREE | |
b4c4c6ee | 12 | select IRQ_DOMAIN |
d1f6f28f | 13 | select HANDLE_DOMAIN_IRQ |
8636f344 | 14 | select GPIOLIB |
f8c4a270 | 15 | select HAVE_ARCH_TRACEHOOK |
c0fcaf55 | 16 | select SPARSE_IRQ |
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17 | select GENERIC_IRQ_CHIP |
18 | select GENERIC_IRQ_PROBE | |
19 | select GENERIC_IRQ_SHOW | |
20 | select GENERIC_IOMAP | |
9f13a1fd | 21 | select GENERIC_CPU_DEVICES |
04ea1e91 | 22 | select HAVE_UID16 |
0662d33a | 23 | select GENERIC_ATOMIC64 |
5bf8f6bf | 24 | select GENERIC_CLOCKEVENTS |
8e6d08e0 | 25 | select GENERIC_CLOCKEVENTS_BROADCAST |
603d6637 | 26 | select GENERIC_STRNCPY_FROM_USER |
b48b2c3e | 27 | select GENERIC_STRNLEN_USER |
8e6d08e0 | 28 | select GENERIC_SMP_IDLE_THREAD |
786d35d4 | 29 | select MODULES_USE_ELF_RELA |
d1a1dc0b | 30 | select HAVE_DEBUG_STACKOVERFLOW |
4db8e6d2 | 31 | select OR1K_PIC |
fff7fb0b | 32 | select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 |
b5f82176 SH |
33 | select ARCH_USE_QUEUED_SPINLOCKS |
34 | select ARCH_USE_QUEUED_RWLOCKS | |
9b54470a | 35 | select OMPIC if SMP |
eecac38b | 36 | select ARCH_WANT_FRAME_POINTERS |
c5ca4560 | 37 | select GENERIC_IRQ_MULTI_HANDLER |
f8c4a270 | 38 | |
4c97a0c8 BM |
39 | config CPU_BIG_ENDIAN |
40 | def_bool y | |
41 | ||
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42 | config MMU |
43 | def_bool y | |
44 | ||
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45 | config RWSEM_GENERIC_SPINLOCK |
46 | def_bool y | |
47 | ||
48 | config RWSEM_XCHGADD_ALGORITHM | |
49 | def_bool n | |
50 | ||
51 | config GENERIC_HWEIGHT | |
52 | def_bool y | |
53 | ||
ce816fa8 | 54 | config NO_IOPORT_MAP |
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55 | def_bool y |
56 | ||
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57 | config TRACE_IRQFLAGS_SUPPORT |
58 | def_bool y | |
59 | ||
60 | # For now, use generic checksum functions | |
61 | #These can be reimplemented in assembly later if so inclined | |
62 | config GENERIC_CSUM | |
63 | def_bool y | |
64 | ||
eecac38b SH |
65 | config STACKTRACE_SUPPORT |
66 | def_bool y | |
67 | ||
78cdfb5c SH |
68 | config LOCKDEP_SUPPORT |
69 | def_bool y | |
70 | ||
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71 | menu "Processor type and features" |
72 | ||
73 | choice | |
74 | prompt "Subarchitecture" | |
75 | default OR1K_1200 | |
76 | ||
77 | config OR1K_1200 | |
78 | bool "OR1200" | |
79 | help | |
80 | Generic OpenRISC 1200 architecture | |
81 | ||
82 | endchoice | |
83 | ||
4ee93d80 JHW |
84 | config DCACHE_WRITETHROUGH |
85 | bool "Have write through data caches" | |
86 | default n | |
87 | help | |
88 | Select this if your implementation features write through data caches. | |
89 | Selecting 'N' here will allow the kernel to force flushing of data | |
90 | caches at relevant times. Most OpenRISC implementations support write- | |
91 | through data caches. | |
92 | ||
93 | If unsure say N here | |
94 | ||
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95 | config OPENRISC_BUILTIN_DTB |
96 | string "Builtin DTB" | |
97 | default "" | |
98 | ||
99 | menu "Class II Instructions" | |
100 | ||
101 | config OPENRISC_HAVE_INST_FF1 | |
102 | bool "Have instruction l.ff1" | |
103 | default y | |
104 | help | |
105 | Select this if your implementation has the Class II instruction l.ff1 | |
106 | ||
107 | config OPENRISC_HAVE_INST_FL1 | |
108 | bool "Have instruction l.fl1" | |
109 | default y | |
110 | help | |
111 | Select this if your implementation has the Class II instruction l.fl1 | |
112 | ||
113 | config OPENRISC_HAVE_INST_MUL | |
114 | bool "Have instruction l.mul for hardware multiply" | |
115 | default y | |
116 | help | |
117 | Select this if your implementation has a hardware multiply instruction | |
118 | ||
119 | config OPENRISC_HAVE_INST_DIV | |
120 | bool "Have instruction l.div for hardware divide" | |
121 | default y | |
122 | help | |
123 | Select this if your implementation has a hardware divide instruction | |
124 | endmenu | |
125 | ||
34bbdcdc | 126 | config NR_CPUS |
8e6d08e0 SK |
127 | int "Maximum number of CPUs (2-32)" |
128 | range 2 32 | |
129 | depends on SMP | |
130 | default "2" | |
131 | ||
132 | config SMP | |
133 | bool "Symmetric Multi-Processing support" | |
134 | help | |
135 | This enables support for systems with more than one CPU. If you have | |
136 | a system with only one CPU, say N. If you have a system with more | |
137 | than one CPU, say Y. | |
138 | ||
139 | If you don't know what to do here, say N. | |
f8c4a270 | 140 | |
8636a1f9 | 141 | source "kernel/Kconfig.hz" |
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142 | |
143 | config OPENRISC_NO_SPR_SR_DSX | |
144 | bool "use SPR_SR_DSX software emulation" if OR1K_1200 | |
145 | default y | |
146 | help | |
147 | SPR_SR_DSX bit is status register bit indicating whether | |
148 | the last exception has happened in delay slot. | |
149 | ||
150 | OpenRISC architecture makes it optional to have it implemented | |
151 | in hardware and the OR1200 does not have it. | |
152 | ||
153 | Say N here if you know that your OpenRISC processor has | |
154 | SPR_SR_DSX bit implemented. Say Y if you are unsure. | |
155 | ||
91993c8c SK |
156 | config OPENRISC_HAVE_SHADOW_GPRS |
157 | bool "Support for shadow gpr files" if !SMP | |
158 | default y if SMP | |
159 | help | |
160 | Say Y here if your OpenRISC processor features shadowed | |
161 | register files. They will in such case be used as a | |
162 | scratch reg storage on exception entry. | |
163 | ||
164 | On SMP systems, this feature is mandatory. | |
165 | On a unicore system it's safe to say N here if you are unsure. | |
166 | ||
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167 | config CMDLINE |
168 | string "Default kernel command string" | |
169 | default "" | |
170 | help | |
171 | On some architectures there is currently no way for the boot loader | |
172 | to pass arguments to the kernel. For these architectures, you should | |
173 | supply some command-line options at build time by entering them | |
174 | here. | |
175 | ||
176 | menu "Debugging options" | |
177 | ||
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178 | config JUMP_UPON_UNHANDLED_EXCEPTION |
179 | bool "Try to die gracefully" | |
180 | default y | |
181 | help | |
182 | Now this puts kernel into infinite loop after first oops. Till | |
183 | your kernel crashes this doesn't have any influence. | |
184 | ||
185 | Say Y if you are unsure. | |
186 | ||
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187 | config OPENRISC_ESR_EXCEPTION_BUG_CHECK |
188 | bool "Check for possible ESR exception bug" | |
189 | default n | |
190 | help | |
191 | This option enables some checks that might expose some problems | |
192 | in kernel. | |
193 | ||
194 | Say N if you are unsure. | |
195 | ||
196 | endmenu | |
197 | ||
198 | endmenu |