[linux-2.6-block.git] / arch / nios2 / platform / Kconfig.platform

# SPDX-License-Identifier: GPL-2.0-only
menu "Platform options"

comment "Memory settings"

config NIOS2_MEM_BASE
	hex "Memory base address"
	default "0x00000000"
	help
	  This is the physical address of the memory that the kernel will run
	  from. This address is used to link the kernel and setup initial memory
	  management. You should take the raw memory address without any MMU
	  or cache bits set.
	  Please not that this address is used directly so you have to manually
	  do address translation if it's connected to a bridge.

comment "Device tree"

config NIOS2_DTB_AT_PHYS_ADDR
	bool "DTB at physical address"
	help
	  When enabled you can select a physical address to load the dtb from.
	  Normally this address is passed by a bootloader such as u-boot but
	  using this you can use a devicetree without a bootloader.
	  This way you can store a devicetree in NOR flash or an onchip rom.
	  Please note that this address is used directly so you have to manually
	  do address translation if it's connected to a bridge. Also take into
	  account that when using an MMU you'd have to ad 0xC0000000 to your
	  address

config NIOS2_DTB_PHYS_ADDR
	hex "DTB Address"
	depends on NIOS2_DTB_AT_PHYS_ADDR
	default "0xC0000000"
	help
	  Physical address of a dtb blob.

config NIOS2_DTB_SOURCE_BOOL
	bool "Compile and link device tree into kernel image"
	help
	  This allows you to specify a dts (device tree source) file
	  which will be compiled and linked into the kernel image.

config NIOS2_DTB_SOURCE
	string "Device tree source file"
	depends on NIOS2_DTB_SOURCE_BOOL
	default ""
	help
	  Absolute path to the device tree source (dts) file describing your
	  system.

comment "Nios II instructions"

config NIOS2_ARCH_REVISION
	int "Select Nios II architecture revision"
	range 1 2
	default 1
	help
	  Select between Nios II R1 and Nios II R2 . The architectures
	  are binary incompatible. Default is R1 .

config NIOS2_HW_MUL_SUPPORT
	bool "Enable MUL instruction"
	help
	  Set to true if you configured the Nios II to include the MUL
	  instruction.  This will enable the -mhw-mul compiler flag.

config NIOS2_HW_MULX_SUPPORT
	bool "Enable MULX instruction"
	help
	  Set to true if you configured the Nios II to include the MULX
	  instruction.  Enables the -mhw-mulx compiler flag.

config NIOS2_HW_DIV_SUPPORT
	bool "Enable DIV instruction"
	help
	  Set to true if you configured the Nios II to include the DIV
	  instruction.  Enables the -mhw-div compiler flag.

config NIOS2_BMX_SUPPORT
	bool "Enable BMX instructions"
	depends on NIOS2_ARCH_REVISION = 2
	help
	  Set to true if you configured the Nios II R2 to include
	  the BMX Bit Manipulation Extension instructions. Enables
	  the -mbmx compiler flag.

config NIOS2_CDX_SUPPORT
	bool "Enable CDX instructions"
	depends on NIOS2_ARCH_REVISION = 2
	help
	  Set to true if you configured the Nios II R2 to include
	  the CDX Bit Manipulation Extension instructions. Enables
	  the -mcdx compiler flag.

config NIOS2_FPU_SUPPORT
	bool "Custom floating point instr support"
	help
	  Enables the -mcustom-fpu-cfg=60-1 compiler flag.

config NIOS2_CI_SWAB_SUPPORT
	bool "Byteswap custom instruction"
	help
	  Use the byteswap (endian converter) Nios II custom instruction provided
	  by Altera and which can be enabled in QSYS builder. This accelerates
	  endian conversions in the kernel (e.g. ntohs).

config NIOS2_CI_SWAB_NO
	int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
	default 0
	help
	  Number of the instruction as configured in QSYS Builder.

comment "Cache settings"

config CUSTOM_CACHE_SETTINGS
	bool "Custom cache settings"
	help
	  This option allows you to tweak the cache settings used during early
	  boot (where the information from device tree is not yet available).
	  There should be no reason to change these values. Linux will work
	  perfectly fine, even if the Nios II is configured with smaller caches.

	  Say N here unless you know what you are doing.

config NIOS2_DCACHE_SIZE
	hex "D-Cache size" if CUSTOM_CACHE_SETTINGS
	range 0x200 0x10000
	default "0x800"
	help
	  Maximum possible data cache size.

config NIOS2_DCACHE_LINE_SIZE
	hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS
	range 0x10 0x20
	default "0x20"
	help
	  Minimum possible data cache line size.

config NIOS2_ICACHE_SIZE
	hex "I-Cache size" if CUSTOM_CACHE_SETTINGS
	range 0x200 0x10000
	default "0x1000"
	help
	  Maximum possible instruction cache size.

endmenu
Commit	Line	Data
ec8f24b7	1	# SPDX-License-Identifier: GPL-2.0-only
2fc8483f LFT	2	menu "Platform options"
	3
	4	comment "Memory settings"
	5
	6	config NIOS2_MEM_BASE
	7	hex "Memory base address"
	8	default "0x00000000"
	9	help
	10	This is the physical address of the memory that the kernel will run
	11	from. This address is used to link the kernel and setup initial memory
	12	management. You should take the raw memory address without any MMU
	13	or cache bits set.
	14	Please not that this address is used directly so you have to manually
	15	do address translation if it's connected to a bridge.
	16
	17	comment "Device tree"
	18
	19	config NIOS2_DTB_AT_PHYS_ADDR
	20	bool "DTB at physical address"
2fc8483f LFT	21	help
	22	When enabled you can select a physical address to load the dtb from.
	23	Normally this address is passed by a bootloader such as u-boot but
	24	using this you can use a devicetree without a bootloader.
	25	This way you can store a devicetree in NOR flash or an onchip rom.
	26	Please note that this address is used directly so you have to manually
	27	do address translation if it's connected to a bridge. Also take into
	28	account that when using an MMU you'd have to ad 0xC0000000 to your
	29	address
	30
	31	config NIOS2_DTB_PHYS_ADDR
	32	hex "DTB Address"
	33	depends on NIOS2_DTB_AT_PHYS_ADDR
	34	default "0xC0000000"
	35	help
	36	Physical address of a dtb blob.
	37
	38	config NIOS2_DTB_SOURCE_BOOL
	39	bool "Compile and link device tree into kernel image"
2fc8483f LFT	40	help
	41	This allows you to specify a dts (device tree source) file
	42	which will be compiled and linked into the kernel image.
	43
	44	config NIOS2_DTB_SOURCE
	45	string "Device tree source file"
	46	depends on NIOS2_DTB_SOURCE_BOOL
	47	default ""
	48	help
	49	Absolute path to the device tree source (dts) file describing your
	50	system.
	51
	52	comment "Nios II instructions"
	53
a89988a6 MV	54	config NIOS2_ARCH_REVISION
	55	int "Select Nios II architecture revision"
	56	range 1 2
	57	default 1
	58	help
	59	Select between Nios II R1 and Nios II R2 . The architectures
	60	are binary incompatible. Default is R1 .
	61
2fc8483f LFT	62	config NIOS2_HW_MUL_SUPPORT
2fc8483f LFT	63	bool "Enable MUL instruction"
2fc8483f LFT	64	help
	65	Set to true if you configured the Nios II to include the MUL
	66	instruction. This will enable the -mhw-mul compiler flag.
	67
	68	config NIOS2_HW_MULX_SUPPORT
	69	bool "Enable MULX instruction"
2fc8483f LFT	70	help
	71	Set to true if you configured the Nios II to include the MULX
	72	instruction. Enables the -mhw-mulx compiler flag.
	73
	74	config NIOS2_HW_DIV_SUPPORT
	75	bool "Enable DIV instruction"
2fc8483f LFT	76	help
	77	Set to true if you configured the Nios II to include the DIV
	78	instruction. Enables the -mhw-div compiler flag.
	79
23460839 MV	80	config NIOS2_BMX_SUPPORT
	81	bool "Enable BMX instructions"
	82	depends on NIOS2_ARCH_REVISION = 2
23460839 MV	83	help
	84	Set to true if you configured the Nios II R2 to include
	85	the BMX Bit Manipulation Extension instructions. Enables
	86	the -mbmx compiler flag.
	87
edebea98 MV	88	config NIOS2_CDX_SUPPORT
	89	bool "Enable CDX instructions"
	90	depends on NIOS2_ARCH_REVISION = 2
edebea98 MV	91	help
	92	Set to true if you configured the Nios II R2 to include
	93	the CDX Bit Manipulation Extension instructions. Enables
	94	the -mcdx compiler flag.
	95
2fc8483f LFT	96	config NIOS2_FPU_SUPPORT
2fc8483f LFT	97	bool "Custom floating point instr support"
2fc8483f LFT	98	help
	99	Enables the -mcustom-fpu-cfg=60-1 compiler flag.
	100
	101	config NIOS2_CI_SWAB_SUPPORT
	102	bool "Byteswap custom instruction"
2fc8483f LFT	103	help
	104	Use the byteswap (endian converter) Nios II custom instruction provided
	105	by Altera and which can be enabled in QSYS builder. This accelerates
	106	endian conversions in the kernel (e.g. ntohs).
	107
	108	config NIOS2_CI_SWAB_NO
	109	int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
	110	default 0
	111	help
	112	Number of the instruction as configured in QSYS Builder.
	113
	114	comment "Cache settings"
	115
	116	config CUSTOM_CACHE_SETTINGS
	117	bool "Custom cache settings"
	118	help
	119	This option allows you to tweak the cache settings used during early
	120	boot (where the information from device tree is not yet available).
	121	There should be no reason to change these values. Linux will work
	122	perfectly fine, even if the Nios II is configured with smaller caches.
	123
	124	Say N here unless you know what you are doing.
	125
	126	config NIOS2_DCACHE_SIZE
	127	hex "D-Cache size" if CUSTOM_CACHE_SETTINGS
	128	range 0x200 0x10000
	129	default "0x800"
	130	help
	131	Maximum possible data cache size.
	132
	133	config NIOS2_DCACHE_LINE_SIZE
	134	hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS
	135	range 0x10 0x20
	136	default "0x20"
	137	help
	138	Minimum possible data cache line size.
	139
	140	config NIOS2_ICACHE_SIZE
	141	hex "I-Cache size" if CUSTOM_CACHE_SETTINGS
	142	range 0x200 0x10000
	143	default "0x1000"
	144	help
	145	Maximum possible instruction cache size.
	146
	147	endmenu