Commit | Line | Data |
---|---|---|
1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 LT |
2 | /* |
3 | * icu.c, Interrupt Control Unit routines for the NEC VR4100 series. | |
4 | * | |
5 | * Copyright (C) 2001-2002 MontaVista Software Inc. | |
ada8e951 YY |
6 | * Author: Yoichi Yuasa <source@mvista.com> |
7 | * Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org> | |
1da177e4 LT |
8 | */ |
9 | /* | |
10 | * Changes: | |
ada8e951 | 11 | * MontaVista Software Inc. <source@mvista.com> |
1da177e4 LT |
12 | * - New creation, NEC VR4122 and VR4131 are supported. |
13 | * - Added support for NEC VR4111 and VR4121. | |
14 | * | |
ada8e951 | 15 | * Yoichi Yuasa <yuasa@linux-mips.org> |
1da177e4 LT |
16 | * - Coped with INTASSIGN of NEC VR4133. |
17 | */ | |
18 | #include <linux/errno.h> | |
26dd3e4f | 19 | #include <linux/export.h> |
1da177e4 | 20 | #include <linux/init.h> |
979934da | 21 | #include <linux/ioport.h> |
1da177e4 | 22 | #include <linux/irq.h> |
1da177e4 LT |
23 | #include <linux/smp.h> |
24 | #include <linux/types.h> | |
25 | ||
26 | #include <asm/cpu.h> | |
27 | #include <asm/io.h> | |
66151bbd | 28 | #include <asm/vr41xx/irq.h> |
1da177e4 LT |
29 | #include <asm/vr41xx/vr41xx.h> |
30 | ||
979934da YY |
31 | static void __iomem *icu1_base; |
32 | static void __iomem *icu2_base; | |
1da177e4 LT |
33 | |
34 | static unsigned char sysint1_assign[16] = { | |
35 | 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; | |
36 | static unsigned char sysint2_assign[16] = { | |
979934da | 37 | 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; |
1da177e4 | 38 | |
70342287 RB |
39 | #define ICU1_TYPE1_BASE 0x0b000080UL |
40 | #define ICU2_TYPE1_BASE 0x0b000200UL | |
1da177e4 | 41 | |
70342287 RB |
42 | #define ICU1_TYPE2_BASE 0x0f000080UL |
43 | #define ICU2_TYPE2_BASE 0x0f0000a0UL | |
979934da YY |
44 | |
45 | #define ICU1_SIZE 0x20 | |
46 | #define ICU2_SIZE 0x1c | |
1da177e4 LT |
47 | |
48 | #define SYSINT1REG 0x00 | |
49 | #define PIUINTREG 0x02 | |
50 | #define INTASSIGN0 0x04 | |
51 | #define INTASSIGN1 0x06 | |
52 | #define GIUINTLREG 0x08 | |
53 | #define DSIUINTREG 0x0a | |
54 | #define MSYSINT1REG 0x0c | |
55 | #define MPIUINTREG 0x0e | |
56 | #define MAIUINTREG 0x10 | |
57 | #define MKIUINTREG 0x12 | |
9a0ad9e9 | 58 | #define MMACINTREG 0x12 |
1da177e4 LT |
59 | #define MGIUINTLREG 0x14 |
60 | #define MDSIUINTREG 0x16 | |
61 | #define NMIREG 0x18 | |
62 | #define SOFTREG 0x1a | |
63 | #define INTASSIGN2 0x1c | |
64 | #define INTASSIGN3 0x1e | |
65 | ||
66 | #define SYSINT2REG 0x00 | |
67 | #define GIUINTHREG 0x02 | |
68 | #define FIRINTREG 0x04 | |
69 | #define MSYSINT2REG 0x06 | |
70 | #define MGIUINTHREG 0x08 | |
71 | #define MFIRINTREG 0x0a | |
72 | #define PCIINTREG 0x0c | |
73 | #define PCIINT0 0x0001 | |
74 | #define SCUINTREG 0x0e | |
75 | #define SCUINT0 0x0001 | |
76 | #define CSIINTREG 0x10 | |
77 | #define MPCIINTREG 0x12 | |
78 | #define MSCUINTREG 0x14 | |
79 | #define MCSIINTREG 0x16 | |
80 | #define BCUINTREG 0x18 | |
81 | #define BCUINTR 0x0001 | |
82 | #define MBCUINTREG 0x1a | |
83 | ||
84 | #define SYSINT1_IRQ_TO_PIN(x) ((x) - SYSINT1_IRQ_BASE) /* Pin 0-15 */ | |
85 | #define SYSINT2_IRQ_TO_PIN(x) ((x) - SYSINT2_IRQ_BASE) /* Pin 0-15 */ | |
86 | ||
979934da YY |
87 | #define INT_TO_IRQ(x) ((x) + 2) /* Int0-4 -> IRQ2-6 */ |
88 | ||
89 | #define icu1_read(offset) readw(icu1_base + (offset)) | |
90 | #define icu1_write(offset, value) writew((value), icu1_base + (offset)) | |
1da177e4 | 91 | |
979934da YY |
92 | #define icu2_read(offset) readw(icu2_base + (offset)) |
93 | #define icu2_write(offset, value) writew((value), icu2_base + (offset)) | |
1da177e4 LT |
94 | |
95 | #define INTASSIGN_MAX 4 | |
96 | #define INTASSIGN_MASK 0x0007 | |
97 | ||
979934da | 98 | static inline uint16_t icu1_set(uint8_t offset, uint16_t set) |
1da177e4 | 99 | { |
979934da | 100 | uint16_t data; |
1da177e4 | 101 | |
979934da YY |
102 | data = icu1_read(offset); |
103 | data |= set; | |
104 | icu1_write(offset, data); | |
1da177e4 | 105 | |
979934da | 106 | return data; |
1da177e4 LT |
107 | } |
108 | ||
979934da | 109 | static inline uint16_t icu1_clear(uint8_t offset, uint16_t clear) |
1da177e4 | 110 | { |
979934da | 111 | uint16_t data; |
1da177e4 | 112 | |
979934da YY |
113 | data = icu1_read(offset); |
114 | data &= ~clear; | |
115 | icu1_write(offset, data); | |
1da177e4 | 116 | |
979934da | 117 | return data; |
1da177e4 LT |
118 | } |
119 | ||
979934da | 120 | static inline uint16_t icu2_set(uint8_t offset, uint16_t set) |
1da177e4 | 121 | { |
979934da | 122 | uint16_t data; |
1da177e4 | 123 | |
979934da YY |
124 | data = icu2_read(offset); |
125 | data |= set; | |
126 | icu2_write(offset, data); | |
1da177e4 | 127 | |
979934da | 128 | return data; |
1da177e4 LT |
129 | } |
130 | ||
979934da | 131 | static inline uint16_t icu2_clear(uint8_t offset, uint16_t clear) |
1da177e4 | 132 | { |
979934da | 133 | uint16_t data; |
1da177e4 | 134 | |
979934da YY |
135 | data = icu2_read(offset); |
136 | data &= ~clear; | |
137 | icu2_write(offset, data); | |
1da177e4 | 138 | |
979934da | 139 | return data; |
1da177e4 LT |
140 | } |
141 | ||
1da177e4 LT |
142 | void vr41xx_enable_piuint(uint16_t mask) |
143 | { | |
fbaa4e2a | 144 | struct irq_desc *desc = irq_to_desc(PIU_IRQ); |
1da177e4 LT |
145 | unsigned long flags; |
146 | ||
10cc3529 RB |
147 | if (current_cpu_type() == CPU_VR4111 || |
148 | current_cpu_type() == CPU_VR4121) { | |
239007b8 | 149 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 150 | icu1_set(MPIUINTREG, mask); |
239007b8 | 151 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
152 | } |
153 | } | |
154 | ||
155 | EXPORT_SYMBOL(vr41xx_enable_piuint); | |
156 | ||
157 | void vr41xx_disable_piuint(uint16_t mask) | |
158 | { | |
fbaa4e2a | 159 | struct irq_desc *desc = irq_to_desc(PIU_IRQ); |
1da177e4 LT |
160 | unsigned long flags; |
161 | ||
10cc3529 RB |
162 | if (current_cpu_type() == CPU_VR4111 || |
163 | current_cpu_type() == CPU_VR4121) { | |
239007b8 | 164 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 165 | icu1_clear(MPIUINTREG, mask); |
239007b8 | 166 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
167 | } |
168 | } | |
169 | ||
170 | EXPORT_SYMBOL(vr41xx_disable_piuint); | |
171 | ||
172 | void vr41xx_enable_aiuint(uint16_t mask) | |
173 | { | |
fbaa4e2a | 174 | struct irq_desc *desc = irq_to_desc(AIU_IRQ); |
1da177e4 LT |
175 | unsigned long flags; |
176 | ||
10cc3529 RB |
177 | if (current_cpu_type() == CPU_VR4111 || |
178 | current_cpu_type() == CPU_VR4121) { | |
239007b8 | 179 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 180 | icu1_set(MAIUINTREG, mask); |
239007b8 | 181 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
182 | } |
183 | } | |
184 | ||
185 | EXPORT_SYMBOL(vr41xx_enable_aiuint); | |
186 | ||
187 | void vr41xx_disable_aiuint(uint16_t mask) | |
188 | { | |
fbaa4e2a | 189 | struct irq_desc *desc = irq_to_desc(AIU_IRQ); |
1da177e4 LT |
190 | unsigned long flags; |
191 | ||
10cc3529 RB |
192 | if (current_cpu_type() == CPU_VR4111 || |
193 | current_cpu_type() == CPU_VR4121) { | |
239007b8 | 194 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 195 | icu1_clear(MAIUINTREG, mask); |
239007b8 | 196 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
197 | } |
198 | } | |
199 | ||
200 | EXPORT_SYMBOL(vr41xx_disable_aiuint); | |
201 | ||
202 | void vr41xx_enable_kiuint(uint16_t mask) | |
203 | { | |
fbaa4e2a | 204 | struct irq_desc *desc = irq_to_desc(KIU_IRQ); |
1da177e4 LT |
205 | unsigned long flags; |
206 | ||
10cc3529 RB |
207 | if (current_cpu_type() == CPU_VR4111 || |
208 | current_cpu_type() == CPU_VR4121) { | |
239007b8 | 209 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 210 | icu1_set(MKIUINTREG, mask); |
239007b8 | 211 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
212 | } |
213 | } | |
214 | ||
215 | EXPORT_SYMBOL(vr41xx_enable_kiuint); | |
216 | ||
217 | void vr41xx_disable_kiuint(uint16_t mask) | |
218 | { | |
fbaa4e2a | 219 | struct irq_desc *desc = irq_to_desc(KIU_IRQ); |
1da177e4 LT |
220 | unsigned long flags; |
221 | ||
10cc3529 RB |
222 | if (current_cpu_type() == CPU_VR4111 || |
223 | current_cpu_type() == CPU_VR4121) { | |
239007b8 | 224 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 225 | icu1_clear(MKIUINTREG, mask); |
239007b8 | 226 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
227 | } |
228 | } | |
229 | ||
230 | EXPORT_SYMBOL(vr41xx_disable_kiuint); | |
231 | ||
9a0ad9e9 YY |
232 | void vr41xx_enable_macint(uint16_t mask) |
233 | { | |
fbaa4e2a | 234 | struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ); |
9a0ad9e9 YY |
235 | unsigned long flags; |
236 | ||
239007b8 | 237 | raw_spin_lock_irqsave(&desc->lock, flags); |
9a0ad9e9 | 238 | icu1_set(MMACINTREG, mask); |
239007b8 | 239 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
9a0ad9e9 YY |
240 | } |
241 | ||
242 | EXPORT_SYMBOL(vr41xx_enable_macint); | |
243 | ||
244 | void vr41xx_disable_macint(uint16_t mask) | |
245 | { | |
fbaa4e2a | 246 | struct irq_desc *desc = irq_to_desc(ETHERNET_IRQ); |
9a0ad9e9 YY |
247 | unsigned long flags; |
248 | ||
239007b8 | 249 | raw_spin_lock_irqsave(&desc->lock, flags); |
9a0ad9e9 | 250 | icu1_clear(MMACINTREG, mask); |
239007b8 | 251 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
9a0ad9e9 YY |
252 | } |
253 | ||
254 | EXPORT_SYMBOL(vr41xx_disable_macint); | |
255 | ||
1da177e4 LT |
256 | void vr41xx_enable_dsiuint(uint16_t mask) |
257 | { | |
fbaa4e2a | 258 | struct irq_desc *desc = irq_to_desc(DSIU_IRQ); |
1da177e4 LT |
259 | unsigned long flags; |
260 | ||
239007b8 | 261 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 262 | icu1_set(MDSIUINTREG, mask); |
239007b8 | 263 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
264 | } |
265 | ||
266 | EXPORT_SYMBOL(vr41xx_enable_dsiuint); | |
267 | ||
268 | void vr41xx_disable_dsiuint(uint16_t mask) | |
269 | { | |
fbaa4e2a | 270 | struct irq_desc *desc = irq_to_desc(DSIU_IRQ); |
1da177e4 LT |
271 | unsigned long flags; |
272 | ||
239007b8 | 273 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 274 | icu1_clear(MDSIUINTREG, mask); |
239007b8 | 275 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
276 | } |
277 | ||
278 | EXPORT_SYMBOL(vr41xx_disable_dsiuint); | |
279 | ||
280 | void vr41xx_enable_firint(uint16_t mask) | |
281 | { | |
fbaa4e2a | 282 | struct irq_desc *desc = irq_to_desc(FIR_IRQ); |
1da177e4 LT |
283 | unsigned long flags; |
284 | ||
239007b8 | 285 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 286 | icu2_set(MFIRINTREG, mask); |
239007b8 | 287 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
288 | } |
289 | ||
290 | EXPORT_SYMBOL(vr41xx_enable_firint); | |
291 | ||
292 | void vr41xx_disable_firint(uint16_t mask) | |
293 | { | |
fbaa4e2a | 294 | struct irq_desc *desc = irq_to_desc(FIR_IRQ); |
1da177e4 LT |
295 | unsigned long flags; |
296 | ||
239007b8 | 297 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 298 | icu2_clear(MFIRINTREG, mask); |
239007b8 | 299 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
300 | } |
301 | ||
302 | EXPORT_SYMBOL(vr41xx_disable_firint); | |
303 | ||
304 | void vr41xx_enable_pciint(void) | |
305 | { | |
fbaa4e2a | 306 | struct irq_desc *desc = irq_to_desc(PCI_IRQ); |
1da177e4 LT |
307 | unsigned long flags; |
308 | ||
10cc3529 RB |
309 | if (current_cpu_type() == CPU_VR4122 || |
310 | current_cpu_type() == CPU_VR4131 || | |
311 | current_cpu_type() == CPU_VR4133) { | |
239007b8 | 312 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 313 | icu2_write(MPCIINTREG, PCIINT0); |
239007b8 | 314 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
315 | } |
316 | } | |
317 | ||
318 | EXPORT_SYMBOL(vr41xx_enable_pciint); | |
319 | ||
320 | void vr41xx_disable_pciint(void) | |
321 | { | |
fbaa4e2a | 322 | struct irq_desc *desc = irq_to_desc(PCI_IRQ); |
1da177e4 LT |
323 | unsigned long flags; |
324 | ||
10cc3529 RB |
325 | if (current_cpu_type() == CPU_VR4122 || |
326 | current_cpu_type() == CPU_VR4131 || | |
327 | current_cpu_type() == CPU_VR4133) { | |
239007b8 | 328 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 329 | icu2_write(MPCIINTREG, 0); |
239007b8 | 330 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
331 | } |
332 | } | |
333 | ||
334 | EXPORT_SYMBOL(vr41xx_disable_pciint); | |
335 | ||
336 | void vr41xx_enable_scuint(void) | |
337 | { | |
fbaa4e2a | 338 | struct irq_desc *desc = irq_to_desc(SCU_IRQ); |
1da177e4 LT |
339 | unsigned long flags; |
340 | ||
10cc3529 RB |
341 | if (current_cpu_type() == CPU_VR4122 || |
342 | current_cpu_type() == CPU_VR4131 || | |
343 | current_cpu_type() == CPU_VR4133) { | |
239007b8 | 344 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 345 | icu2_write(MSCUINTREG, SCUINT0); |
239007b8 | 346 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
347 | } |
348 | } | |
349 | ||
350 | EXPORT_SYMBOL(vr41xx_enable_scuint); | |
351 | ||
352 | void vr41xx_disable_scuint(void) | |
353 | { | |
fbaa4e2a | 354 | struct irq_desc *desc = irq_to_desc(SCU_IRQ); |
1da177e4 LT |
355 | unsigned long flags; |
356 | ||
10cc3529 RB |
357 | if (current_cpu_type() == CPU_VR4122 || |
358 | current_cpu_type() == CPU_VR4131 || | |
359 | current_cpu_type() == CPU_VR4133) { | |
239007b8 | 360 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 361 | icu2_write(MSCUINTREG, 0); |
239007b8 | 362 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
363 | } |
364 | } | |
365 | ||
366 | EXPORT_SYMBOL(vr41xx_disable_scuint); | |
367 | ||
368 | void vr41xx_enable_csiint(uint16_t mask) | |
369 | { | |
fbaa4e2a | 370 | struct irq_desc *desc = irq_to_desc(CSI_IRQ); |
1da177e4 LT |
371 | unsigned long flags; |
372 | ||
10cc3529 RB |
373 | if (current_cpu_type() == CPU_VR4122 || |
374 | current_cpu_type() == CPU_VR4131 || | |
375 | current_cpu_type() == CPU_VR4133) { | |
239007b8 | 376 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 377 | icu2_set(MCSIINTREG, mask); |
239007b8 | 378 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
379 | } |
380 | } | |
381 | ||
382 | EXPORT_SYMBOL(vr41xx_enable_csiint); | |
383 | ||
384 | void vr41xx_disable_csiint(uint16_t mask) | |
385 | { | |
fbaa4e2a | 386 | struct irq_desc *desc = irq_to_desc(CSI_IRQ); |
1da177e4 LT |
387 | unsigned long flags; |
388 | ||
10cc3529 RB |
389 | if (current_cpu_type() == CPU_VR4122 || |
390 | current_cpu_type() == CPU_VR4131 || | |
391 | current_cpu_type() == CPU_VR4133) { | |
239007b8 | 392 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 393 | icu2_clear(MCSIINTREG, mask); |
239007b8 | 394 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
395 | } |
396 | } | |
397 | ||
398 | EXPORT_SYMBOL(vr41xx_disable_csiint); | |
399 | ||
400 | void vr41xx_enable_bcuint(void) | |
401 | { | |
fbaa4e2a | 402 | struct irq_desc *desc = irq_to_desc(BCU_IRQ); |
1da177e4 LT |
403 | unsigned long flags; |
404 | ||
10cc3529 RB |
405 | if (current_cpu_type() == CPU_VR4122 || |
406 | current_cpu_type() == CPU_VR4131 || | |
407 | current_cpu_type() == CPU_VR4133) { | |
239007b8 | 408 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 409 | icu2_write(MBCUINTREG, BCUINTR); |
239007b8 | 410 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
411 | } |
412 | } | |
413 | ||
414 | EXPORT_SYMBOL(vr41xx_enable_bcuint); | |
415 | ||
416 | void vr41xx_disable_bcuint(void) | |
417 | { | |
fbaa4e2a | 418 | struct irq_desc *desc = irq_to_desc(BCU_IRQ); |
1da177e4 LT |
419 | unsigned long flags; |
420 | ||
10cc3529 RB |
421 | if (current_cpu_type() == CPU_VR4122 || |
422 | current_cpu_type() == CPU_VR4131 || | |
423 | current_cpu_type() == CPU_VR4133) { | |
239007b8 | 424 | raw_spin_lock_irqsave(&desc->lock, flags); |
979934da | 425 | icu2_write(MBCUINTREG, 0); |
239007b8 | 426 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 LT |
427 | } |
428 | } | |
429 | ||
430 | EXPORT_SYMBOL(vr41xx_disable_bcuint); | |
431 | ||
fbaa4e2a | 432 | static void disable_sysint1_irq(struct irq_data *d) |
1da177e4 | 433 | { |
fbaa4e2a | 434 | icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq)); |
1da177e4 LT |
435 | } |
436 | ||
fbaa4e2a | 437 | static void enable_sysint1_irq(struct irq_data *d) |
1da177e4 | 438 | { |
fbaa4e2a | 439 | icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(d->irq)); |
1da177e4 LT |
440 | } |
441 | ||
94dee171 | 442 | static struct irq_chip sysint1_irq_type = { |
70d21cde | 443 | .name = "SYSINT1", |
fbaa4e2a TG |
444 | .irq_mask = disable_sysint1_irq, |
445 | .irq_unmask = enable_sysint1_irq, | |
1da177e4 LT |
446 | }; |
447 | ||
fbaa4e2a | 448 | static void disable_sysint2_irq(struct irq_data *d) |
1da177e4 | 449 | { |
fbaa4e2a | 450 | icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq)); |
1da177e4 LT |
451 | } |
452 | ||
fbaa4e2a | 453 | static void enable_sysint2_irq(struct irq_data *d) |
1da177e4 | 454 | { |
fbaa4e2a | 455 | icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(d->irq)); |
1da177e4 LT |
456 | } |
457 | ||
94dee171 | 458 | static struct irq_chip sysint2_irq_type = { |
70d21cde | 459 | .name = "SYSINT2", |
fbaa4e2a TG |
460 | .irq_mask = disable_sysint2_irq, |
461 | .irq_unmask = enable_sysint2_irq, | |
1da177e4 LT |
462 | }; |
463 | ||
1da177e4 LT |
464 | static inline int set_sysint1_assign(unsigned int irq, unsigned char assign) |
465 | { | |
fbaa4e2a | 466 | struct irq_desc *desc = irq_to_desc(irq); |
1da177e4 LT |
467 | uint16_t intassign0, intassign1; |
468 | unsigned int pin; | |
469 | ||
470 | pin = SYSINT1_IRQ_TO_PIN(irq); | |
471 | ||
239007b8 | 472 | raw_spin_lock_irq(&desc->lock); |
1da177e4 | 473 | |
979934da YY |
474 | intassign0 = icu1_read(INTASSIGN0); |
475 | intassign1 = icu1_read(INTASSIGN1); | |
1da177e4 LT |
476 | |
477 | switch (pin) { | |
478 | case 0: | |
479 | intassign0 &= ~INTASSIGN_MASK; | |
480 | intassign0 |= (uint16_t)assign; | |
481 | break; | |
482 | case 1: | |
483 | intassign0 &= ~(INTASSIGN_MASK << 3); | |
484 | intassign0 |= (uint16_t)assign << 3; | |
485 | break; | |
486 | case 2: | |
487 | intassign0 &= ~(INTASSIGN_MASK << 6); | |
488 | intassign0 |= (uint16_t)assign << 6; | |
489 | break; | |
490 | case 3: | |
491 | intassign0 &= ~(INTASSIGN_MASK << 9); | |
492 | intassign0 |= (uint16_t)assign << 9; | |
493 | break; | |
494 | case 8: | |
495 | intassign0 &= ~(INTASSIGN_MASK << 12); | |
496 | intassign0 |= (uint16_t)assign << 12; | |
497 | break; | |
498 | case 9: | |
499 | intassign1 &= ~INTASSIGN_MASK; | |
500 | intassign1 |= (uint16_t)assign; | |
501 | break; | |
502 | case 11: | |
503 | intassign1 &= ~(INTASSIGN_MASK << 6); | |
504 | intassign1 |= (uint16_t)assign << 6; | |
505 | break; | |
506 | case 12: | |
507 | intassign1 &= ~(INTASSIGN_MASK << 9); | |
508 | intassign1 |= (uint16_t)assign << 9; | |
509 | break; | |
510 | default: | |
239007b8 | 511 | raw_spin_unlock_irq(&desc->lock); |
1da177e4 LT |
512 | return -EINVAL; |
513 | } | |
514 | ||
515 | sysint1_assign[pin] = assign; | |
979934da YY |
516 | icu1_write(INTASSIGN0, intassign0); |
517 | icu1_write(INTASSIGN1, intassign1); | |
1da177e4 | 518 | |
239007b8 | 519 | raw_spin_unlock_irq(&desc->lock); |
1da177e4 LT |
520 | |
521 | return 0; | |
522 | } | |
523 | ||
524 | static inline int set_sysint2_assign(unsigned int irq, unsigned char assign) | |
525 | { | |
fbaa4e2a | 526 | struct irq_desc *desc = irq_to_desc(irq); |
1da177e4 LT |
527 | uint16_t intassign2, intassign3; |
528 | unsigned int pin; | |
529 | ||
530 | pin = SYSINT2_IRQ_TO_PIN(irq); | |
531 | ||
239007b8 | 532 | raw_spin_lock_irq(&desc->lock); |
1da177e4 | 533 | |
979934da YY |
534 | intassign2 = icu1_read(INTASSIGN2); |
535 | intassign3 = icu1_read(INTASSIGN3); | |
1da177e4 LT |
536 | |
537 | switch (pin) { | |
538 | case 0: | |
539 | intassign2 &= ~INTASSIGN_MASK; | |
540 | intassign2 |= (uint16_t)assign; | |
541 | break; | |
542 | case 1: | |
543 | intassign2 &= ~(INTASSIGN_MASK << 3); | |
544 | intassign2 |= (uint16_t)assign << 3; | |
545 | break; | |
546 | case 3: | |
547 | intassign2 &= ~(INTASSIGN_MASK << 6); | |
548 | intassign2 |= (uint16_t)assign << 6; | |
549 | break; | |
550 | case 4: | |
551 | intassign2 &= ~(INTASSIGN_MASK << 9); | |
552 | intassign2 |= (uint16_t)assign << 9; | |
553 | break; | |
554 | case 5: | |
555 | intassign2 &= ~(INTASSIGN_MASK << 12); | |
556 | intassign2 |= (uint16_t)assign << 12; | |
557 | break; | |
558 | case 6: | |
559 | intassign3 &= ~INTASSIGN_MASK; | |
560 | intassign3 |= (uint16_t)assign; | |
561 | break; | |
562 | case 7: | |
563 | intassign3 &= ~(INTASSIGN_MASK << 3); | |
564 | intassign3 |= (uint16_t)assign << 3; | |
565 | break; | |
566 | case 8: | |
567 | intassign3 &= ~(INTASSIGN_MASK << 6); | |
568 | intassign3 |= (uint16_t)assign << 6; | |
569 | break; | |
570 | case 9: | |
571 | intassign3 &= ~(INTASSIGN_MASK << 9); | |
572 | intassign3 |= (uint16_t)assign << 9; | |
573 | break; | |
574 | case 10: | |
575 | intassign3 &= ~(INTASSIGN_MASK << 12); | |
576 | intassign3 |= (uint16_t)assign << 12; | |
577 | break; | |
578 | default: | |
239007b8 | 579 | raw_spin_unlock_irq(&desc->lock); |
1da177e4 LT |
580 | return -EINVAL; |
581 | } | |
582 | ||
583 | sysint2_assign[pin] = assign; | |
979934da YY |
584 | icu1_write(INTASSIGN2, intassign2); |
585 | icu1_write(INTASSIGN3, intassign3); | |
1da177e4 | 586 | |
239007b8 | 587 | raw_spin_unlock_irq(&desc->lock); |
1da177e4 LT |
588 | |
589 | return 0; | |
590 | } | |
591 | ||
592 | int vr41xx_set_intassign(unsigned int irq, unsigned char intassign) | |
593 | { | |
594 | int retval = -EINVAL; | |
595 | ||
10cc3529 | 596 | if (current_cpu_type() != CPU_VR4133) |
1da177e4 LT |
597 | return -EINVAL; |
598 | ||
599 | if (intassign > INTASSIGN_MAX) | |
600 | return -EINVAL; | |
601 | ||
602 | if (irq >= SYSINT1_IRQ_BASE && irq <= SYSINT1_IRQ_LAST) | |
603 | retval = set_sysint1_assign(irq, intassign); | |
604 | else if (irq >= SYSINT2_IRQ_BASE && irq <= SYSINT2_IRQ_LAST) | |
605 | retval = set_sysint2_assign(irq, intassign); | |
606 | ||
607 | return retval; | |
608 | } | |
609 | ||
610 | EXPORT_SYMBOL(vr41xx_set_intassign); | |
611 | ||
937a8015 | 612 | static int icu_get_irq(unsigned int irq) |
1da177e4 LT |
613 | { |
614 | uint16_t pend1, pend2; | |
615 | uint16_t mask1, mask2; | |
616 | int i; | |
617 | ||
979934da YY |
618 | pend1 = icu1_read(SYSINT1REG); |
619 | mask1 = icu1_read(MSYSINT1REG); | |
1da177e4 | 620 | |
979934da YY |
621 | pend2 = icu2_read(SYSINT2REG); |
622 | mask2 = icu2_read(MSYSINT2REG); | |
1da177e4 LT |
623 | |
624 | mask1 &= pend1; | |
625 | mask2 &= pend2; | |
626 | ||
627 | if (mask1) { | |
628 | for (i = 0; i < 16; i++) { | |
979934da YY |
629 | if (irq == INT_TO_IRQ(sysint1_assign[i]) && (mask1 & (1 << i))) |
630 | return SYSINT1_IRQ(i); | |
1da177e4 LT |
631 | } |
632 | } | |
633 | ||
634 | if (mask2) { | |
635 | for (i = 0; i < 16; i++) { | |
979934da YY |
636 | if (irq == INT_TO_IRQ(sysint2_assign[i]) && (mask2 & (1 << i))) |
637 | return SYSINT2_IRQ(i); | |
1da177e4 LT |
638 | } |
639 | } | |
640 | ||
641 | printk(KERN_ERR "spurious ICU interrupt: %04x,%04x\n", pend1, pend2); | |
642 | ||
643 | atomic_inc(&irq_err_count); | |
1da177e4 | 644 | |
979934da YY |
645 | return -1; |
646 | } | |
1da177e4 LT |
647 | |
648 | static int __init vr41xx_icu_init(void) | |
649 | { | |
979934da YY |
650 | unsigned long icu1_start, icu2_start; |
651 | int i; | |
652 | ||
10cc3529 | 653 | switch (current_cpu_type()) { |
1da177e4 LT |
654 | case CPU_VR4111: |
655 | case CPU_VR4121: | |
979934da YY |
656 | icu1_start = ICU1_TYPE1_BASE; |
657 | icu2_start = ICU2_TYPE1_BASE; | |
1da177e4 LT |
658 | break; |
659 | case CPU_VR4122: | |
660 | case CPU_VR4131: | |
661 | case CPU_VR4133: | |
979934da YY |
662 | icu1_start = ICU1_TYPE2_BASE; |
663 | icu2_start = ICU2_TYPE2_BASE; | |
1da177e4 LT |
664 | break; |
665 | default: | |
666 | printk(KERN_ERR "ICU: Unexpected CPU of NEC VR4100 series\n"); | |
979934da | 667 | return -ENODEV; |
1da177e4 LT |
668 | } |
669 | ||
979934da YY |
670 | if (request_mem_region(icu1_start, ICU1_SIZE, "ICU") == NULL) |
671 | return -EBUSY; | |
1da177e4 | 672 | |
979934da YY |
673 | if (request_mem_region(icu2_start, ICU2_SIZE, "ICU") == NULL) { |
674 | release_mem_region(icu1_start, ICU1_SIZE); | |
675 | return -EBUSY; | |
676 | } | |
1da177e4 | 677 | |
979934da YY |
678 | icu1_base = ioremap(icu1_start, ICU1_SIZE); |
679 | if (icu1_base == NULL) { | |
680 | release_mem_region(icu1_start, ICU1_SIZE); | |
681 | release_mem_region(icu2_start, ICU2_SIZE); | |
682 | return -ENOMEM; | |
683 | } | |
1da177e4 | 684 | |
979934da YY |
685 | icu2_base = ioremap(icu2_start, ICU2_SIZE); |
686 | if (icu2_base == NULL) { | |
687 | iounmap(icu1_base); | |
688 | release_mem_region(icu1_start, ICU1_SIZE); | |
689 | release_mem_region(icu2_start, ICU2_SIZE); | |
690 | return -ENOMEM; | |
691 | } | |
1da177e4 | 692 | |
979934da YY |
693 | icu1_write(MSYSINT1REG, 0); |
694 | icu1_write(MGIUINTLREG, 0xffff); | |
1da177e4 | 695 | |
979934da YY |
696 | icu2_write(MSYSINT2REG, 0); |
697 | icu2_write(MGIUINTHREG, 0xffff); | |
1da177e4 LT |
698 | |
699 | for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) | |
e4ec7989 | 700 | irq_set_chip_and_handler(i, &sysint1_irq_type, |
1417836e | 701 | handle_level_irq); |
1da177e4 LT |
702 | |
703 | for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) | |
e4ec7989 | 704 | irq_set_chip_and_handler(i, &sysint2_irq_type, |
1417836e | 705 | handle_level_irq); |
1da177e4 | 706 | |
979934da YY |
707 | cascade_irq(INT0_IRQ, icu_get_irq); |
708 | cascade_irq(INT1_IRQ, icu_get_irq); | |
709 | cascade_irq(INT2_IRQ, icu_get_irq); | |
710 | cascade_irq(INT3_IRQ, icu_get_irq); | |
711 | cascade_irq(INT4_IRQ, icu_get_irq); | |
1da177e4 | 712 | |
979934da | 713 | return 0; |
1da177e4 | 714 | } |
979934da YY |
715 | |
716 | core_initcall(vr41xx_icu_init); |