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[MIPS] TXx9: Reorganize PCI code
[linux-2.6-block.git] / arch / mips / txx9 / jmr3927 / setup.c
CommitLineData
832348ff 1/*
1da177e4
LT		 2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
832348ff
RB		 22 * Copyright 2001 MontaVista Software Inc.
23 * Author: MontaVista Software, Inc.
24 * ahennessy@mvista.com
25 *
26 * Copyright (C) 2000-2001 Toshiba Corporation
27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
1da177e4
LT		 28 */
29
1da177e4
LT		 30#include <linux/init.h>
31#include <linux/kernel.h>
1da177e4 32#include <linux/types.h>
1da177e4 33#include <linux/ioport.h>
1da177e4 34#include <linux/delay.h>
fcdb27ad 35#include <linux/pm.h>
a0574e04 36#include <linux/platform_device.h>
2064ba23 37#include <linux/clk.h>
1bd0962e 38#include <linux/gpio.h>
5eaf7a21 39#ifdef CONFIG_SERIAL_TXX9
5eaf7a21
RB		 40#include <linux/serial_core.h>
41#endif
1da177e4 42
229f773e 43#include <asm/txx9tmr.h>
1bd0962e 44#include <asm/txx9pio.h>
1da177e4 45#include <asm/reboot.h>
89d63fe1 46#include <asm/txx9/pci.h>
22b1d707 47#include <asm/txx9/jmr3927.h>
1da177e4 48#include <asm/mipsregs.h>
1da177e4 49
2127435e 50extern void puts(const char *cp);
380b9253 51
1da177e4 52/* don't enable - see errata */
2127435e 53static int jmr3927_ccfg_toeon;
1da177e4
LT		 54
55static inline void do_reset(void)
56{
1da177e4
LT		 57#if 1 /* Resetting PCI bus */
58 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
59 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
60 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
61 mdelay(1);
62 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
63#endif
64 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
65}
66
67static void jmr3927_machine_restart(char *command)
68{
69 local_irq_disable();
70 puts("Rebooting...");
71 do_reset();
72}
73
74static void jmr3927_machine_halt(void)
75{
76 puts("JMR-TX3927 halted.\n");
77 while (1);
78}
79
80static void jmr3927_machine_power_off(void)
81{
82 puts("JMR-TX3927 halted. Please turn off the power.\n");
83 while (1);
84}
85
4b550488 86void __init plat_time_init(void)
1da177e4 87{
229f773e
AN		 88 txx9_clockevent_init(TX3927_TMR_REG(0),
89 TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
90 JMR3927_IMCLK);
91 txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
1da177e4
LT		 92}
93
1da177e4
LT		 94#define DO_WRITE_THROUGH
95#define DO_ENABLE_CACHE
96
97extern char * __init prom_getcmdline(void);
98static void jmr3927_board_init(void);
1da177e4 99
2925aba4 100void __init plat_mem_setup(void)
1da177e4
LT		 101{
102 char *argptr;
103
104 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
105
1da177e4
LT		 106 _machine_restart = jmr3927_machine_restart;
107 _machine_halt = jmr3927_machine_halt;
fcdb27ad 108 pm_power_off = jmr3927_machine_power_off;
1da177e4
LT		 109
110 /*
111 * IO/MEM resources.
112 */
89d63fe1
AN		 113 ioport_resource.start = 0;
114 ioport_resource.end = 0xffffffff;
5eaf7a21
RB		 115 iomem_resource.start = 0;
116 iomem_resource.end = 0xffffffff;
1da177e4
LT		 117
118 /* Reboot on panic */
119 panic_timeout = 180;
120
1da177e4
LT		 121 /* cache setup */
122 {
123 unsigned int conf;
124#ifdef DO_ENABLE_CACHE
125 int mips_ic_disable = 0, mips_dc_disable = 0;
126#else
127 int mips_ic_disable = 1, mips_dc_disable = 1;
128#endif
129#ifdef DO_WRITE_THROUGH
130 int mips_config_cwfon = 0;
131 int mips_config_wbon = 0;
132#else
133 int mips_config_cwfon = 1;
134 int mips_config_wbon = 1;
135#endif
136
137 conf = read_c0_conf();
138 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
139 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
140 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
141 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
142 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
143
144 write_c0_conf(conf);
145 write_c0_cache(0);
146 }
1da177e4
LT		 147
148 /* initialize board */
149 jmr3927_board_init();
150
151 argptr = prom_getcmdline();
152
2127435e
AN		 153 if ((argptr = strstr(argptr, "toeon")) != NULL)
154 jmr3927_ccfg_toeon = 1;
1da177e4
LT		 155 argptr = prom_getcmdline();
156 if ((argptr = strstr(argptr, "ip=")) == NULL) {
157 argptr = prom_getcmdline();
158 strcat(argptr, " ip=bootp");
159 }
160
5eaf7a21
RB		 161#ifdef CONFIG_SERIAL_TXX9
162 {
163 extern int early_serial_txx9_setup(struct uart_port *port);
164 int i;
165 struct uart_port req;
166 for(i = 0; i < 2; i++) {
167 memset(&req, 0, sizeof(req));
168 req.line = i;
169 req.iotype = UPIO_MEM;
2127435e 170 req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
5eaf7a21
RB		 171 req.mapbase = TX3927_SIO_REG(i);
172 req.irq = i == 0 ?
173 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
174 if (i == 0)
175 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
176 req.uartclk = JMR3927_IMCLK;
177 early_serial_txx9_setup(&req);
178 }
179 }
180#ifdef CONFIG_SERIAL_TXX9_CONSOLE
1da177e4
LT		 181 argptr = prom_getcmdline();
182 if ((argptr = strstr(argptr, "console=")) == NULL) {
183 argptr = prom_getcmdline();
184 strcat(argptr, " console=ttyS1,115200");
185 }
186#endif
5eaf7a21 187#endif
1da177e4
LT		 188}
189
1da177e4
LT		 190static void tx3927_setup(void);
191
89d63fe1
AN		 192static void __init jmr3927_pci_setup(void)
193{
194#ifdef CONFIG_PCI
195 int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB);
196 struct pci_controller *c;
197
198 c = txx9_alloc_pci_controller(&txx9_primary_pcic,
199 JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE,
200 JMR3927_PCIIO, JMR3927_PCIIO_SIZE);
201 register_pci_controller(c);
202 if (!extarb) {
203 /* Reset PCI Bus */
204 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
205 udelay(100);
206 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
207 JMR3927_IOC_RESET_ADDR);
208 udelay(100);
209 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
210 }
211 tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb);
212#endif /* CONFIG_PCI */
213}
214
1da177e4
LT		 215static void __init jmr3927_board_init(void)
216{
1da177e4 217 tx3927_setup();
89d63fe1 218 jmr3927_pci_setup();
1da177e4 219
1da177e4
LT		 220 /* SIO0 DTR on */
221 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
222
223 jmr3927_led_set(0);
224
1da177e4
LT		 225 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
226 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
227 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
228 jmr3927_dipsw1(), jmr3927_dipsw2(),
229 jmr3927_dipsw3(), jmr3927_dipsw4());
1da177e4
LT		 230}
231
2127435e 232static void __init tx3927_setup(void)
1da177e4
LT		 233{
234 int i;
235
236 /* SDRAMC are configured by PROM */
237
238 /* ROMC */
239 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
240 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
241 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
242 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
243
244 /* CCFG */
245 /* enable Timeout BusError */
246 if (jmr3927_ccfg_toeon)
247 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
248
249 /* clear BusErrorOnWrite flag */
250 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
251 /* Disable PCI snoop */
252 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
2064ba23
AN		 253 /* do reset on watchdog */
254 tx3927_ccfgptr->ccfg |= TX3927_CCFG_WR;
1da177e4
LT		 255
256#ifdef DO_WRITE_THROUGH
257 /* Enable PCI SNOOP - with write through only */
258 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
259#endif
260
261 /* Pin selection */
262 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
263 tx3927_ccfgptr->pcfg |=
264 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
265 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
266
267 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
268 tx3927_ccfgptr->crir,
269 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
270
1da177e4 271 /* TMR */
229f773e
AN		 272 for (i = 0; i < TX3927_NR_TMR; i++)
273 txx9_tmr_init(TX3927_TMR_REG(i));
1da177e4
LT		 274
275 /* DMA */
276 tx3927_dmaptr->mcr = 0;
25b8ac3b 277 for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
1da177e4
LT		 278 /* reset channel */
279 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
280 tx3927_dmaptr->ch[i].ccr = 0;
281 }
282 /* enable DMA */
283#ifdef __BIG_ENDIAN
284 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
285#else
286 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
287#endif
288
1da177e4
LT		 289 /* PIO */
290 /* PIO[15:12] connected to LEDs */
1bd0962e
AN		 291 __raw_writel(0x0000f000, &tx3927_pioptr->dir);
292 __raw_writel(0, &tx3927_pioptr->maskcpu);
293 __raw_writel(0, &tx3927_pioptr->maskext);
294 txx9_gpio_init(TX3927_PIO_REG, 0, 16);
295 gpio_request(11, "dipsw1");
296 gpio_request(10, "dipsw2");
1da177e4
LT		 297 {
298 unsigned int conf;
299
300 conf = read_c0_conf();
301 if (!(conf & TX39_CONF_ICE))
302 printk("TX3927 I-Cache disabled.\n");
303 if (!(conf & TX39_CONF_DCE))
304 printk("TX3927 D-Cache disabled.\n");
305 else if (!(conf & TX39_CONF_WBON))
306 printk("TX3927 D-Cache WriteThrough.\n");
307 else if (!(conf & TX39_CONF_CWFON))
308 printk("TX3927 D-Cache WriteBack.\n");
309 else
310 printk("TX3927 D-Cache WriteBack (CWF) .\n");
311 }
312}
a0574e04
AN		 313
314/* This trick makes rtc-ds1742 driver usable as is. */
315unsigned long __swizzle_addr_b(unsigned long port)
316{
317 if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
318 return port;
319 port = (port & 0xffff0000) | (port & 0x7fff << 1);
320#ifdef __BIG_ENDIAN
321 return port;
322#else
323 return port | 1;
324#endif
325}
326EXPORT_SYMBOL(__swizzle_addr_b);
327
328static int __init jmr3927_rtc_init(void)
329{
4614c326 330 static struct resource __initdata res = {
a0574e04
AN		 331 .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
332 .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
333 .flags = IORESOURCE_MEM,
334 };
335 struct platform_device *dev;
a95e23a2 336 dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
a0574e04
AN		 337 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
338}
339device_initcall(jmr3927_rtc_init);
2064ba23
AN		 340
341/* Watchdog support */
342
343static int __init txx9_wdt_init(unsigned long base)
344{
345 struct resource res = {
346 .start = base,
347 .end = base + 0x100 - 1,
348 .flags = IORESOURCE_MEM,
349 };
350 struct platform_device *dev =
351 platform_device_register_simple("txx9wdt", -1, &res, 1);
352 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
353}
354
355static int __init jmr3927_wdt_init(void)
356{
357 return txx9_wdt_init(TX3927_TMR_REG(2));
358}
359device_initcall(jmr3927_wdt_init);
360
361/* Minimum CLK support */
362
363struct clk *clk_get(struct device *dev, const char *id)
364{
365 if (!strcmp(id, "imbus_clk"))
366 return (struct clk *)JMR3927_IMCLK;
367 return ERR_PTR(-ENOENT);
368}
369EXPORT_SYMBOL(clk_get);
370
371int clk_enable(struct clk *clk)
372{
373 return 0;
374}
375EXPORT_SYMBOL(clk_enable);
376
377void clk_disable(struct clk *clk)
378{
379}
380EXPORT_SYMBOL(clk_disable);
381
382unsigned long clk_get_rate(struct clk *clk)
383{
384 return (unsigned long)clk;
385}
386EXPORT_SYMBOL(clk_get_rate);
387
388void clk_put(struct clk *clk)
389{
390}
391EXPORT_SYMBOL(clk_put);
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