[linux-2.6-block.git] / arch / mips / txx9 / jmr3927 / irq.c

/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              ahennessy@mvista.com
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000-2001 Toshiba Corporation
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/init.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/txx9/generic.h>
#include <asm/txx9/jmr3927.h>

#if JMR3927_IRQ_END > NR_IRQS
#error JMR3927_IRQ_END > NR_IRQS
#endif

/*
 * CP0_STATUS is a thread's resource (saved/restored on context switch).
 * So disable_irq/enable_irq MUST handle IOC/IRC registers.
 */
static void mask_irq_ioc(struct irq_data *d)
{
	/* 0: mask */
	unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
	unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	unsigned int bit = 1 << irq_nr;
	jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
	/* flush write buffer */
	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}
static void unmask_irq_ioc(struct irq_data *d)
{
	/* 0: mask */
	unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
	unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	unsigned int bit = 1 << irq_nr;
	jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
	/* flush write buffer */
	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}

static int jmr3927_ioc_irqroute(void)
{
	unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
	int i;

	for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
		if (istat & (1 << i))
			return JMR3927_IRQ_IOC + i;
	}
	return -1;
}

static int jmr3927_irq_dispatch(int pending)
{
	int irq;

	if ((pending & CAUSEF_IP7) == 0)
		return -1;
	irq = (pending >> CAUSEB_IP2) & 0x0f;
	irq += JMR3927_IRQ_IRC;
	if (irq == JMR3927_IRQ_IOCINT)
		irq = jmr3927_ioc_irqroute();
	return irq;
}

static struct irq_chip jmr3927_irq_ioc = {
	.name = "jmr3927_ioc",
	.irq_mask = mask_irq_ioc,
	.irq_unmask = unmask_irq_ioc,
};

void __init jmr3927_irq_setup(void)
{
	int i;

	txx9_irq_dispatch = jmr3927_irq_dispatch;
	/* Now, interrupt control disabled, */
	/* all IRC interrupts are masked, */
	/* all IRC interrupt mode are Low Active. */

	/* mask all IOC interrupts */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
	/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
	jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);

	/* clear PCI Soft interrupts */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
	/* clear PCI Reset interrupts */
	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);

	tx3927_irq_init();
	for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
		set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);

	/* setup IOC interrupt 1 (PCI, MODEM) */
	set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright 2001 MontaVista Software Inc.
	3	* Author: MontaVista Software, Inc.
	4	* ahennessy@mvista.com
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*
	10	* Copyright (C) 2000-2001 Toshiba Corporation
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License as published by the
	14	* Free Software Foundation; either version 2 of the License, or (at your
	15	* option) any later version.
	16	*
	17	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	18	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	19	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	20	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	23	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	24	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	27	*
	28	* You should have received a copy of the GNU General Public License along
	29	* with this program; if not, write to the Free Software Foundation, Inc.,
	30	* 675 Mass Ave, Cambridge, MA 02139, USA.
	31	*/
1da177e4	32	#include <linux/init.h>
1da177e4 LT	33	#include <linux/types.h>
1da177e4 LT	34	#include <linux/interrupt.h>
ca4d3e67	35	#include <linux/irq.h>
1da177e4 LT	36
	37	#include <asm/io.h>
	38	#include <asm/mipsregs.h>
edcaf1a6	39	#include <asm/txx9/generic.h>
22b1d707	40	#include <asm/txx9/jmr3927.h>
1da177e4 LT	41
	42	#if JMR3927_IRQ_END > NR_IRQS
	43	#error JMR3927_IRQ_END > NR_IRQS
	44	#endif
	45
1da177e4 LT	46	/*
1da177e4 LT	47	* CP0_STATUS is a thread's resource (saved/restored on context switch).
2127435e	48	* So disable_irq/enable_irq MUST handle IOC/IRC registers.
1da177e4	49	*/
d7ae7c71	50	static void mask_irq_ioc(struct irq_data *d)
1da177e4 LT	51	{
1da177e4 LT	52	/* 0: mask */
d7ae7c71	53	unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
1da177e4 LT	54	unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	55	unsigned int bit = 1 << irq_nr;
	56	jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
	57	/* flush write buffer */
	58	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
	59	}
d7ae7c71	60	static void unmask_irq_ioc(struct irq_data *d)
1da177e4 LT	61	{
1da177e4 LT	62	/* 0: mask */
d7ae7c71	63	unsigned int irq_nr = d->irq - JMR3927_IRQ_IOC;
1da177e4 LT	64	unsigned char imask = jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
	65	unsigned int bit = 1 << irq_nr;
	66	jmr3927_ioc_reg_out(imask \| bit, JMR3927_IOC_INTM_ADDR);
	67	/* flush write buffer */
	68	(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
	69	}
	70
edcaf1a6	71	static int jmr3927_ioc_irqroute(void)
1da177e4 LT	72	{
	73	unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
	74	int i;
	75
	76	for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
edcaf1a6 AN	77	if (istat & (1 << i))
edcaf1a6 AN	78	return JMR3927_IRQ_IOC + i;
1da177e4	79	}
edcaf1a6	80	return -1;
1da177e4 LT	81	}
1da177e4 LT	82
edcaf1a6 AN	83	static int jmr3927_irq_dispatch(int pending)
	84	{
	85	int irq;
	86
	87	if ((pending & CAUSEF_IP7) == 0)
	88	return -1;
	89	irq = (pending >> CAUSEB_IP2) & 0x0f;
	90	irq += JMR3927_IRQ_IRC;
	91	if (irq == JMR3927_IRQ_IOCINT)
	92	irq = jmr3927_ioc_irqroute();
	93	return irq;
	94	}
1da177e4	95
f6727fb8 AN	96	static struct irq_chip jmr3927_irq_ioc = {
f6727fb8 AN	97	.name = "jmr3927_ioc",
d7ae7c71 TG	98	.irq_mask = mask_irq_ioc,
d7ae7c71 TG	99	.irq_unmask = unmask_irq_ioc,
f6727fb8	100	};
1da177e4	101
edcaf1a6	102	void __init jmr3927_irq_setup(void)
1da177e4	103	{
f6727fb8 AN	104	int i;
f6727fb8 AN	105
edcaf1a6	106	txx9_irq_dispatch = jmr3927_irq_dispatch;
1da177e4 LT	107	/* Now, interrupt control disabled, */
	108	/* all IRC interrupts are masked, */
	109	/* all IRC interrupt mode are Low Active. */
	110
1da177e4 LT	111	/* mask all IOC interrupts */
	112	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
	113	/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
	114	jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
	115
1da177e4 LT	116	/* clear PCI Soft interrupts */
	117	jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
	118	/* clear PCI Reset interrupts */
	119	jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
	120
f6727fb8 AN	121	tx3927_irq_init();
	122	for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
	123	set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
1da177e4 LT	124
1da177e4 LT	125	/* setup IOC interrupt 1 (PCI, MODEM) */
edcaf1a6	126	set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
1da177e4	127	}