[linux-2.6-block.git] / arch / mips / sni / pcit.c

/*
 * PCI Tower specific code
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/serial_8250.h>

#include <asm/sni.h>
#include <asm/time.h>
#include <asm/irq_cpu.h>


#define PORT(_base,_irq)				\
	{						\
		.iobase		= _base,		\
		.irq		= _irq,			\
		.uartclk	= 1843200,		\
		.iotype		= UPIO_PORT,		\
		.flags		= UPF_BOOT_AUTOCONF,	\
	}

static struct plat_serial8250_port pcit_data[] = {
	PORT(0x3f8, 0),
	PORT(0x2f8, 3),
	{ },
};

static struct platform_device pcit_serial8250_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= pcit_data,
	},
};

static struct plat_serial8250_port pcit_cplus_data[] = {
	PORT(0x3f8, 0),
	PORT(0x2f8, 3),
	PORT(0x3e8, 4),
	PORT(0x2e8, 3),
	{ },
};

static struct platform_device pcit_cplus_serial8250_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= pcit_cplus_data,
	},
};

static struct resource pcit_cmos_rsrc[] = {
	{
		.start = 0x70,
		.end   = 0x71,
		.flags = IORESOURCE_IO
	},
	{
		.start = 8,
		.end   = 8,
		.flags = IORESOURCE_IRQ
	}
};

static struct platform_device pcit_cmos_device = {
	.name		= "rtc_cmos",
	.num_resources	= ARRAY_SIZE(pcit_cmos_rsrc),
	.resource	= pcit_cmos_rsrc
};

static struct platform_device pcit_pcspeaker_pdev = {
	.name		= "pcspkr",
	.id		= -1,
};

static struct resource sni_io_resource = {
	.start	= 0x00000000UL,
	.end	= 0x03bfffffUL,
	.name	= "PCIT IO",
	.flags	= IORESOURCE_IO,
};

static struct resource pcit_io_resources[] = {
	{
		.start	= 0x00,
		.end	= 0x1f,
		.name	= "dma1",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0x40,
		.end	= 0x5f,
		.name	= "timer",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0x60,
		.end	= 0x6f,
		.name	= "keyboard",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0x80,
		.end	= 0x8f,
		.name	= "dma page reg",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0xc0,
		.end	= 0xdf,
		.name	= "dma2",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0xcf8,
		.end	= 0xcfb,
		.name	= "PCI config addr",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0xcfc,
		.end	= 0xcff,
		.name	= "PCI config data",
		.flags	= IORESOURCE_BUSY
	}
};

static struct resource sni_mem_resource = {
	.start	= 0x18000000UL,
	.end	= 0x1fbfffffUL,
	.name	= "PCIT PCI MEM",
	.flags	= IORESOURCE_MEM
};

static void __init sni_pcit_resource_init(void)
{
	int i;

	/* request I/O space for devices used on all i[345]86 PCs */
	for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
		request_resource(&sni_io_resource, pcit_io_resources + i);
}


extern struct pci_ops sni_pcit_ops;

static struct pci_controller sni_pcit_controller = {
	.pci_ops	= &sni_pcit_ops,
	.mem_resource	= &sni_mem_resource,
	.mem_offset	= 0x00000000UL,
	.io_resource	= &sni_io_resource,
	.io_offset	= 0x00000000UL,
	.io_map_base	= SNI_PORT_BASE
};

static void enable_pcit_irq(struct irq_data *d)
{
	u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);

	*(volatile u32 *)SNI_PCIT_INT_REG |= mask;
}

void disable_pcit_irq(struct irq_data *d)
{
	u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);

	*(volatile u32 *)SNI_PCIT_INT_REG &= ~mask;
}

static struct irq_chip pcit_irq_type = {
	.name = "PCIT",
	.irq_mask = disable_pcit_irq,
	.irq_unmask = enable_pcit_irq,
};

static void pcit_hwint1(void)
{
	u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
	int irq;

	clear_c0_status(IE_IRQ1);
	irq = ffs((pending >> 16) & 0x7f);

	if (likely(irq > 0))
		do_IRQ(irq + SNI_PCIT_INT_START - 1);
	set_c0_status(IE_IRQ1);
}

static void pcit_hwint0(void)
{
	u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
	int irq;

	clear_c0_status(IE_IRQ0);
	irq = ffs((pending >> 16) & 0x3f);

	if (likely(irq > 0))
		do_IRQ(irq + SNI_PCIT_INT_START - 1);
	set_c0_status(IE_IRQ0);
}

static void sni_pcit_hwint(void)
{
	u32 pending = read_c0_cause() & read_c0_status();

	if (pending & C_IRQ1)
		pcit_hwint1();
	else if (pending & C_IRQ2)
		do_IRQ(MIPS_CPU_IRQ_BASE + 4);
	else if (pending & C_IRQ3)
		do_IRQ(MIPS_CPU_IRQ_BASE + 5);
	else if (pending & C_IRQ5)
		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
}

static void sni_pcit_hwint_cplus(void)
{
	u32 pending = read_c0_cause() & read_c0_status();

	if (pending & C_IRQ0)
		pcit_hwint0();
	else if (pending & C_IRQ1)
		do_IRQ(MIPS_CPU_IRQ_BASE + 3);
	else if (pending & C_IRQ2)
		do_IRQ(MIPS_CPU_IRQ_BASE + 4);
	else if (pending & C_IRQ3)
		do_IRQ(MIPS_CPU_IRQ_BASE + 5);
	else if (pending & C_IRQ5)
		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
}

void __init sni_pcit_irq_init(void)
{
	int i;

	mips_cpu_irq_init();
	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
		irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
	*(volatile u32 *)SNI_PCIT_INT_REG = 0;
	sni_hwint = sni_pcit_hwint;
	change_c0_status(ST0_IM, IE_IRQ1);
	setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq);
}

void __init sni_pcit_cplus_irq_init(void)
{
	int i;

	mips_cpu_irq_init();
	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
		irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
	*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
	sni_hwint = sni_pcit_hwint_cplus;
	change_c0_status(ST0_IM, IE_IRQ0);
	setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
}

void __init sni_pcit_init(void)
{
	ioport_resource.end = sni_io_resource.end;
#ifdef CONFIG_PCI
	PCIBIOS_MIN_IO = 0x9000;
	register_pci_controller(&sni_pcit_controller);
#endif
	sni_pcit_resource_init();
}

static int __init snirm_pcit_setup_devinit(void)
{
	switch (sni_brd_type) {
	case SNI_BRD_PCI_TOWER:
		platform_device_register(&pcit_serial8250_device);
		platform_device_register(&pcit_cmos_device);
		platform_device_register(&pcit_pcspeaker_pdev);
		break;

	case SNI_BRD_PCI_TOWER_CPLUS:
		platform_device_register(&pcit_cplus_serial8250_device);
		platform_device_register(&pcit_cmos_device);
		platform_device_register(&pcit_pcspeaker_pdev);
		break;
	}
	return 0;
}

device_initcall(snirm_pcit_setup_devinit);
Commit	Line	Data
c066a32a TB	1	/*
	2	* PCI Tower specific code
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
ca4d3e67	13	#include <linux/irq.h>
c066a32a TB	14	#include <linux/pci.h>
	15	#include <linux/serial_8250.h>
	16
c066a32a TB	17	#include <asm/sni.h>
	18	#include <asm/time.h>
	19	#include <asm/irq_cpu.h>
	20
	21
	22	#define PORT(_base,_irq) \
	23	{ \
	24	.iobase = _base, \
	25	.irq = _irq, \
	26	.uartclk = 1843200, \
	27	.iotype = UPIO_PORT, \
	28	.flags = UPF_BOOT_AUTOCONF, \
	29	}
	30
	31	static struct plat_serial8250_port pcit_data[] = {
	32	PORT(0x3f8, 0),
	33	PORT(0x2f8, 3),
	34	{ },
	35	};
	36
	37	static struct platform_device pcit_serial8250_device = {
	38	.name = "serial8250",
	39	.id = PLAT8250_DEV_PLATFORM,
	40	.dev = {
	41	.platform_data = pcit_data,
	42	},
	43	};
	44
	45	static struct plat_serial8250_port pcit_cplus_data[] = {
bea77175	46	PORT(0x3f8, 0),
c066a32a TB	47	PORT(0x2f8, 3),
	48	PORT(0x3e8, 4),
	49	PORT(0x2e8, 3),
	50	{ },
	51	};
	52
	53	static struct platform_device pcit_cplus_serial8250_device = {
	54	.name = "serial8250",
	55	.id = PLAT8250_DEV_PLATFORM,
	56	.dev = {
	57	.platform_data = pcit_cplus_data,
	58	},
	59	};
	60
06cf5583	61	static struct resource pcit_cmos_rsrc[] = {
70342287 RB	62	{
	63	.start = 0x70,
	64	.end = 0x71,
	65	.flags = IORESOURCE_IO
	66	},
	67	{
	68	.start = 8,
	69	.end = 8,
	70	.flags = IORESOURCE_IRQ
	71	}
06cf5583 TB	72	};
	73
	74	static struct platform_device pcit_cmos_device = {
70342287 RB	75	.name = "rtc_cmos",
	76	.num_resources = ARRAY_SIZE(pcit_cmos_rsrc),
	77	.resource = pcit_cmos_rsrc
06cf5583 TB	78	};
06cf5583 TB	79
19388fb0 RB	80	static struct platform_device pcit_pcspeaker_pdev = {
	81	.name = "pcspkr",
	82	.id = -1,
	83	};
	84
c066a32a	85	static struct resource sni_io_resource = {
bea77175	86	.start = 0x00000000UL,
c066a32a	87	.end = 0x03bfffffUL,
bea77175	88	.name = "PCIT IO",
c066a32a TB	89	.flags = IORESOURCE_IO,
	90	};
	91
	92	static struct resource pcit_io_resources[] = {
	93	{
	94	.start = 0x00,
	95	.end = 0x1f,
	96	.name = "dma1",
	97	.flags = IORESOURCE_BUSY
	98	}, {
	99	.start = 0x40,
	100	.end = 0x5f,
	101	.name = "timer",
	102	.flags = IORESOURCE_BUSY
	103	}, {
	104	.start = 0x60,
	105	.end = 0x6f,
	106	.name = "keyboard",
	107	.flags = IORESOURCE_BUSY
	108	}, {
	109	.start = 0x80,
	110	.end = 0x8f,
	111	.name = "dma page reg",
	112	.flags = IORESOURCE_BUSY
	113	}, {
	114	.start = 0xc0,
	115	.end = 0xdf,
	116	.name = "dma2",
	117	.flags = IORESOURCE_BUSY
bea77175 TB	118	}, {
	119	.start = 0xcf8,
	120	.end = 0xcfb,
	121	.name = "PCI config addr",
	122	.flags = IORESOURCE_BUSY
c066a32a TB	123	}, {
	124	.start = 0xcfc,
	125	.end = 0xcff,
	126	.name = "PCI config data",
	127	.flags = IORESOURCE_BUSY
	128	}
	129	};
	130
	131	static struct resource sni_mem_resource = {
bea77175 TB	132	.start = 0x18000000UL,
bea77175 TB	133	.end = 0x1fbfffffUL,
c066a32a TB	134	.name = "PCIT PCI MEM",
	135	.flags = IORESOURCE_MEM
	136	};
	137
c066a32a TB	138	static void __init sni_pcit_resource_init(void)
	139	{
	140	int i;
	141
	142	/* request I/O space for devices used on all i[345]86 PCs */
	143	for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
bea77175	144	request_resource(&sni_io_resource, pcit_io_resources + i);
c066a32a TB	145	}
	146
	147
	148	extern struct pci_ops sni_pcit_ops;
	149
	150	static struct pci_controller sni_pcit_controller = {
	151	.pci_ops = &sni_pcit_ops,
	152	.mem_resource = &sni_mem_resource,
bea77175	153	.mem_offset = 0x00000000UL,
c066a32a	154	.io_resource = &sni_io_resource,
bea77175	155	.io_offset = 0x00000000UL,
70342287	156	.io_map_base = SNI_PORT_BASE
c066a32a TB	157	};
c066a32a TB	158
0b888c7f	159	static void enable_pcit_irq(struct irq_data *d)
c066a32a	160	{
0b888c7f	161	u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
c066a32a TB	162
	163	(volatile u32 )SNI_PCIT_INT_REG \|= mask;
	164	}
	165
0b888c7f	166	void disable_pcit_irq(struct irq_data *d)
c066a32a	167	{
0b888c7f	168	u32 mask = 1 << (d->irq - SNI_PCIT_INT_START + 24);
c066a32a TB	169
	170	(volatile u32 )SNI_PCIT_INT_REG &= ~mask;
	171	}
	172
c066a32a	173	static struct irq_chip pcit_irq_type = {
8922f79e	174	.name = "PCIT",
0b888c7f TG	175	.irq_mask = disable_pcit_irq,
0b888c7f TG	176	.irq_unmask = enable_pcit_irq,
c066a32a TB	177	};
	178
	179	static void pcit_hwint1(void)
	180	{
	181	u32 pending = (volatile u32 )SNI_PCIT_INT_REG;
	182	int irq;
	183
	184	clear_c0_status(IE_IRQ1);
	185	irq = ffs((pending >> 16) & 0x7f);
	186
	187	if (likely(irq > 0))
49a89efb RB	188	do_IRQ(irq + SNI_PCIT_INT_START - 1);
49a89efb RB	189	set_c0_status(IE_IRQ1);
c066a32a TB	190	}
	191
	192	static void pcit_hwint0(void)
	193	{
	194	u32 pending = (volatile u32 )SNI_PCIT_INT_REG;
	195	int irq;
	196
	197	clear_c0_status(IE_IRQ0);
bea77175	198	irq = ffs((pending >> 16) & 0x3f);
c066a32a TB	199
c066a32a TB	200	if (likely(irq > 0))
49a89efb RB	201	do_IRQ(irq + SNI_PCIT_INT_START - 1);
49a89efb RB	202	set_c0_status(IE_IRQ0);
c066a32a TB	203	}
	204
	205	static void sni_pcit_hwint(void)
	206	{
119537c0	207	u32 pending = read_c0_cause() & read_c0_status();
c066a32a TB	208
	209	if (pending & C_IRQ1)
	210	pcit_hwint1();
	211	else if (pending & C_IRQ2)
49a89efb	212	do_IRQ(MIPS_CPU_IRQ_BASE + 4);
c066a32a	213	else if (pending & C_IRQ3)
49a89efb	214	do_IRQ(MIPS_CPU_IRQ_BASE + 5);
c066a32a	215	else if (pending & C_IRQ5)
49a89efb	216	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
c066a32a TB	217	}
	218
	219	static void sni_pcit_hwint_cplus(void)
	220	{
119537c0	221	u32 pending = read_c0_cause() & read_c0_status();
c066a32a TB	222
	223	if (pending & C_IRQ0)
	224	pcit_hwint0();
bea77175	225	else if (pending & C_IRQ1)
49a89efb	226	do_IRQ(MIPS_CPU_IRQ_BASE + 3);
c066a32a	227	else if (pending & C_IRQ2)
49a89efb	228	do_IRQ(MIPS_CPU_IRQ_BASE + 4);
c066a32a	229	else if (pending & C_IRQ3)
49a89efb	230	do_IRQ(MIPS_CPU_IRQ_BASE + 5);
c066a32a	231	else if (pending & C_IRQ5)
49a89efb	232	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
c066a32a TB	233	}
	234
	235	void __init sni_pcit_irq_init(void)
	236	{
	237	int i;
	238
	239	mips_cpu_irq_init();
	240	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
e4ec7989	241	irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
c066a32a TB	242	(volatile u32 )SNI_PCIT_INT_REG = 0;
	243	sni_hwint = sni_pcit_hwint;
	244	change_c0_status(ST0_IM, IE_IRQ1);
49a89efb	245	setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq);
c066a32a TB	246	}
	247
	248	void __init sni_pcit_cplus_irq_init(void)
	249	{
	250	int i;
	251
	252	mips_cpu_irq_init();
	253	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
e4ec7989	254	irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
bea77175	255	(volatile u32 )SNI_PCIT_INT_REG = 0x40000000;
c066a32a TB	256	sni_hwint = sni_pcit_hwint_cplus;
c066a32a TB	257	change_c0_status(ST0_IM, IE_IRQ0);
49a89efb	258	setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
c066a32a TB	259	}
c066a32a TB	260
06cf5583	261	void __init sni_pcit_init(void)
c066a32a	262	{
bea77175	263	ioport_resource.end = sni_io_resource.end;
c066a32a	264	#ifdef CONFIG_PCI
bea77175	265	PCIBIOS_MIN_IO = 0x9000;
c066a32a TB	266	register_pci_controller(&sni_pcit_controller);
c066a32a TB	267	#endif
bea77175	268	sni_pcit_resource_init();
c066a32a TB	269	}
	270
	271	static int __init snirm_pcit_setup_devinit(void)
	272	{
	273	switch (sni_brd_type) {
	274	case SNI_BRD_PCI_TOWER:
70342287 RB	275	platform_device_register(&pcit_serial8250_device);
70342287 RB	276	platform_device_register(&pcit_cmos_device);
19388fb0	277	platform_device_register(&pcit_pcspeaker_pdev);
70342287	278	break;
c066a32a TB	279
c066a32a TB	280	case SNI_BRD_PCI_TOWER_CPLUS:
70342287 RB	281	platform_device_register(&pcit_cplus_serial8250_device);
70342287 RB	282	platform_device_register(&pcit_cmos_device);
19388fb0	283	platform_device_register(&pcit_pcspeaker_pdev);
70342287	284	break;
c066a32a TB	285	}
	286	return 0;
	287	}
	288
	289	device_initcall(snirm_pcit_setup_devinit);