[linux-2.6-block.git] / arch / mips / sni / pcit.c

/*
 * PCI Tower specific code
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/serial_8250.h>

#include <asm/sni.h>
#include <asm/time.h>
#include <asm/irq_cpu.h>


#define PORT(_base,_irq)				\
	{						\
		.iobase		= _base,		\
		.irq		= _irq,			\
		.uartclk	= 1843200,		\
		.iotype		= UPIO_PORT,		\
		.flags		= UPF_BOOT_AUTOCONF,	\
	}

static struct plat_serial8250_port pcit_data[] = {
	PORT(0x3f8, 0),
	PORT(0x2f8, 3),
	{ },
};

static struct platform_device pcit_serial8250_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= pcit_data,
	},
};

static struct plat_serial8250_port pcit_cplus_data[] = {
	PORT(0x3f8, 0),
	PORT(0x2f8, 3),
	PORT(0x3e8, 4),
	PORT(0x2e8, 3),
	{ },
};

static struct platform_device pcit_cplus_serial8250_device = {
	.name			= "serial8250",
	.id			= PLAT8250_DEV_PLATFORM,
	.dev			= {
		.platform_data	= pcit_cplus_data,
	},
};

static struct resource pcit_cmos_rsrc[] = {
        {
                .start = 0x70,
                .end   = 0x71,
                .flags = IORESOURCE_IO
        },
        {
                .start = 8,
                .end   = 8,
                .flags = IORESOURCE_IRQ
        }
};

static struct platform_device pcit_cmos_device = {
        .name           = "rtc_cmos",
        .num_resources  = ARRAY_SIZE(pcit_cmos_rsrc),
        .resource       = pcit_cmos_rsrc
};

static struct resource sni_io_resource = {
	.start	= 0x00000000UL,
	.end	= 0x03bfffffUL,
	.name	= "PCIT IO",
	.flags	= IORESOURCE_IO,
};

static struct resource pcit_io_resources[] = {
	{
		.start	= 0x00,
		.end	= 0x1f,
		.name	= "dma1",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0x40,
		.end	= 0x5f,
		.name	= "timer",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0x60,
		.end	= 0x6f,
		.name	= "keyboard",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0x80,
		.end	= 0x8f,
		.name	= "dma page reg",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0xc0,
		.end	= 0xdf,
		.name	= "dma2",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0xcf8,
		.end	= 0xcfb,
		.name	= "PCI config addr",
		.flags	= IORESOURCE_BUSY
	}, {
		.start	=  0xcfc,
		.end	= 0xcff,
		.name	= "PCI config data",
		.flags	= IORESOURCE_BUSY
	}
};

static struct resource sni_mem_resource = {
	.start	= 0x18000000UL,
	.end	= 0x1fbfffffUL,
	.name	= "PCIT PCI MEM",
	.flags	= IORESOURCE_MEM
};

static void __init sni_pcit_resource_init(void)
{
	int i;

	/* request I/O space for devices used on all i[345]86 PCs */
	for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
		request_resource(&sni_io_resource, pcit_io_resources + i);
}


extern struct pci_ops sni_pcit_ops;

static struct pci_controller sni_pcit_controller = {
	.pci_ops	= &sni_pcit_ops,
	.mem_resource	= &sni_mem_resource,
	.mem_offset	= 0x00000000UL,
	.io_resource	= &sni_io_resource,
	.io_offset	= 0x00000000UL,
	.io_map_base    = SNI_PORT_BASE
};

static void enable_pcit_irq(unsigned int irq)
{
	u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24);

	*(volatile u32 *)SNI_PCIT_INT_REG |= mask;
}

void disable_pcit_irq(unsigned int irq)
{
	u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24);

	*(volatile u32 *)SNI_PCIT_INT_REG &= ~mask;
}

void end_pcit_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_pcit_irq(irq);
}

static struct irq_chip pcit_irq_type = {
	.typename = "PCIT",
	.ack = disable_pcit_irq,
	.mask = disable_pcit_irq,
	.mask_ack = disable_pcit_irq,
	.unmask = enable_pcit_irq,
	.end = end_pcit_irq,
};

static void pcit_hwint1(void)
{
	u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
	int irq;

	clear_c0_status(IE_IRQ1);
	irq = ffs((pending >> 16) & 0x7f);

	if (likely(irq > 0))
		do_IRQ(irq + SNI_PCIT_INT_START - 1);
	set_c0_status(IE_IRQ1);
}

static void pcit_hwint0(void)
{
	u32 pending = *(volatile u32 *)SNI_PCIT_INT_REG;
	int irq;

	clear_c0_status(IE_IRQ0);
	irq = ffs((pending >> 16) & 0x3f);

	if (likely(irq > 0))
		do_IRQ(irq + SNI_PCIT_INT_START - 1);
	set_c0_status(IE_IRQ0);
}

static void sni_pcit_hwint(void)
{
	u32 pending = read_c0_cause() & read_c0_status();

	if (pending & C_IRQ1)
		pcit_hwint1();
	else if (pending & C_IRQ2)
		do_IRQ(MIPS_CPU_IRQ_BASE + 4);
	else if (pending & C_IRQ3)
		do_IRQ(MIPS_CPU_IRQ_BASE + 5);
	else if (pending & C_IRQ5)
		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
}

static void sni_pcit_hwint_cplus(void)
{
	u32 pending = read_c0_cause() & read_c0_status();

	if (pending & C_IRQ0)
		pcit_hwint0();
	else if (pending & C_IRQ1)
		do_IRQ(MIPS_CPU_IRQ_BASE + 3);
	else if (pending & C_IRQ2)
		do_IRQ(MIPS_CPU_IRQ_BASE + 4);
	else if (pending & C_IRQ3)
		do_IRQ(MIPS_CPU_IRQ_BASE + 5);
	else if (pending & C_IRQ5)
		do_IRQ(MIPS_CPU_IRQ_BASE + 7);
}

void __init sni_pcit_irq_init(void)
{
	int i;

	mips_cpu_irq_init();
	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
		set_irq_chip(i, &pcit_irq_type);
	*(volatile u32 *)SNI_PCIT_INT_REG = 0;
	sni_hwint = sni_pcit_hwint;
	change_c0_status(ST0_IM, IE_IRQ1);
	setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq);
}

void __init sni_pcit_cplus_irq_init(void)
{
	int i;

	mips_cpu_irq_init();
	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
		set_irq_chip(i, &pcit_irq_type);
	*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
	sni_hwint = sni_pcit_hwint_cplus;
	change_c0_status(ST0_IM, IE_IRQ0);
	setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
}

void __init sni_pcit_init(void)
{
	ioport_resource.end = sni_io_resource.end;
#ifdef CONFIG_PCI
	PCIBIOS_MIN_IO = 0x9000;
	register_pci_controller(&sni_pcit_controller);
#endif
	sni_pcit_resource_init();
}

static int __init snirm_pcit_setup_devinit(void)
{
	switch (sni_brd_type) {
	case SNI_BRD_PCI_TOWER:
	        platform_device_register(&pcit_serial8250_device);
	        platform_device_register(&pcit_cmos_device);
	        break;

	case SNI_BRD_PCI_TOWER_CPLUS:
	        platform_device_register(&pcit_cplus_serial8250_device);
	        platform_device_register(&pcit_cmos_device);
	        break;
	}
	return 0;
}

device_initcall(snirm_pcit_setup_devinit);
Commit	Line	Data
c066a32a TB	1	/*
	2	* PCI Tower specific code
	3	*
	4	* This file is subject to the terms and conditions of the GNU General Public
	5	* License. See the file "COPYING" in the main directory of this archive
	6	* for more details.
	7	*
	8	* Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/pci.h>
	14	#include <linux/serial_8250.h>
	15
c066a32a TB	16	#include <asm/sni.h>
	17	#include <asm/time.h>
	18	#include <asm/irq_cpu.h>
	19
	20
	21	#define PORT(_base,_irq) \
	22	{ \
	23	.iobase = _base, \
	24	.irq = _irq, \
	25	.uartclk = 1843200, \
	26	.iotype = UPIO_PORT, \
	27	.flags = UPF_BOOT_AUTOCONF, \
	28	}
	29
	30	static struct plat_serial8250_port pcit_data[] = {
	31	PORT(0x3f8, 0),
	32	PORT(0x2f8, 3),
	33	{ },
	34	};
	35
	36	static struct platform_device pcit_serial8250_device = {
	37	.name = "serial8250",
	38	.id = PLAT8250_DEV_PLATFORM,
	39	.dev = {
	40	.platform_data = pcit_data,
	41	},
	42	};
	43
	44	static struct plat_serial8250_port pcit_cplus_data[] = {
bea77175	45	PORT(0x3f8, 0),
c066a32a TB	46	PORT(0x2f8, 3),
	47	PORT(0x3e8, 4),
	48	PORT(0x2e8, 3),
	49	{ },
	50	};
	51
	52	static struct platform_device pcit_cplus_serial8250_device = {
	53	.name = "serial8250",
	54	.id = PLAT8250_DEV_PLATFORM,
	55	.dev = {
	56	.platform_data = pcit_cplus_data,
	57	},
	58	};
	59
06cf5583 TB	60	static struct resource pcit_cmos_rsrc[] = {
	61	{
	62	.start = 0x70,
	63	.end = 0x71,
	64	.flags = IORESOURCE_IO
	65	},
	66	{
	67	.start = 8,
	68	.end = 8,
	69	.flags = IORESOURCE_IRQ
	70	}
	71	};
	72
	73	static struct platform_device pcit_cmos_device = {
	74	.name = "rtc_cmos",
	75	.num_resources = ARRAY_SIZE(pcit_cmos_rsrc),
	76	.resource = pcit_cmos_rsrc
	77	};
	78
c066a32a	79	static struct resource sni_io_resource = {
bea77175	80	.start = 0x00000000UL,
c066a32a	81	.end = 0x03bfffffUL,
bea77175	82	.name = "PCIT IO",
c066a32a TB	83	.flags = IORESOURCE_IO,
	84	};
	85
	86	static struct resource pcit_io_resources[] = {
	87	{
	88	.start = 0x00,
	89	.end = 0x1f,
	90	.name = "dma1",
	91	.flags = IORESOURCE_BUSY
	92	}, {
	93	.start = 0x40,
	94	.end = 0x5f,
	95	.name = "timer",
	96	.flags = IORESOURCE_BUSY
	97	}, {
	98	.start = 0x60,
	99	.end = 0x6f,
	100	.name = "keyboard",
	101	.flags = IORESOURCE_BUSY
	102	}, {
	103	.start = 0x80,
	104	.end = 0x8f,
	105	.name = "dma page reg",
	106	.flags = IORESOURCE_BUSY
	107	}, {
	108	.start = 0xc0,
	109	.end = 0xdf,
	110	.name = "dma2",
	111	.flags = IORESOURCE_BUSY
bea77175 TB	112	}, {
	113	.start = 0xcf8,
	114	.end = 0xcfb,
	115	.name = "PCI config addr",
	116	.flags = IORESOURCE_BUSY
c066a32a TB	117	}, {
	118	.start = 0xcfc,
	119	.end = 0xcff,
	120	.name = "PCI config data",
	121	.flags = IORESOURCE_BUSY
	122	}
	123	};
	124
	125	static struct resource sni_mem_resource = {
bea77175 TB	126	.start = 0x18000000UL,
bea77175 TB	127	.end = 0x1fbfffffUL,
c066a32a TB	128	.name = "PCIT PCI MEM",
	129	.flags = IORESOURCE_MEM
	130	};
	131
c066a32a TB	132	static void __init sni_pcit_resource_init(void)
	133	{
	134	int i;
	135
	136	/* request I/O space for devices used on all i[345]86 PCs */
	137	for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
bea77175	138	request_resource(&sni_io_resource, pcit_io_resources + i);
c066a32a TB	139	}
	140
	141
	142	extern struct pci_ops sni_pcit_ops;
	143
	144	static struct pci_controller sni_pcit_controller = {
	145	.pci_ops = &sni_pcit_ops,
	146	.mem_resource = &sni_mem_resource,
bea77175	147	.mem_offset = 0x00000000UL,
c066a32a	148	.io_resource = &sni_io_resource,
bea77175 TB	149	.io_offset = 0x00000000UL,
bea77175 TB	150	.io_map_base = SNI_PORT_BASE
c066a32a TB	151	};
	152
	153	static void enable_pcit_irq(unsigned int irq)
	154	{
	155	u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24);
	156
	157	(volatile u32 )SNI_PCIT_INT_REG \|= mask;
	158	}
	159
	160	void disable_pcit_irq(unsigned int irq)
	161	{
	162	u32 mask = 1 << (irq - SNI_PCIT_INT_START + 24);
	163
	164	(volatile u32 )SNI_PCIT_INT_REG &= ~mask;
	165	}
	166
	167	void end_pcit_irq(unsigned int irq)
	168	{
	169	if (!(irq_desc[irq].status & (IRQ_DISABLED\|IRQ_INPROGRESS)))
	170	enable_pcit_irq(irq);
	171	}
	172
	173	static struct irq_chip pcit_irq_type = {
	174	.typename = "PCIT",
	175	.ack = disable_pcit_irq,
	176	.mask = disable_pcit_irq,
	177	.mask_ack = disable_pcit_irq,
	178	.unmask = enable_pcit_irq,
	179	.end = end_pcit_irq,
	180	};
	181
	182	static void pcit_hwint1(void)
	183	{
	184	u32 pending = (volatile u32 )SNI_PCIT_INT_REG;
	185	int irq;
	186
	187	clear_c0_status(IE_IRQ1);
	188	irq = ffs((pending >> 16) & 0x7f);
	189
	190	if (likely(irq > 0))
49a89efb RB	191	do_IRQ(irq + SNI_PCIT_INT_START - 1);
49a89efb RB	192	set_c0_status(IE_IRQ1);
c066a32a TB	193	}
	194
	195	static void pcit_hwint0(void)
	196	{
	197	u32 pending = (volatile u32 )SNI_PCIT_INT_REG;
	198	int irq;
	199
	200	clear_c0_status(IE_IRQ0);
bea77175	201	irq = ffs((pending >> 16) & 0x3f);
c066a32a TB	202
c066a32a TB	203	if (likely(irq > 0))
49a89efb RB	204	do_IRQ(irq + SNI_PCIT_INT_START - 1);
49a89efb RB	205	set_c0_status(IE_IRQ0);
c066a32a TB	206	}
	207
	208	static void sni_pcit_hwint(void)
	209	{
119537c0	210	u32 pending = read_c0_cause() & read_c0_status();
c066a32a TB	211
	212	if (pending & C_IRQ1)
	213	pcit_hwint1();
	214	else if (pending & C_IRQ2)
49a89efb	215	do_IRQ(MIPS_CPU_IRQ_BASE + 4);
c066a32a	216	else if (pending & C_IRQ3)
49a89efb	217	do_IRQ(MIPS_CPU_IRQ_BASE + 5);
c066a32a	218	else if (pending & C_IRQ5)
49a89efb	219	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
c066a32a TB	220	}
	221
	222	static void sni_pcit_hwint_cplus(void)
	223	{
119537c0	224	u32 pending = read_c0_cause() & read_c0_status();
c066a32a TB	225
	226	if (pending & C_IRQ0)
	227	pcit_hwint0();
bea77175	228	else if (pending & C_IRQ1)
49a89efb	229	do_IRQ(MIPS_CPU_IRQ_BASE + 3);
c066a32a	230	else if (pending & C_IRQ2)
49a89efb	231	do_IRQ(MIPS_CPU_IRQ_BASE + 4);
c066a32a	232	else if (pending & C_IRQ3)
49a89efb	233	do_IRQ(MIPS_CPU_IRQ_BASE + 5);
c066a32a	234	else if (pending & C_IRQ5)
49a89efb	235	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
c066a32a TB	236	}
	237
	238	void __init sni_pcit_irq_init(void)
	239	{
	240	int i;
	241
	242	mips_cpu_irq_init();
	243	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
	244	set_irq_chip(i, &pcit_irq_type);
	245	(volatile u32 )SNI_PCIT_INT_REG = 0;
	246	sni_hwint = sni_pcit_hwint;
	247	change_c0_status(ST0_IM, IE_IRQ1);
49a89efb	248	setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq);
c066a32a TB	249	}
	250
	251	void __init sni_pcit_cplus_irq_init(void)
	252	{
	253	int i;
	254
	255	mips_cpu_irq_init();
	256	for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
	257	set_irq_chip(i, &pcit_irq_type);
bea77175	258	(volatile u32 )SNI_PCIT_INT_REG = 0x40000000;
c066a32a TB	259	sni_hwint = sni_pcit_hwint_cplus;
c066a32a TB	260	change_c0_status(ST0_IM, IE_IRQ0);
49a89efb	261	setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
c066a32a TB	262	}
c066a32a TB	263
06cf5583	264	void __init sni_pcit_init(void)
c066a32a	265	{
bea77175	266	ioport_resource.end = sni_io_resource.end;
c066a32a	267	#ifdef CONFIG_PCI
bea77175	268	PCIBIOS_MIN_IO = 0x9000;
c066a32a TB	269	register_pci_controller(&sni_pcit_controller);
c066a32a TB	270	#endif
bea77175	271	sni_pcit_resource_init();
c066a32a TB	272	}
	273
	274	static int __init snirm_pcit_setup_devinit(void)
	275	{
	276	switch (sni_brd_type) {
	277	case SNI_BRD_PCI_TOWER:
	278	platform_device_register(&pcit_serial8250_device);
06cf5583	279	platform_device_register(&pcit_cmos_device);
c066a32a TB	280	break;
	281
	282	case SNI_BRD_PCI_TOWER_CPLUS:
	283	platform_device_register(&pcit_cplus_serial8250_device);
06cf5583	284	platform_device_register(&pcit_cmos_device);
c066a32a TB	285	break;
	286	}
	287	return 0;
	288	}
	289
	290	device_initcall(snirm_pcit_setup_devinit);