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1da177e4 LT |
1 | /* |
2 | * Copyright (C) 2001, 2002, 2003 Broadcom Corporation | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | */ | |
18 | ||
19 | #include <linux/init.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/smp.h> | |
23 | #include <linux/kernel_stat.h> | |
184748cc | 24 | #include <linux/sched.h> |
1da177e4 LT |
25 | |
26 | #include <asm/mmu_context.h> | |
27 | #include <asm/io.h> | |
87353d8a | 28 | #include <asm/fw/cfe/cfe_api.h> |
1da177e4 LT |
29 | #include <asm/sibyte/sb1250.h> |
30 | #include <asm/sibyte/sb1250_regs.h> | |
31 | #include <asm/sibyte/sb1250_int.h> | |
32 | ||
33 | static void *mailbox_set_regs[] = { | |
65bda1a9 MR |
34 | IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_SET_CPU), |
35 | IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_SET_CPU) | |
1da177e4 LT |
36 | }; |
37 | ||
38 | static void *mailbox_clear_regs[] = { | |
65bda1a9 MR |
39 | IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CLR_CPU), |
40 | IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CLR_CPU) | |
1da177e4 LT |
41 | }; |
42 | ||
43 | static void *mailbox_regs[] = { | |
65bda1a9 MR |
44 | IOADDR(A_IMR_CPU0_BASE + R_IMR_MAILBOX_CPU), |
45 | IOADDR(A_IMR_CPU1_BASE + R_IMR_MAILBOX_CPU) | |
1da177e4 LT |
46 | }; |
47 | ||
48 | /* | |
49 | * SMP init and finish on secondary CPUs | |
50 | */ | |
078a55fc | 51 | void sb1250_smp_init(void) |
1da177e4 LT |
52 | { |
53 | unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | | |
54 | STATUSF_IP1 | STATUSF_IP0; | |
55 | ||
56 | /* Set interrupt mask, but don't enable */ | |
57 | change_c0_status(ST0_IM, imask); | |
58 | } | |
59 | ||
87353d8a RB |
60 | /* |
61 | * These are routines for dealing with the sb1250 smp capabilities | |
62 | * independent of board/firmware | |
63 | */ | |
64 | ||
65 | /* | |
66 | * Simple enough; everything is set up, so just poke the appropriate mailbox | |
67 | * register, and we should be set | |
68 | */ | |
69 | static void sb1250_send_ipi_single(int cpu, unsigned int action) | |
70 | { | |
71 | __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); | |
72 | } | |
73 | ||
48a048fe RR |
74 | static inline void sb1250_send_ipi_mask(const struct cpumask *mask, |
75 | unsigned int action) | |
87353d8a RB |
76 | { |
77 | unsigned int i; | |
78 | ||
48a048fe | 79 | for_each_cpu(i, mask) |
87353d8a RB |
80 | sb1250_send_ipi_single(i, action); |
81 | } | |
82 | ||
83 | /* | |
84 | * Code to run on secondary just after probing the CPU | |
85 | */ | |
078a55fc | 86 | static void sb1250_init_secondary(void) |
87353d8a RB |
87 | { |
88 | extern void sb1250_smp_init(void); | |
89 | ||
90 | sb1250_smp_init(); | |
91 | } | |
92 | ||
93 | /* | |
94 | * Do any tidying up before marking online and running the idle | |
95 | * loop | |
96 | */ | |
078a55fc | 97 | static void sb1250_smp_finish(void) |
1da177e4 | 98 | { |
d527eef5 RB |
99 | extern void sb1250_clockevent_init(void); |
100 | ||
101 | sb1250_clockevent_init(); | |
1da177e4 LT |
102 | local_irq_enable(); |
103 | } | |
104 | ||
105 | /* | |
87353d8a | 106 | * Final cleanup after all secondaries booted |
1da177e4 | 107 | */ |
87353d8a RB |
108 | static void sb1250_cpus_done(void) |
109 | { | |
110 | } | |
1da177e4 LT |
111 | |
112 | /* | |
87353d8a RB |
113 | * Setup the PC, SP, and GP of a secondary processor and start it |
114 | * running! | |
1da177e4 | 115 | */ |
078a55fc | 116 | static void sb1250_boot_secondary(int cpu, struct task_struct *idle) |
1da177e4 | 117 | { |
87353d8a RB |
118 | int retval; |
119 | ||
120 | retval = cfe_cpu_start(cpu_logical_map(cpu), &smp_bootstrap, | |
121 | __KSTK_TOS(idle), | |
122 | (unsigned long)task_thread_info(idle), 0); | |
123 | if (retval != 0) | |
124 | printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval); | |
1da177e4 LT |
125 | } |
126 | ||
87353d8a RB |
127 | /* |
128 | * Use CFE to find out how many CPUs are available, setting up | |
0b5f9c00 | 129 | * cpu_possible_mask and the logical/physical mappings. |
87353d8a RB |
130 | * XXXKW will the boot CPU ever not be physical 0? |
131 | * | |
132 | * Common setup before any secondaries are started | |
133 | */ | |
134 | static void __init sb1250_smp_setup(void) | |
135 | { | |
136 | int i, num; | |
137 | ||
0b5f9c00 | 138 | init_cpu_possible(cpumask_of(0)); |
87353d8a RB |
139 | __cpu_number_map[0] = 0; |
140 | __cpu_logical_map[0] = 0; | |
141 | ||
142 | for (i = 1, num = 0; i < NR_CPUS; i++) { | |
143 | if (cfe_cpu_stop(i) == 0) { | |
0b5f9c00 | 144 | set_cpu_possible(i, true); |
87353d8a RB |
145 | __cpu_number_map[i] = ++num; |
146 | __cpu_logical_map[num] = i; | |
147 | } | |
148 | } | |
149 | printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); | |
150 | } | |
151 | ||
152 | static void __init sb1250_prepare_cpus(unsigned int max_cpus) | |
153 | { | |
154 | } | |
155 | ||
156 | struct plat_smp_ops sb_smp_ops = { | |
157 | .send_ipi_single = sb1250_send_ipi_single, | |
158 | .send_ipi_mask = sb1250_send_ipi_mask, | |
159 | .init_secondary = sb1250_init_secondary, | |
160 | .smp_finish = sb1250_smp_finish, | |
161 | .cpus_done = sb1250_cpus_done, | |
162 | .boot_secondary = sb1250_boot_secondary, | |
163 | .smp_setup = sb1250_smp_setup, | |
164 | .prepare_cpus = sb1250_prepare_cpus, | |
165 | }; | |
166 | ||
937a8015 | 167 | void sb1250_mailbox_interrupt(void) |
1da177e4 LT |
168 | { |
169 | int cpu = smp_processor_id(); | |
d2287f5e | 170 | int irq = K_INT_MBOX_0; |
1da177e4 LT |
171 | unsigned int action; |
172 | ||
310ff2c8 | 173 | kstat_incr_irq_this_cpu(irq); |
1da177e4 | 174 | /* Load the mailbox register to figure out what we're supposed to do */ |
65bda1a9 | 175 | action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; |
1da177e4 LT |
176 | |
177 | /* Clear the mailbox to clear the interrupt */ | |
65bda1a9 | 178 | ____raw_writeq(((u64)action) << 48, mailbox_clear_regs[cpu]); |
1da177e4 | 179 | |
184748cc PZ |
180 | if (action & SMP_RESCHEDULE_YOURSELF) |
181 | scheduler_ipi(); | |
1da177e4 LT |
182 | |
183 | if (action & SMP_CALL_FUNCTION) | |
184 | smp_call_function_interrupt(); | |
185 | } |