[linux-block.git] / arch / mips / sibyte / Kconfig

# SPDX-License-Identifier: GPL-2.0
config SIBYTE_SB1250
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_ENABLE_LDT_IF_PCI
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC
	select SYS_SUPPORTS_SMP

config SIBYTE_BCM1120
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select IRQ_MIPS_CPU
	select SIBYTE_BCM112X
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC

config SIBYTE_BCM1125
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_BCM112X
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC

config SIBYTE_BCM1125H
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_BCM112X
	select SIBYTE_ENABLE_LDT_IF_PCI
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC

config SIBYTE_BCM112X
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select IRQ_MIPS_CPU
	select SIBYTE_SB1xxx_SOC
	select SIBYTE_HAS_ZBUS_PROFILING

config SIBYTE_BCM1x80
	bool
	select CEVT_BCM1480
	select CSRC_BCM1480
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC
	select SYS_SUPPORTS_SMP

config SIBYTE_BCM1x55
	bool
	select CEVT_BCM1480
	select CSRC_BCM1480
	select HW_HAS_PCI
	select IRQ_MIPS_CPU
	select SIBYTE_SB1xxx_SOC
	select SIBYTE_HAS_ZBUS_PROFILING
	select SYS_SUPPORTS_SMP

config SIBYTE_SB1xxx_SOC
	bool
	select DMA_COHERENT
	select IRQ_MIPS_CPU
	select SWAP_IO_SPACE
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL
	select FW_CFE
	select SYS_HAS_EARLY_PRINTK

choice
	prompt "SiByte SOC Stepping"
	depends on SIBYTE_SB1xxx_SOC

config CPU_SB1_PASS_2_1250
	bool "1250 An"
	depends on SIBYTE_SB1250
	select CPU_SB1_PASS_2
	help
	  Also called BCM1250 Pass 2

config CPU_SB1_PASS_2_2
	bool "1250 Bn"
	depends on SIBYTE_SB1250
	select CPU_HAS_PREFETCH
	help
	  Also called BCM1250 Pass 2.2

config CPU_SB1_PASS_4
	bool "1250 Cn"
	depends on SIBYTE_SB1250
	select CPU_HAS_PREFETCH
	help
	  Also called BCM1250 Pass 3

config CPU_SB1_PASS_2_112x
	bool "112x Hybrid"
	depends on SIBYTE_BCM112X
	select CPU_SB1_PASS_2

config CPU_SB1_PASS_3
	bool "112x An"
	depends on SIBYTE_BCM112X
	select CPU_HAS_PREFETCH

endchoice

config CPU_SB1_PASS_2
	bool

config SIBYTE_HAS_LDT
	bool

config SIBYTE_ENABLE_LDT_IF_PCI
	bool
	select SIBYTE_HAS_LDT if PCI

config SB1_CEX_ALWAYS_FATAL
	bool "All cache exceptions considered fatal (no recovery attempted)"
	depends on SIBYTE_SB1xxx_SOC

config SB1_CERR_STALL
	bool "Stall (rather than panic) on fatal cache error"
	depends on SIBYTE_SB1xxx_SOC

config SIBYTE_CFE_CONSOLE
	bool "Use firmware console"
	depends on SIBYTE_SB1xxx_SOC
	help
	  Use the CFE API's console write routines during boot.  Other console
	  options (VT console, sb1250 duart console, etc.) should not be
	  configured.

config SIBYTE_BUS_WATCHER
	bool "Support for Bus Watcher statistics"
	depends on SIBYTE_SB1xxx_SOC && \
		(SIBYTE_BCM112X || SIBYTE_SB1250 || \
		 SIBYTE_BCM1x55 || SIBYTE_BCM1x80)
	help
	  Handle and keep statistics on the bus error interrupts (COR_ECC,
	  BAD_ECC, IO_BUS).

config SIBYTE_BW_TRACE
	bool "Capture bus trace before bus error"
	depends on SIBYTE_BUS_WATCHER
	help
	  Run a continuous bus trace, dumping the raw data as soon as
	  a ZBbus error is detected.  Cannot work if ZBbus profiling
	  is turned on, and also will interfere with JTAG-based trace
	  buffer activity.  Raw buffer data is dumped to console, and
	  must be processed off-line.

config SIBYTE_TBPROF
	tristate "Support for ZBbus profiling"
	depends on SIBYTE_HAS_ZBUS_PROFILING

config SIBYTE_HAS_ZBUS_PROFILING
	bool
Commit	Line	Data
b2441318	1	# SPDX-License-Identifier: GPL-2.0
38b18f72 RB	2	config SIBYTE_SB1250
38b18f72 RB	3	bool
217dd11e RB	4	select CEVT_SB1250
217dd11e RB	5	select CSRC_SB1250
38b18f72	6	select HW_HAS_PCI
67e38cf2	7	select IRQ_MIPS_CPU
ca6f5494	8	select SIBYTE_ENABLE_LDT_IF_PCI
d619f38f	9	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72	10	select SIBYTE_SB1xxx_SOC
e73ea273	11	select SYS_SUPPORTS_SMP
38b18f72 RB	12
	13	config SIBYTE_BCM1120
	14	bool
217dd11e RB	15	select CEVT_SB1250
217dd11e RB	16	select CSRC_SB1250
67e38cf2	17	select IRQ_MIPS_CPU
38b18f72	18	select SIBYTE_BCM112X
bb9b813b	19	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 RB	20	select SIBYTE_SB1xxx_SOC
	21
	22	config SIBYTE_BCM1125
	23	bool
217dd11e RB	24	select CEVT_SB1250
217dd11e RB	25	select CSRC_SB1250
38b18f72	26	select HW_HAS_PCI
67e38cf2	27	select IRQ_MIPS_CPU
38b18f72	28	select SIBYTE_BCM112X
bb9b813b	29	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 RB	30	select SIBYTE_SB1xxx_SOC
	31
	32	config SIBYTE_BCM1125H
	33	bool
217dd11e RB	34	select CEVT_SB1250
217dd11e RB	35	select CSRC_SB1250
38b18f72	36	select HW_HAS_PCI
67e38cf2	37	select IRQ_MIPS_CPU
38b18f72	38	select SIBYTE_BCM112X
ca6f5494	39	select SIBYTE_ENABLE_LDT_IF_PCI
bb9b813b	40	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 RB	41	select SIBYTE_SB1xxx_SOC
	42
	43	config SIBYTE_BCM112X
	44	bool
217dd11e RB	45	select CEVT_SB1250
217dd11e RB	46	select CSRC_SB1250
67e38cf2	47	select IRQ_MIPS_CPU
38b18f72	48	select SIBYTE_SB1xxx_SOC
bb9b813b	49	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72	50
f137e463 AI	51	config SIBYTE_BCM1x80
f137e463 AI	52	bool
217dd11e RB	53	select CEVT_BCM1480
217dd11e RB	54	select CSRC_BCM1480
f137e463	55	select HW_HAS_PCI
67e38cf2	56	select IRQ_MIPS_CPU
d619f38f	57	select SIBYTE_HAS_ZBUS_PROFILING
f137e463	58	select SIBYTE_SB1xxx_SOC
e73ea273	59	select SYS_SUPPORTS_SMP
f137e463 AI	60
	61	config SIBYTE_BCM1x55
	62	bool
217dd11e RB	63	select CEVT_BCM1480
217dd11e RB	64	select CSRC_BCM1480
f137e463	65	select HW_HAS_PCI
67e38cf2	66	select IRQ_MIPS_CPU
f137e463	67	select SIBYTE_SB1xxx_SOC
bb9b813b	68	select SIBYTE_HAS_ZBUS_PROFILING
e73ea273	69	select SYS_SUPPORTS_SMP
f137e463	70
38b18f72 RB	71	config SIBYTE_SB1xxx_SOC
38b18f72 RB	72	bool
38b18f72	73	select DMA_COHERENT
67e38cf2	74	select IRQ_MIPS_CPU
38b18f72 RB	75	select SWAP_IO_SPACE
	76	select SYS_SUPPORTS_32BIT_KERNEL
	77	select SYS_SUPPORTS_64BIT_KERNEL
0e2794b0	78	select FW_CFE
05f94eeb	79	select SYS_HAS_EARLY_PRINTK
38b18f72 RB	80
	81	choice
	82	prompt "SiByte SOC Stepping"
	83	depends on SIBYTE_SB1xxx_SOC
	84
38b18f72 RB	85	config CPU_SB1_PASS_2_1250
	86	bool "1250 An"
	87	depends on SIBYTE_SB1250
	88	select CPU_SB1_PASS_2
	89	help
	90	Also called BCM1250 Pass 2
	91
	92	config CPU_SB1_PASS_2_2
	93	bool "1250 Bn"
	94	depends on SIBYTE_SB1250
	95	select CPU_HAS_PREFETCH
	96	help
	97	Also called BCM1250 Pass 2.2
	98
	99	config CPU_SB1_PASS_4
	100	bool "1250 Cn"
	101	depends on SIBYTE_SB1250
	102	select CPU_HAS_PREFETCH
	103	help
	104	Also called BCM1250 Pass 3
	105
	106	config CPU_SB1_PASS_2_112x
	107	bool "112x Hybrid"
	108	depends on SIBYTE_BCM112X
	109	select CPU_SB1_PASS_2
	110
	111	config CPU_SB1_PASS_3
	112	bool "112x An"
	113	depends on SIBYTE_BCM112X
	114	select CPU_HAS_PREFETCH
	115
	116	endchoice
	117
	118	config CPU_SB1_PASS_2
	119	bool
	120
	121	config SIBYTE_HAS_LDT
	122	bool
ca6f5494 RB	123
	124	config SIBYTE_ENABLE_LDT_IF_PCI
	125	bool
	126	select SIBYTE_HAS_LDT if PCI
38b18f72	127
77607635	128	config SB1_CEX_ALWAYS_FATAL
a4b5bd9a AI	129	bool "All cache exceptions considered fatal (no recovery attempted)"
	130	depends on SIBYTE_SB1xxx_SOC
	131
77607635	132	config SB1_CERR_STALL
a4b5bd9a AI	133	bool "Stall (rather than panic) on fatal cache error"
	134	depends on SIBYTE_SB1xxx_SOC
	135
38b18f72 RB	136	config SIBYTE_CFE_CONSOLE
38b18f72 RB	137	bool "Use firmware console"
05f94eeb	138	depends on SIBYTE_SB1xxx_SOC
38b18f72 RB	139	help
	140	Use the CFE API's console write routines during boot. Other console
	141	options (VT console, sb1250 duart console, etc.) should not be
	142	configured.
	143
38b18f72 RB	144	config SIBYTE_BUS_WATCHER
38b18f72 RB	145	bool "Support for Bus Watcher statistics"
6793f55c	146	depends on SIBYTE_SB1xxx_SOC && \
54292850 AR	147	(SIBYTE_BCM112X \|\| SIBYTE_SB1250 \|\| \
54292850 AR	148	SIBYTE_BCM1x55 \|\| SIBYTE_BCM1x80)
38b18f72 RB	149	help
	150	Handle and keep statistics on the bus error interrupts (COR_ECC,
	151	BAD_ECC, IO_BUS).
	152
	153	config SIBYTE_BW_TRACE
	154	bool "Capture bus trace before bus error"
	155	depends on SIBYTE_BUS_WATCHER
	156	help
	157	Run a continuous bus trace, dumping the raw data as soon as
	158	a ZBbus error is detected. Cannot work if ZBbus profiling
	159	is turned on, and also will interfere with JTAG-based trace
	160	buffer activity. Raw buffer data is dumped to console, and
	161	must be processed off-line.
	162
38b18f72	163	config SIBYTE_TBPROF
bb9b813b RB	164	tristate "Support for ZBbus profiling"
	165	depends on SIBYTE_HAS_ZBUS_PROFILING
	166
	167	config SIBYTE_HAS_ZBUS_PROFILING
	168	bool