[linux-2.6-block.git] / arch / mips / sibyte / Kconfig

config SIBYTE_SB1250
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select HW_HAS_PCI
	select IRQ_CPU
	select SIBYTE_ENABLE_LDT_IF_PCI
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC
	select SYS_SUPPORTS_SMP

config SIBYTE_BCM1120
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select IRQ_CPU
	select SIBYTE_BCM112X
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC

config SIBYTE_BCM1125
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select HW_HAS_PCI
	select IRQ_CPU
	select SIBYTE_BCM112X
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC

config SIBYTE_BCM1125H
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select HW_HAS_PCI
	select IRQ_CPU
	select SIBYTE_BCM112X
	select SIBYTE_ENABLE_LDT_IF_PCI
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC

config SIBYTE_BCM112X
	bool
	select CEVT_SB1250
	select CSRC_SB1250
	select IRQ_CPU
	select SIBYTE_SB1xxx_SOC
	select SIBYTE_HAS_ZBUS_PROFILING

config SIBYTE_BCM1x80
	bool
	select CEVT_BCM1480
	select CSRC_BCM1480
	select HW_HAS_PCI
	select IRQ_CPU
	select SIBYTE_HAS_ZBUS_PROFILING
	select SIBYTE_SB1xxx_SOC
	select SYS_SUPPORTS_SMP

config SIBYTE_BCM1x55
	bool
	select CEVT_BCM1480
	select CSRC_BCM1480
	select HW_HAS_PCI
	select IRQ_CPU
	select SIBYTE_SB1xxx_SOC
	select SIBYTE_HAS_ZBUS_PROFILING
	select SYS_SUPPORTS_SMP

config SIBYTE_SB1xxx_SOC
	bool
	select DMA_COHERENT
	select IRQ_CPU
	select SIBYTE_CFE
	select SWAP_IO_SPACE
	select SYS_SUPPORTS_32BIT_KERNEL
	select SYS_SUPPORTS_64BIT_KERNEL

choice
	prompt "SiByte SOC Stepping"
	depends on SIBYTE_SB1xxx_SOC

config CPU_SB1_PASS_1
	bool "1250 Pass1"
	depends on SIBYTE_SB1250
	select CPU_HAS_PREFETCH

config CPU_SB1_PASS_2_1250
	bool "1250 An"
	depends on SIBYTE_SB1250
	select CPU_SB1_PASS_2
	help
	  Also called BCM1250 Pass 2

config CPU_SB1_PASS_2_2
	bool "1250 Bn"
	depends on SIBYTE_SB1250
	select CPU_HAS_PREFETCH
	help
	  Also called BCM1250 Pass 2.2

config CPU_SB1_PASS_4
	bool "1250 Cn"
	depends on SIBYTE_SB1250
	select CPU_HAS_PREFETCH
	help
	  Also called BCM1250 Pass 3

config CPU_SB1_PASS_2_112x
	bool "112x Hybrid"
	depends on SIBYTE_BCM112X
	select CPU_SB1_PASS_2

config CPU_SB1_PASS_3
	bool "112x An"
	depends on SIBYTE_BCM112X
	select CPU_HAS_PREFETCH

endchoice

config CPU_SB1_PASS_2
	bool

config SIBYTE_HAS_LDT
	bool

config SIBYTE_ENABLE_LDT_IF_PCI
	bool
	select SIBYTE_HAS_LDT if PCI

config SB1_CEX_ALWAYS_FATAL
	bool "All cache exceptions considered fatal (no recovery attempted)"
	depends on SIBYTE_SB1xxx_SOC

config SB1_CERR_STALL
	bool "Stall (rather than panic) on fatal cache error"
	depends on SIBYTE_SB1xxx_SOC

config SIBYTE_CFE
	bool "Booting from CFE"
	depends on SIBYTE_SB1xxx_SOC
	select CFE
	select SYS_HAS_EARLY_PRINTK
	help
	  Make use of the CFE API for enumerating available memory,
	  controlling secondary CPUs, and possibly console output.

config SIBYTE_CFE_CONSOLE
	bool "Use firmware console"
	depends on SIBYTE_CFE
	help
	  Use the CFE API's console write routines during boot.  Other console
	  options (VT console, sb1250 duart console, etc.) should not be
	  configured.

config SIBYTE_STANDALONE
	bool
	depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
	select SYS_HAS_EARLY_PRINTK
	default y

config SIBYTE_STANDALONE_RAM_SIZE
	int "Memory size (in megabytes)"
	depends on SIBYTE_STANDALONE
	default "32"

config SIBYTE_BUS_WATCHER
	bool "Support for Bus Watcher statistics"
	depends on SIBYTE_SB1xxx_SOC
	help
	  Handle and keep statistics on the bus error interrupts (COR_ECC,
	  BAD_ECC, IO_BUS).

config SIBYTE_BW_TRACE
	bool "Capture bus trace before bus error"
	depends on SIBYTE_BUS_WATCHER
	help
	  Run a continuous bus trace, dumping the raw data as soon as
	  a ZBbus error is detected.  Cannot work if ZBbus profiling
	  is turned on, and also will interfere with JTAG-based trace
	  buffer activity.  Raw buffer data is dumped to console, and
	  must be processed off-line.

config SIBYTE_TBPROF
	tristate "Support for ZBbus profiling"
	depends on SIBYTE_HAS_ZBUS_PROFILING

config SIBYTE_HAS_ZBUS_PROFILING
	bool
Commit	Line	Data
38b18f72 RB	1	config SIBYTE_SB1250
38b18f72 RB	2	bool
217dd11e RB	3	select CEVT_SB1250
217dd11e RB	4	select CSRC_SB1250
38b18f72	5	select HW_HAS_PCI
7bcf7717	6	select IRQ_CPU
ca6f5494	7	select SIBYTE_ENABLE_LDT_IF_PCI
d619f38f	8	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72	9	select SIBYTE_SB1xxx_SOC
e73ea273	10	select SYS_SUPPORTS_SMP
38b18f72 RB	11
	12	config SIBYTE_BCM1120
	13	bool
217dd11e RB	14	select CEVT_SB1250
217dd11e RB	15	select CSRC_SB1250
7bcf7717	16	select IRQ_CPU
38b18f72	17	select SIBYTE_BCM112X
bb9b813b	18	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 RB	19	select SIBYTE_SB1xxx_SOC
	20
	21	config SIBYTE_BCM1125
	22	bool
217dd11e RB	23	select CEVT_SB1250
217dd11e RB	24	select CSRC_SB1250
38b18f72	25	select HW_HAS_PCI
7bcf7717	26	select IRQ_CPU
38b18f72	27	select SIBYTE_BCM112X
bb9b813b	28	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 RB	29	select SIBYTE_SB1xxx_SOC
	30
	31	config SIBYTE_BCM1125H
	32	bool
217dd11e RB	33	select CEVT_SB1250
217dd11e RB	34	select CSRC_SB1250
38b18f72	35	select HW_HAS_PCI
7bcf7717	36	select IRQ_CPU
38b18f72	37	select SIBYTE_BCM112X
ca6f5494	38	select SIBYTE_ENABLE_LDT_IF_PCI
bb9b813b	39	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72 RB	40	select SIBYTE_SB1xxx_SOC
	41
	42	config SIBYTE_BCM112X
	43	bool
217dd11e RB	44	select CEVT_SB1250
217dd11e RB	45	select CSRC_SB1250
7bcf7717	46	select IRQ_CPU
38b18f72	47	select SIBYTE_SB1xxx_SOC
bb9b813b	48	select SIBYTE_HAS_ZBUS_PROFILING
38b18f72	49
f137e463 AI	50	config SIBYTE_BCM1x80
f137e463 AI	51	bool
217dd11e RB	52	select CEVT_BCM1480
217dd11e RB	53	select CSRC_BCM1480
f137e463	54	select HW_HAS_PCI
7bcf7717	55	select IRQ_CPU
d619f38f	56	select SIBYTE_HAS_ZBUS_PROFILING
f137e463	57	select SIBYTE_SB1xxx_SOC
e73ea273	58	select SYS_SUPPORTS_SMP
f137e463 AI	59
	60	config SIBYTE_BCM1x55
	61	bool
217dd11e RB	62	select CEVT_BCM1480
217dd11e RB	63	select CSRC_BCM1480
f137e463	64	select HW_HAS_PCI
7bcf7717	65	select IRQ_CPU
f137e463	66	select SIBYTE_SB1xxx_SOC
bb9b813b	67	select SIBYTE_HAS_ZBUS_PROFILING
e73ea273	68	select SYS_SUPPORTS_SMP
f137e463	69
38b18f72 RB	70	config SIBYTE_SB1xxx_SOC
38b18f72 RB	71	bool
38b18f72	72	select DMA_COHERENT
7bcf7717	73	select IRQ_CPU
38b18f72 RB	74	select SIBYTE_CFE
	75	select SWAP_IO_SPACE
	76	select SYS_SUPPORTS_32BIT_KERNEL
	77	select SYS_SUPPORTS_64BIT_KERNEL
	78
	79	choice
	80	prompt "SiByte SOC Stepping"
	81	depends on SIBYTE_SB1xxx_SOC
	82
	83	config CPU_SB1_PASS_1
	84	bool "1250 Pass1"
	85	depends on SIBYTE_SB1250
	86	select CPU_HAS_PREFETCH
	87
	88	config CPU_SB1_PASS_2_1250
	89	bool "1250 An"
	90	depends on SIBYTE_SB1250
	91	select CPU_SB1_PASS_2
	92	help
	93	Also called BCM1250 Pass 2
	94
	95	config CPU_SB1_PASS_2_2
	96	bool "1250 Bn"
	97	depends on SIBYTE_SB1250
	98	select CPU_HAS_PREFETCH
	99	help
	100	Also called BCM1250 Pass 2.2
	101
	102	config CPU_SB1_PASS_4
	103	bool "1250 Cn"
	104	depends on SIBYTE_SB1250
	105	select CPU_HAS_PREFETCH
	106	help
	107	Also called BCM1250 Pass 3
	108
	109	config CPU_SB1_PASS_2_112x
	110	bool "112x Hybrid"
	111	depends on SIBYTE_BCM112X
	112	select CPU_SB1_PASS_2
	113
	114	config CPU_SB1_PASS_3
	115	bool "112x An"
	116	depends on SIBYTE_BCM112X
	117	select CPU_HAS_PREFETCH
	118
	119	endchoice
	120
	121	config CPU_SB1_PASS_2
	122	bool
	123
	124	config SIBYTE_HAS_LDT
	125	bool
ca6f5494 RB	126
	127	config SIBYTE_ENABLE_LDT_IF_PCI
	128	bool
	129	select SIBYTE_HAS_LDT if PCI
38b18f72	130
77607635	131	config SB1_CEX_ALWAYS_FATAL
a4b5bd9a AI	132	bool "All cache exceptions considered fatal (no recovery attempted)"
	133	depends on SIBYTE_SB1xxx_SOC
	134
77607635	135	config SB1_CERR_STALL
a4b5bd9a AI	136	bool "Stall (rather than panic) on fatal cache error"
	137	depends on SIBYTE_SB1xxx_SOC
	138
38b18f72 RB	139	config SIBYTE_CFE
	140	bool "Booting from CFE"
	141	depends on SIBYTE_SB1xxx_SOC
df78b5c8	142	select CFE
36a88530	143	select SYS_HAS_EARLY_PRINTK
38b18f72 RB	144	help
	145	Make use of the CFE API for enumerating available memory,
	146	controlling secondary CPUs, and possibly console output.
	147
	148	config SIBYTE_CFE_CONSOLE
	149	bool "Use firmware console"
	150	depends on SIBYTE_CFE
	151	help
	152	Use the CFE API's console write routines during boot. Other console
	153	options (VT console, sb1250 duart console, etc.) should not be
	154	configured.
	155
	156	config SIBYTE_STANDALONE
	157	bool
	158	depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
36a88530	159	select SYS_HAS_EARLY_PRINTK
38b18f72 RB	160	default y
	161
	162	config SIBYTE_STANDALONE_RAM_SIZE
	163	int "Memory size (in megabytes)"
	164	depends on SIBYTE_STANDALONE
	165	default "32"
	166
	167	config SIBYTE_BUS_WATCHER
	168	bool "Support for Bus Watcher statistics"
	169	depends on SIBYTE_SB1xxx_SOC
	170	help
	171	Handle and keep statistics on the bus error interrupts (COR_ECC,
	172	BAD_ECC, IO_BUS).
	173
	174	config SIBYTE_BW_TRACE
	175	bool "Capture bus trace before bus error"
	176	depends on SIBYTE_BUS_WATCHER
	177	help
	178	Run a continuous bus trace, dumping the raw data as soon as
	179	a ZBbus error is detected. Cannot work if ZBbus profiling
	180	is turned on, and also will interfere with JTAG-based trace
	181	buffer activity. Raw buffer data is dumped to console, and
	182	must be processed off-line.
	183
38b18f72	184	config SIBYTE_TBPROF
bb9b813b RB	185	tristate "Support for ZBbus profiling"
	186	depends on SIBYTE_HAS_ZBUS_PROFILING
	187
	188	config SIBYTE_HAS_ZBUS_PROFILING
	189	bool