[linux-2.6-block.git] / arch / mips / rb532 / gpio.c

/*
 *  Miscellaneous functions for IDT EB434 board
 *
 *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 *  Copyright 2006 Phil Sutter <n0-1@freewrt.org>
 *  Copyright 2007 Florian Fainelli <florian@openwrt.org>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <asm/mach-rc32434/rb.h>
#include <asm/mach-rc32434/gpio.h>

struct rb532_gpio_chip {
	struct gpio_chip chip;
	void __iomem	 *regbase;
	void		(*set_int_level)(struct gpio_chip *chip, unsigned offset, int value);
	int		(*get_int_level)(struct gpio_chip *chip, unsigned offset);
	void		(*set_int_status)(struct gpio_chip *chip, unsigned offset, int value);
	int		(*get_int_status)(struct gpio_chip *chip, unsigned offset);
};

struct mpmc_device dev3;

static struct resource rb532_gpio_reg0_res[] = {
	{
		.name 	= "gpio_reg0",
		.start 	= REGBASE + GPIOBASE,
		.end 	= REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
		.flags 	= IORESOURCE_MEM,
	}
};

static struct resource rb532_dev3_ctl_res[] = {
	{
		.name	= "dev3_ctl",
		.start	= REGBASE + DEV3BASE,
		.end	= REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
		.flags	= IORESOURCE_MEM,
	}
};

void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
{
	unsigned long flags;
	unsigned data;
	unsigned i = 0;

	spin_lock_irqsave(&dev3.lock, flags);

	data = readl(IDT434_REG_BASE + reg_offs);
	for (i = 0; i != len; ++i) {
		if (val & (1 << i))
			data |= (1 << (i + bit));
		else
			data &= ~(1 << (i + bit));
	}
	writel(data, (IDT434_REG_BASE + reg_offs));

	spin_unlock_irqrestore(&dev3.lock, flags);
}
EXPORT_SYMBOL(set_434_reg);

unsigned get_434_reg(unsigned reg_offs)
{
	return readl(IDT434_REG_BASE + reg_offs);
}
EXPORT_SYMBOL(get_434_reg);

void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
{
	unsigned long flags;

	spin_lock_irqsave(&dev3.lock, flags);

	dev3.state = (dev3.state | or_mask) & ~nand_mask;
	writel(dev3.state, &dev3.base);

	spin_unlock_irqrestore(&dev3.lock, flags);
}
EXPORT_SYMBOL(set_latch_u5);

unsigned char get_latch_u5(void)
{
	return dev3.state;
}
EXPORT_SYMBOL(get_latch_u5);

/*
 * Return GPIO level */
static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	u32			mask = 1 << offset;
	struct rb532_gpio_chip	*gpch;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	return readl(gpch->regbase + GPIOD) & mask;
}

/*
 * Set output GPIO level
 */
static void rb532_gpio_set(struct gpio_chip *chip,
				unsigned offset, int value)
{
	unsigned long		flags;
	u32			mask = 1 << offset;
	u32			tmp;
	struct rb532_gpio_chip	*gpch;
	void __iomem		*gpvr;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	gpvr = gpch->regbase + GPIOD;

	local_irq_save(flags);
	tmp = readl(gpvr);
	if (value)
		tmp |= mask;
	else
		tmp &= ~mask;
	writel(tmp, gpvr);
	local_irq_restore(flags);
}

/*
 * Set GPIO direction to input
 */
static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	unsigned long		flags;
	u32			mask = 1 << offset;
	u32			value;
	struct rb532_gpio_chip	*gpch;
	void __iomem		*gpdr;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	gpdr = gpch->regbase + GPIOCFG;

	local_irq_save(flags);
	value = readl(gpdr);
	value &= ~mask;
	writel(value, gpdr);
	local_irq_restore(flags);

	return 0;
}

/*
 * Set GPIO direction to output
 */
static int rb532_gpio_direction_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	unsigned long		flags;
	u32			mask = 1 << offset;
	u32			tmp;
	struct rb532_gpio_chip	*gpch;
	void __iomem		*gpdr;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	writel(mask, gpch->regbase + GPIOD);
	gpdr = gpch->regbase + GPIOCFG;

	local_irq_save(flags);
	tmp = readl(gpdr);
	tmp |= mask;
	writel(tmp, gpdr);
	local_irq_restore(flags);

	return 0;
}

/*
 * Set the GPIO interrupt level
 */
static void rb532_gpio_set_int_level(struct gpio_chip *chip,
					unsigned offset, int value)
{
	unsigned long		flags;
	u32			mask = 1 << offset;
	u32			tmp;
	struct rb532_gpio_chip	*gpch;
	void __iomem		*gpil;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	gpil = gpch->regbase + GPIOILEVEL;

	local_irq_save(flags);
	tmp = readl(gpil);
	if (value)
		tmp |= mask;
	else
		tmp &= ~mask;
	writel(tmp, gpil);
	local_irq_restore(flags);
}

/*
 * Get the GPIO interrupt level
 */
static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset)
{
	u32			mask = 1 << offset;
	struct rb532_gpio_chip	*gpch;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	return readl(gpch->regbase + GPIOILEVEL) & mask;
}

/*
 * Set the GPIO interrupt status
 */
static void rb532_gpio_set_int_status(struct gpio_chip *chip,
				unsigned offset, int value)
{
	unsigned long		flags;
	u32			mask = 1 << offset;
	u32			tmp;
	struct rb532_gpio_chip	*gpch;
	void __iomem		*gpis;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	gpis = gpch->regbase + GPIOISTAT;

	local_irq_save(flags);
	tmp = readl(gpis);
	if (value)
		tmp |= mask;
	else
		tmp &= ~mask;
	writel(tmp, gpis);
	local_irq_restore(flags);
}

/*
 * Get the GPIO interrupt status
 */
static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset)
{
	u32			mask = 1 << offset;
	struct rb532_gpio_chip	*gpch;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	return readl(gpch->regbase + GPIOISTAT) & mask;
}

static struct rb532_gpio_chip rb532_gpio_chip[] = {
	[0] = {
		.chip = {
			.label			= "gpio0",
			.direction_input	= rb532_gpio_direction_input,
			.direction_output	= rb532_gpio_direction_output,
			.get			= rb532_gpio_get,
			.set			= rb532_gpio_set,
			.base			= 0,
			.ngpio			= 32,
		},
		.get_int_level		= rb532_gpio_get_int_level,
		.set_int_level		= rb532_gpio_set_int_level,
		.get_int_status		= rb532_gpio_get_int_status,
		.set_int_status		= rb532_gpio_set_int_status,
	},
};

int __init rb532_gpio_init(void)
{
	struct resource *r;

	r = rb532_gpio_reg0_res;
	rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);

	if (!rb532_gpio_chip->regbase) {
		printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
		return -ENXIO;
	}

	/* Register our GPIO chip */
	gpiochip_add(&rb532_gpio_chip->chip);

	r = rb532_dev3_ctl_res;
	dev3.base = ioremap_nocache(r->start, r->end - r->start);

	if (!dev3.base) {
		printk(KERN_ERR "rb532: cannot remap device controller 3\n");
		return -ENXIO;
	}

	/* Set the interrupt status and level for the CF pin */
	rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1);
	rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0);

	return 0;
}
arch_initcall(rb532_gpio_init);
Commit	Line	Data
73b4390f RB	1	/*
	2	* Miscellaneous functions for IDT EB434 board
	3	*
	4	* Copyright 2004 IDT Inc. (rischelp@idt.com)
	5	* Copyright 2006 Phil Sutter <n0-1@freewrt.org>
	6	* Copyright 2007 Florian Fainelli <florian@openwrt.org>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	14	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	15	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	16	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	17	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	18	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	19	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	20	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	21	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	22	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	23	*
	24	* You should have received a copy of the GNU General Public License along
	25	* with this program; if not, write to the Free Software Foundation, Inc.,
	26	* 675 Mass Ave, Cambridge, MA 02139, USA.
	27	*/
	28
	29	#include <linux/kernel.h>
73b4390f RB	30	#include <linux/init.h>
73b4390f RB	31	#include <linux/types.h>
73b4390f	32	#include <linux/spinlock.h>
73b4390f	33	#include <linux/platform_device.h>
d888e25b	34	#include <linux/gpio.h>
73b4390f RB	35
73b4390f RB	36	#include <asm/mach-rc32434/rb.h>
d888e25b FF	37	#include <asm/mach-rc32434/gpio.h>
	38
	39	struct rb532_gpio_chip {
	40	struct gpio_chip chip;
	41	void __iomem *regbase;
	42	void (set_int_level)(struct gpio_chip chip, unsigned offset, int value);
	43	int (get_int_level)(struct gpio_chip chip, unsigned offset);
	44	void (set_int_status)(struct gpio_chip chip, unsigned offset, int value);
	45	int (get_int_status)(struct gpio_chip chip, unsigned offset);
	46	};
73b4390f RB	47
	48	struct mpmc_device dev3;
	49
	50	static struct resource rb532_gpio_reg0_res[] = {
	51	{
	52	.name = "gpio_reg0",
3c8cf8ca FF	53	.start = REGBASE + GPIOBASE,
3c8cf8ca FF	54	.end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
73b4390f RB	55	.flags = IORESOURCE_MEM,
	56	}
	57	};
	58
	59	static struct resource rb532_dev3_ctl_res[] = {
	60	{
	61	.name = "dev3_ctl",
3c8cf8ca FF	62	.start = REGBASE + DEV3BASE,
3c8cf8ca FF	63	.end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
73b4390f RB	64	.flags = IORESOURCE_MEM,
	65	}
	66	};
	67
	68	void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
	69	{
8b32d6d0 AB	70	unsigned long flags;
8b32d6d0 AB	71	unsigned data;
73b4390f RB	72	unsigned i = 0;
	73
	74	spin_lock_irqsave(&dev3.lock, flags);
	75
c76befc3	76	data = readl(IDT434_REG_BASE + reg_offs);
73b4390f RB	77	for (i = 0; i != len; ++i) {
	78	if (val & (1 << i))
	79	data \|= (1 << (i + bit));
	80	else
	81	data &= ~(1 << (i + bit));
	82	}
	83	writel(data, (IDT434_REG_BASE + reg_offs));
	84
	85	spin_unlock_irqrestore(&dev3.lock, flags);
	86	}
	87	EXPORT_SYMBOL(set_434_reg);
	88
	89	unsigned get_434_reg(unsigned reg_offs)
	90	{
	91	return readl(IDT434_REG_BASE + reg_offs);
	92	}
	93	EXPORT_SYMBOL(get_434_reg);
	94
	95	void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
	96	{
8b32d6d0	97	unsigned long flags;
73b4390f RB	98
	99	spin_lock_irqsave(&dev3.lock, flags);
	100
	101	dev3.state = (dev3.state \| or_mask) & ~nand_mask;
	102	writel(dev3.state, &dev3.base);
	103
	104	spin_unlock_irqrestore(&dev3.lock, flags);
	105	}
	106	EXPORT_SYMBOL(set_latch_u5);
	107
	108	unsigned char get_latch_u5(void)
	109	{
	110	return dev3.state;
	111	}
	112	EXPORT_SYMBOL(get_latch_u5);
	113
d888e25b FF	114	/*
	115	* Return GPIO level */
	116	static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
73b4390f	117	{
d888e25b FF	118	u32 mask = 1 << offset;
	119	struct rb532_gpio_chip *gpch;
	120
	121	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	122	return readl(gpch->regbase + GPIOD) & mask;
73b4390f	123	}
73b4390f	124
d888e25b FF	125	/*
	126	* Set output GPIO level
	127	*/
	128	static void rb532_gpio_set(struct gpio_chip *chip,
	129	unsigned offset, int value)
73b4390f	130	{
d888e25b FF	131	unsigned long flags;
	132	u32 mask = 1 << offset;
	133	u32 tmp;
	134	struct rb532_gpio_chip *gpch;
	135	void __iomem *gpvr;
73b4390f	136
d888e25b FF	137	gpch = container_of(chip, struct rb532_gpio_chip, chip);
d888e25b FF	138	gpvr = gpch->regbase + GPIOD;
73b4390f	139
d888e25b FF	140	local_irq_save(flags);
	141	tmp = readl(gpvr);
	142	if (value)
	143	tmp \|= mask;
	144	else
	145	tmp &= ~mask;
	146	writel(tmp, gpvr);
	147	local_irq_restore(flags);
73b4390f	148	}
73b4390f	149
d888e25b FF	150	/*
	151	* Set GPIO direction to input
	152	*/
	153	static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
73b4390f	154	{
d888e25b FF	155	unsigned long flags;
	156	u32 mask = 1 << offset;
	157	u32 value;
	158	struct rb532_gpio_chip *gpch;
	159	void __iomem *gpdr;
73b4390f	160
d888e25b FF	161	gpch = container_of(chip, struct rb532_gpio_chip, chip);
d888e25b FF	162	gpdr = gpch->regbase + GPIOCFG;
73b4390f	163
d888e25b FF	164	local_irq_save(flags);
	165	value = readl(gpdr);
	166	value &= ~mask;
	167	writel(value, gpdr);
	168	local_irq_restore(flags);
73b4390f RB	169
	170	return 0;
	171	}
73b4390f	172
d888e25b FF	173	/*
	174	* Set GPIO direction to output
	175	*/
	176	static int rb532_gpio_direction_output(struct gpio_chip *chip,
	177	unsigned offset, int value)
73b4390f	178	{
d888e25b FF	179	unsigned long flags;
	180	u32 mask = 1 << offset;
	181	u32 tmp;
	182	struct rb532_gpio_chip *gpch;
	183	void __iomem *gpdr;
	184
	185	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	186	writel(mask, gpch->regbase + GPIOD);
	187	gpdr = gpch->regbase + GPIOCFG;
	188
	189	local_irq_save(flags);
	190	tmp = readl(gpdr);
	191	tmp \|= mask;
	192	writel(tmp, gpdr);
	193	local_irq_restore(flags);
73b4390f	194
d888e25b	195	return 0;
73b4390f	196	}
73b4390f	197
d888e25b FF	198	/*
	199	* Set the GPIO interrupt level
	200	*/
	201	static void rb532_gpio_set_int_level(struct gpio_chip *chip,
	202	unsigned offset, int value)
73b4390f	203	{
d888e25b FF	204	unsigned long flags;
	205	u32 mask = 1 << offset;
	206	u32 tmp;
	207	struct rb532_gpio_chip *gpch;
	208	void __iomem *gpil;
73b4390f	209
d888e25b FF	210	gpch = container_of(chip, struct rb532_gpio_chip, chip);
d888e25b FF	211	gpil = gpch->regbase + GPIOILEVEL;
73b4390f	212
d888e25b FF	213	local_irq_save(flags);
d888e25b FF	214	tmp = readl(gpil);
73b4390f	215	if (value)
d888e25b FF	216	tmp \|= mask;
	217	else
	218	tmp &= ~mask;
	219	writel(tmp, gpil);
	220	local_irq_restore(flags);
73b4390f	221	}
73b4390f	222
d888e25b FF	223	/*
	224	* Get the GPIO interrupt level
	225	*/
	226	static int rb532_gpio_get_int_level(struct gpio_chip *chip, unsigned offset)
73b4390f	227	{
d888e25b FF	228	u32 mask = 1 << offset;
	229	struct rb532_gpio_chip *gpch;
	230
	231	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	232	return readl(gpch->regbase + GPIOILEVEL) & mask;
73b4390f	233	}
73b4390f	234
d888e25b FF	235	/*
	236	* Set the GPIO interrupt status
	237	*/
	238	static void rb532_gpio_set_int_status(struct gpio_chip *chip,
	239	unsigned offset, int value)
73b4390f	240	{
d888e25b FF	241	unsigned long flags;
	242	u32 mask = 1 << offset;
	243	u32 tmp;
	244	struct rb532_gpio_chip *gpch;
	245	void __iomem *gpis;
	246
	247	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	248	gpis = gpch->regbase + GPIOISTAT;
73b4390f	249
d888e25b FF	250	local_irq_save(flags);
d888e25b FF	251	tmp = readl(gpis);
73b4390f	252	if (value)
d888e25b FF	253	tmp \|= mask;
	254	else
	255	tmp &= ~mask;
	256	writel(tmp, gpis);
	257	local_irq_restore(flags);
73b4390f	258	}
73b4390f	259
d888e25b FF	260	/*
	261	* Get the GPIO interrupt status
	262	*/
	263	static int rb532_gpio_get_int_status(struct gpio_chip *chip, unsigned offset)
73b4390f	264	{
d888e25b FF	265	u32 mask = 1 << offset;
	266	struct rb532_gpio_chip *gpch;
	267
	268	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	269	return readl(gpch->regbase + GPIOISTAT) & mask;
73b4390f	270	}
d888e25b FF	271
	272	static struct rb532_gpio_chip rb532_gpio_chip[] = {
	273	[0] = {
	274	.chip = {
	275	.label = "gpio0",
	276	.direction_input = rb532_gpio_direction_input,
	277	.direction_output = rb532_gpio_direction_output,
	278	.get = rb532_gpio_get,
	279	.set = rb532_gpio_set,
	280	.base = 0,
	281	.ngpio = 32,
	282	},
	283	.get_int_level = rb532_gpio_get_int_level,
	284	.set_int_level = rb532_gpio_set_int_level,
	285	.get_int_status = rb532_gpio_get_int_status,
	286	.set_int_status = rb532_gpio_set_int_status,
	287	},
	288	};
73b4390f RB	289
	290	int __init rb532_gpio_init(void)
	291	{
d888e25b	292	struct resource *r;
73b4390f	293
d888e25b FF	294	r = rb532_gpio_reg0_res;
	295	rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);
	296
	297	if (!rb532_gpio_chip->regbase) {
73b4390f RB	298	printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
	299	return -ENXIO;
	300	}
	301
d888e25b FF	302	/* Register our GPIO chip */
	303	gpiochip_add(&rb532_gpio_chip->chip);
	304
	305	r = rb532_dev3_ctl_res;
	306	dev3.base = ioremap_nocache(r->start, r->end - r->start);
73b4390f RB	307
	308	if (!dev3.base) {
	309	printk(KERN_ERR "rb532: cannot remap device controller 3\n");
	310	return -ENXIO;
	311	}
	312
fa36b043 FF	313	/* Set the interrupt status and level for the CF pin */
	314	rb532_gpio_set_int_level(&rb532_gpio_chip->chip, CF_GPIO_NUM, 1);
	315	rb532_gpio_set_int_status(&rb532_gpio_chip->chip, CF_GPIO_NUM, 0);
	316
73b4390f RB	317	return 0;
	318	}
	319	arch_initcall(rb532_gpio_init);