[linux-2.6-block.git] / arch / mips / rb532 / gpio.c

/*
 *  Miscellaneous functions for IDT EB434 board
 *
 *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 *  Copyright 2006 Phil Sutter <n0-1@freewrt.org>
 *  Copyright 2007 Florian Fainelli <florian@openwrt.org>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <asm/mach-rc32434/rb.h>
#include <asm/mach-rc32434/gpio.h>

struct rb532_gpio_chip {
	struct gpio_chip chip;
	void __iomem	 *regbase;
};

struct mpmc_device dev3;

static struct resource rb532_gpio_reg0_res[] = {
	{
		.name 	= "gpio_reg0",
		.start 	= REGBASE + GPIOBASE,
		.end 	= REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
		.flags 	= IORESOURCE_MEM,
	}
};

static struct resource rb532_dev3_ctl_res[] = {
	{
		.name	= "dev3_ctl",
		.start	= REGBASE + DEV3BASE,
		.end	= REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
		.flags	= IORESOURCE_MEM,
	}
};

void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
{
	unsigned long flags;
	unsigned data;
	unsigned i = 0;

	spin_lock_irqsave(&dev3.lock, flags);

	data = readl(IDT434_REG_BASE + reg_offs);
	for (i = 0; i != len; ++i) {
		if (val & (1 << i))
			data |= (1 << (i + bit));
		else
			data &= ~(1 << (i + bit));
	}
	writel(data, (IDT434_REG_BASE + reg_offs));

	spin_unlock_irqrestore(&dev3.lock, flags);
}
EXPORT_SYMBOL(set_434_reg);

unsigned get_434_reg(unsigned reg_offs)
{
	return readl(IDT434_REG_BASE + reg_offs);
}
EXPORT_SYMBOL(get_434_reg);

void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
{
	unsigned long flags;

	spin_lock_irqsave(&dev3.lock, flags);

	dev3.state = (dev3.state | or_mask) & ~nand_mask;
	writel(dev3.state, &dev3.base);

	spin_unlock_irqrestore(&dev3.lock, flags);
}
EXPORT_SYMBOL(set_latch_u5);

unsigned char get_latch_u5(void)
{
	return dev3.state;
}
EXPORT_SYMBOL(get_latch_u5);

/* rb532_set_bit - sanely set a bit
 *
 * bitval: new value for the bit
 * offset: bit index in the 4 byte address range
 * ioaddr: 4 byte aligned address being altered
 */
static inline void rb532_set_bit(unsigned bitval,
		unsigned offset, void __iomem *ioaddr)
{
	unsigned long flags;
	u32 val;

	local_irq_save(flags);

	val = readl(ioaddr);
	val &= ~(!bitval << offset);   /* unset bit if bitval == 0 */
	val |= (!!bitval << offset);   /* set bit if bitval == 1 */
	writel(val, ioaddr);

	local_irq_restore(flags);
}

/* rb532_get_bit - read a bit
 *
 * returns the boolean state of the bit, which may be > 1
 */
static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
{
	return (readl(ioaddr) & (1 << offset));
}

/*
 * Return GPIO level */
static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct rb532_gpio_chip	*gpch;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	return rb532_get_bit(offset, gpch->regbase + GPIOD);
}

/*
 * Set output GPIO level
 */
static void rb532_gpio_set(struct gpio_chip *chip,
				unsigned offset, int value)
{
	struct rb532_gpio_chip	*gpch;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);
	rb532_set_bit(value, offset, gpch->regbase + GPIOD);
}

/*
 * Set GPIO direction to input
 */
static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct rb532_gpio_chip	*gpch;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);

	if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
		return 1;	/* alternate function, GPIOCFG is ignored */

	rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
	return 0;
}

/*
 * Set GPIO direction to output
 */
static int rb532_gpio_direction_output(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct rb532_gpio_chip	*gpch;

	gpch = container_of(chip, struct rb532_gpio_chip, chip);

	if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
		return 1;	/* alternate function, GPIOCFG is ignored */

	/* set the initial output value */
	rb532_set_bit(value, offset, gpch->regbase + GPIOD);

	rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
	return 0;
}

static struct rb532_gpio_chip rb532_gpio_chip[] = {
	[0] = {
		.chip = {
			.label			= "gpio0",
			.direction_input	= rb532_gpio_direction_input,
			.direction_output	= rb532_gpio_direction_output,
			.get			= rb532_gpio_get,
			.set			= rb532_gpio_set,
			.base			= 0,
			.ngpio			= 32,
		},
	},
};

/*
 * Set GPIO interrupt level
 */
void rb532_gpio_set_ilevel(int bit, unsigned gpio)
{
	rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
}
EXPORT_SYMBOL(rb532_gpio_set_ilevel);

/*
 * Set GPIO interrupt status
 */
void rb532_gpio_set_istat(int bit, unsigned gpio)
{
	rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
}
EXPORT_SYMBOL(rb532_gpio_set_istat);

/*
 * Configure GPIO alternate function
 */
static void rb532_gpio_set_func(int bit, unsigned gpio)
{
       rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
}

int __init rb532_gpio_init(void)
{
	struct resource *r;

	r = rb532_gpio_reg0_res;
	rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);

	if (!rb532_gpio_chip->regbase) {
		printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
		return -ENXIO;
	}

	/* Register our GPIO chip */
	gpiochip_add(&rb532_gpio_chip->chip);

	r = rb532_dev3_ctl_res;
	dev3.base = ioremap_nocache(r->start, r->end - r->start);

	if (!dev3.base) {
		printk(KERN_ERR "rb532: cannot remap device controller 3\n");
		return -ENXIO;
	}

	/* configure CF_GPIO_NUM as CFRDY IRQ source */
	rb532_gpio_set_func(0, CF_GPIO_NUM);
	rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
	rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
	rb532_gpio_set_istat(0, CF_GPIO_NUM);

	return 0;
}
arch_initcall(rb532_gpio_init);
Commit	Line	Data
73b4390f RB	1	/*
	2	* Miscellaneous functions for IDT EB434 board
	3	*
	4	* Copyright 2004 IDT Inc. (rischelp@idt.com)
	5	* Copyright 2006 Phil Sutter <n0-1@freewrt.org>
	6	* Copyright 2007 Florian Fainelli <florian@openwrt.org>
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	14	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	15	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	16	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	17	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	18	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	19	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	20	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	21	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	22	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	23	*
	24	* You should have received a copy of the GNU General Public License along
	25	* with this program; if not, write to the Free Software Foundation, Inc.,
	26	* 675 Mass Ave, Cambridge, MA 02139, USA.
	27	*/
	28
	29	#include <linux/kernel.h>
73b4390f RB	30	#include <linux/init.h>
73b4390f RB	31	#include <linux/types.h>
73b4390f	32	#include <linux/spinlock.h>
73b4390f	33	#include <linux/platform_device.h>
d888e25b	34	#include <linux/gpio.h>
73b4390f RB	35
73b4390f RB	36	#include <asm/mach-rc32434/rb.h>
d888e25b FF	37	#include <asm/mach-rc32434/gpio.h>
	38
	39	struct rb532_gpio_chip {
	40	struct gpio_chip chip;
	41	void __iomem *regbase;
d888e25b	42	};
73b4390f RB	43
	44	struct mpmc_device dev3;
	45
	46	static struct resource rb532_gpio_reg0_res[] = {
	47	{
	48	.name = "gpio_reg0",
3c8cf8ca FF	49	.start = REGBASE + GPIOBASE,
3c8cf8ca FF	50	.end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
73b4390f RB	51	.flags = IORESOURCE_MEM,
	52	}
	53	};
	54
	55	static struct resource rb532_dev3_ctl_res[] = {
	56	{
	57	.name = "dev3_ctl",
3c8cf8ca FF	58	.start = REGBASE + DEV3BASE,
3c8cf8ca FF	59	.end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
73b4390f RB	60	.flags = IORESOURCE_MEM,
	61	}
	62	};
	63
	64	void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
	65	{
8b32d6d0 AB	66	unsigned long flags;
8b32d6d0 AB	67	unsigned data;
73b4390f RB	68	unsigned i = 0;
	69
	70	spin_lock_irqsave(&dev3.lock, flags);
	71
c76befc3	72	data = readl(IDT434_REG_BASE + reg_offs);
73b4390f RB	73	for (i = 0; i != len; ++i) {
	74	if (val & (1 << i))
	75	data \|= (1 << (i + bit));
	76	else
	77	data &= ~(1 << (i + bit));
	78	}
	79	writel(data, (IDT434_REG_BASE + reg_offs));
	80
	81	spin_unlock_irqrestore(&dev3.lock, flags);
	82	}
	83	EXPORT_SYMBOL(set_434_reg);
	84
	85	unsigned get_434_reg(unsigned reg_offs)
	86	{
	87	return readl(IDT434_REG_BASE + reg_offs);
	88	}
	89	EXPORT_SYMBOL(get_434_reg);
	90
	91	void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
	92	{
8b32d6d0	93	unsigned long flags;
73b4390f RB	94
	95	spin_lock_irqsave(&dev3.lock, flags);
	96
	97	dev3.state = (dev3.state \| or_mask) & ~nand_mask;
	98	writel(dev3.state, &dev3.base);
	99
	100	spin_unlock_irqrestore(&dev3.lock, flags);
	101	}
	102	EXPORT_SYMBOL(set_latch_u5);
	103
	104	unsigned char get_latch_u5(void)
	105	{
	106	return dev3.state;
	107	}
	108	EXPORT_SYMBOL(get_latch_u5);
	109
2e373952 PS	110	/* rb532_set_bit - sanely set a bit
	111	*
	112	* bitval: new value for the bit
	113	* offset: bit index in the 4 byte address range
	114	* ioaddr: 4 byte aligned address being altered
	115	*/
	116	static inline void rb532_set_bit(unsigned bitval,
	117	unsigned offset, void __iomem *ioaddr)
	118	{
	119	unsigned long flags;
	120	u32 val;
	121
2e373952 PS	122	local_irq_save(flags);
	123
	124	val = readl(ioaddr);
5379a5fd PS	125	val &= ~(!bitval << offset); /* unset bit if bitval == 0 */
5379a5fd PS	126	val \|= (!!bitval << offset); /* set bit if bitval == 1 */
2e373952 PS	127	writel(val, ioaddr);
	128
	129	local_irq_restore(flags);
	130	}
	131
	132	/* rb532_get_bit - read a bit
	133	*
	134	* returns the boolean state of the bit, which may be > 1
	135	*/
	136	static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
	137	{
	138	return (readl(ioaddr) & (1 << offset));
	139	}
	140
d888e25b FF	141	/*
	142	* Return GPIO level */
	143	static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
73b4390f	144	{
d888e25b FF	145	struct rb532_gpio_chip *gpch;
	146
	147	gpch = container_of(chip, struct rb532_gpio_chip, chip);
2e373952	148	return rb532_get_bit(offset, gpch->regbase + GPIOD);
73b4390f	149	}
73b4390f	150
d888e25b FF	151	/*
	152	* Set output GPIO level
	153	*/
	154	static void rb532_gpio_set(struct gpio_chip *chip,
	155	unsigned offset, int value)
73b4390f	156	{
d888e25b	157	struct rb532_gpio_chip *gpch;
73b4390f	158
d888e25b	159	gpch = container_of(chip, struct rb532_gpio_chip, chip);
2e373952	160	rb532_set_bit(value, offset, gpch->regbase + GPIOD);
73b4390f	161	}
73b4390f	162
d888e25b FF	163	/*
	164	* Set GPIO direction to input
	165	*/
	166	static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
73b4390f	167	{
d888e25b	168	struct rb532_gpio_chip *gpch;
73b4390f	169
d888e25b	170	gpch = container_of(chip, struct rb532_gpio_chip, chip);
73b4390f	171
2e373952 PS	172	if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
2e373952 PS	173	return 1; /* alternate function, GPIOCFG is ignored */
73b4390f	174
2e373952	175	rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
73b4390f RB	176	return 0;
73b4390f RB	177	}
73b4390f	178
d888e25b FF	179	/*
	180	* Set GPIO direction to output
	181	*/
	182	static int rb532_gpio_direction_output(struct gpio_chip *chip,
	183	unsigned offset, int value)
73b4390f	184	{
d888e25b	185	struct rb532_gpio_chip *gpch;
d888e25b FF	186
d888e25b FF	187	gpch = container_of(chip, struct rb532_gpio_chip, chip);
d888e25b	188
2e373952 PS	189	if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
2e373952 PS	190	return 1; /* alternate function, GPIOCFG is ignored */
73b4390f	191
2e373952 PS	192	/* set the initial output value */
	193	rb532_set_bit(value, offset, gpch->regbase + GPIOD);
	194
	195	rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
d888e25b	196	return 0;
73b4390f	197	}
73b4390f	198
2e373952 PS	199	static struct rb532_gpio_chip rb532_gpio_chip[] = {
	200	[0] = {
	201	.chip = {
	202	.label = "gpio0",
	203	.direction_input = rb532_gpio_direction_input,
	204	.direction_output = rb532_gpio_direction_output,
	205	.get = rb532_gpio_get,
	206	.set = rb532_gpio_set,
	207	.base = 0,
	208	.ngpio = 32,
	209	},
	210	},
	211	};
73b4390f	212
d888e25b	213	/*
2e373952	214	* Set GPIO interrupt level
d888e25b	215	*/
2e373952	216	void rb532_gpio_set_ilevel(int bit, unsigned gpio)
73b4390f	217	{
2e373952	218	rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
73b4390f	219	}
2e373952	220	EXPORT_SYMBOL(rb532_gpio_set_ilevel);
73b4390f	221
d888e25b	222	/*
2e373952	223	* Set GPIO interrupt status
d888e25b	224	*/
2e373952	225	void rb532_gpio_set_istat(int bit, unsigned gpio)
73b4390f	226	{
2e373952	227	rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
73b4390f	228	}
2e373952	229	EXPORT_SYMBOL(rb532_gpio_set_istat);
73b4390f	230
d888e25b	231	/*
2e373952	232	* Configure GPIO alternate function
d888e25b	233	*/
2e373952	234	static void rb532_gpio_set_func(int bit, unsigned gpio)
73b4390f	235	{
2e373952	236	rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
73b4390f	237	}
d888e25b	238
73b4390f RB	239	int __init rb532_gpio_init(void)
73b4390f RB	240	{
d888e25b	241	struct resource *r;
73b4390f	242
d888e25b FF	243	r = rb532_gpio_reg0_res;
	244	rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);
	245
	246	if (!rb532_gpio_chip->regbase) {
73b4390f RB	247	printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
	248	return -ENXIO;
	249	}
	250
d888e25b FF	251	/* Register our GPIO chip */
	252	gpiochip_add(&rb532_gpio_chip->chip);
	253
	254	r = rb532_dev3_ctl_res;
	255	dev3.base = ioremap_nocache(r->start, r->end - r->start);
73b4390f RB	256
	257	if (!dev3.base) {
	258	printk(KERN_ERR "rb532: cannot remap device controller 3\n");
	259	return -ENXIO;
	260	}
	261
2e373952 PS	262	/* configure CF_GPIO_NUM as CFRDY IRQ source */
	263	rb532_gpio_set_func(0, CF_GPIO_NUM);
	264	rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
	265	rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
	266	rb532_gpio_set_istat(0, CF_GPIO_NUM);
fa36b043	267
73b4390f RB	268	return 0;
	269	}
	270	arch_initcall(rb532_gpio_init);