Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
c06e836a | 2 | /* |
c06e836a JC |
3 | * |
4 | * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org> | |
5 | * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> | |
97b92108 | 6 | * Copyright (C) 2013 John Crispin <john@phrozen.org> |
c06e836a JC |
7 | */ |
8 | ||
9 | #include <linux/pm.h> | |
10 | #include <linux/io.h> | |
2a153f1c | 11 | #include <linux/of.h> |
1a935205 | 12 | #include <linux/delay.h> |
c06e836a JC |
13 | |
14 | #include <asm/reboot.h> | |
15 | ||
16 | #include <asm/mach-ralink/ralink_regs.h> | |
17 | ||
18 | /* Reset Control */ | |
1a935205 JC |
19 | #define SYSC_REG_RESET_CTRL 0x034 |
20 | ||
21 | #define RSTCTL_RESET_PCI BIT(26) | |
22 | #define RSTCTL_RESET_SYSTEM BIT(0) | |
c06e836a JC |
23 | |
24 | static void ralink_restart(char *command) | |
25 | { | |
1a935205 JC |
26 | if (IS_ENABLED(CONFIG_PCI)) { |
27 | rt_sysc_m32(0, RSTCTL_RESET_PCI, SYSC_REG_RESET_CTRL); | |
28 | mdelay(50); | |
29 | } | |
30 | ||
c06e836a JC |
31 | local_irq_disable(); |
32 | rt_sysc_w32(RSTCTL_RESET_SYSTEM, SYSC_REG_RESET_CTRL); | |
33 | unreachable(); | |
34 | } | |
35 | ||
c06e836a JC |
36 | static int __init mips_reboot_setup(void) |
37 | { | |
38 | _machine_restart = ralink_restart; | |
c06e836a JC |
39 | |
40 | return 0; | |
41 | } | |
42 | ||
43 | arch_initcall(mips_reboot_setup); |