[linux-2.6-block.git] / arch / mips / ralink / irq.c

/*
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 */

#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>

#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>

#include "common.h"

/* INTC register offsets */
#define INTC_REG_STATUS0	0x00
#define INTC_REG_STATUS1	0x04
#define INTC_REG_TYPE		0x20
#define INTC_REG_RAW_STATUS	0x30
#define INTC_REG_ENABLE		0x34
#define INTC_REG_DISABLE	0x38

#define INTC_INT_GLOBAL		BIT(31)

#define RALINK_CPU_IRQ_INTC	(MIPS_CPU_IRQ_BASE + 2)
#define RALINK_CPU_IRQ_PCI	(MIPS_CPU_IRQ_BASE + 4)
#define RALINK_CPU_IRQ_FE	(MIPS_CPU_IRQ_BASE + 5)
#define RALINK_CPU_IRQ_WIFI	(MIPS_CPU_IRQ_BASE + 6)
#define RALINK_CPU_IRQ_COUNTER	(MIPS_CPU_IRQ_BASE + 7)

/* we have a cascade of 8 irqs */
#define RALINK_INTC_IRQ_BASE	8

/* we have 32 SoC irqs */
#define RALINK_INTC_IRQ_COUNT	32

#define RALINK_INTC_IRQ_PERFC   (RALINK_INTC_IRQ_BASE + 9)

static void __iomem *rt_intc_membase;

static inline void rt_intc_w32(u32 val, unsigned reg)
{
	__raw_writel(val, rt_intc_membase + reg);
}

static inline u32 rt_intc_r32(unsigned reg)
{
	return __raw_readl(rt_intc_membase + reg);
}

static void ralink_intc_irq_unmask(struct irq_data *d)
{
	rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
}

static void ralink_intc_irq_mask(struct irq_data *d)
{
	rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
}

static struct irq_chip ralink_intc_irq_chip = {
	.name		= "INTC",
	.irq_unmask	= ralink_intc_irq_unmask,
	.irq_mask	= ralink_intc_irq_mask,
	.irq_mask_ack	= ralink_intc_irq_mask,
};

unsigned int get_c0_compare_int(void)
{
	return CP0_LEGACY_COMPARE_IRQ;
}

static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	u32 pending = rt_intc_r32(INTC_REG_STATUS0);

	if (pending) {
		struct irq_domain *domain = irq_get_handler_data(irq);
		generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
	} else {
		spurious_interrupt();
	}
}

asmlinkage void plat_irq_dispatch(void)
{
	unsigned long pending;

	pending = read_c0_status() & read_c0_cause() & ST0_IM;

	if (pending & STATUSF_IP7)
		do_IRQ(RALINK_CPU_IRQ_COUNTER);

	else if (pending & STATUSF_IP5)
		do_IRQ(RALINK_CPU_IRQ_FE);

	else if (pending & STATUSF_IP6)
		do_IRQ(RALINK_CPU_IRQ_WIFI);

	else if (pending & STATUSF_IP4)
		do_IRQ(RALINK_CPU_IRQ_PCI);

	else if (pending & STATUSF_IP2)
		do_IRQ(RALINK_CPU_IRQ_INTC);

	else
		spurious_interrupt();
}

static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
{
	irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);

	return 0;
}

static const struct irq_domain_ops irq_domain_ops = {
	.xlate = irq_domain_xlate_onecell,
	.map = intc_map,
};

static int __init intc_of_init(struct device_node *node,
			       struct device_node *parent)
{
	struct resource res;
	struct irq_domain *domain;
	int irq;

	irq = irq_of_parse_and_map(node, 0);
	if (!irq)
		panic("Failed to get INTC IRQ");

	if (of_address_to_resource(node, 0, &res))
		panic("Failed to get intc memory range");

	if (request_mem_region(res.start, resource_size(&res),
				res.name) < 0)
		pr_err("Failed to request intc memory");

	rt_intc_membase = ioremap_nocache(res.start,
					resource_size(&res));
	if (!rt_intc_membase)
		panic("Failed to remap intc memory");

	/* disable all interrupts */
	rt_intc_w32(~0, INTC_REG_DISABLE);

	/* route all INTC interrupts to MIPS HW0 interrupt */
	rt_intc_w32(0, INTC_REG_TYPE);

	domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
			RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
	if (!domain)
		panic("Failed to add irqdomain");

	rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);

	irq_set_chained_handler(irq, ralink_intc_irq_handler);
	irq_set_handler_data(irq, domain);

	/* tell the kernel which irq is used for performance monitoring */
	cp0_perfcount_irq = irq_create_mapping(domain, 9);

	return 0;
}

static struct of_device_id __initdata of_irq_ids[] = {
	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
	{ .compatible = "ralink,rt2880-intc", .data = intc_of_init },
	{},
};

void __init arch_init_irq(void)
{
	of_irq_init(of_irq_ids);
}
Commit	Line	Data
19d3814e JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
	6	* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
	7	* Copyright (C) 2013 John Crispin <blogic@openwrt.org>
	8	*/
	9
	10	#include <linux/io.h>
	11	#include <linux/bitops.h>
	12	#include <linux/of_platform.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_irq.h>
	15	#include <linux/irqdomain.h>
	16	#include <linux/interrupt.h>
	17
	18	#include <asm/irq_cpu.h>
	19	#include <asm/mipsregs.h>
	20
	21	#include "common.h"
	22
	23	/* INTC register offsets */
	24	#define INTC_REG_STATUS0 0x00
	25	#define INTC_REG_STATUS1 0x04
	26	#define INTC_REG_TYPE 0x20
	27	#define INTC_REG_RAW_STATUS 0x30
	28	#define INTC_REG_ENABLE 0x34
	29	#define INTC_REG_DISABLE 0x38
	30
	31	#define INTC_INT_GLOBAL BIT(31)
	32
	33	#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
48b4aba7	34	#define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
19d3814e JC	35	#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
	36	#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
	37	#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
	38
	39	/* we have a cascade of 8 irqs */
	40	#define RALINK_INTC_IRQ_BASE 8
	41
	42	/* we have 32 SoC irqs */
	43	#define RALINK_INTC_IRQ_COUNT 32
	44
	45	#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
	46
	47	static void __iomem *rt_intc_membase;
	48
	49	static inline void rt_intc_w32(u32 val, unsigned reg)
	50	{
	51	__raw_writel(val, rt_intc_membase + reg);
	52	}
	53
	54	static inline u32 rt_intc_r32(unsigned reg)
	55	{
	56	return __raw_readl(rt_intc_membase + reg);
	57	}
	58
	59	static void ralink_intc_irq_unmask(struct irq_data *d)
	60	{
	61	rt_intc_w32(BIT(d->hwirq), INTC_REG_ENABLE);
	62	}
	63
	64	static void ralink_intc_irq_mask(struct irq_data *d)
	65	{
	66	rt_intc_w32(BIT(d->hwirq), INTC_REG_DISABLE);
	67	}
	68
	69	static struct irq_chip ralink_intc_irq_chip = {
	70	.name = "INTC",
	71	.irq_unmask = ralink_intc_irq_unmask,
	72	.irq_mask = ralink_intc_irq_mask,
	73	.irq_mask_ack = ralink_intc_irq_mask,
	74	};
	75
078a55fc	76	unsigned int get_c0_compare_int(void)
19d3814e JC	77	{
	78	return CP0_LEGACY_COMPARE_IRQ;
	79	}
	80
	81	static void ralink_intc_irq_handler(unsigned int irq, struct irq_desc *desc)
	82	{
	83	u32 pending = rt_intc_r32(INTC_REG_STATUS0);
	84
	85	if (pending) {
	86	struct irq_domain *domain = irq_get_handler_data(irq);
	87	generic_handle_irq(irq_find_mapping(domain, __ffs(pending)));
	88	} else {
	89	spurious_interrupt();
	90	}
	91	}
	92
	93	asmlinkage void plat_irq_dispatch(void)
	94	{
	95	unsigned long pending;
	96
	97	pending = read_c0_status() & read_c0_cause() & ST0_IM;
	98
	99	if (pending & STATUSF_IP7)
	100	do_IRQ(RALINK_CPU_IRQ_COUNTER);
	101
	102	else if (pending & STATUSF_IP5)
	103	do_IRQ(RALINK_CPU_IRQ_FE);
	104
	105	else if (pending & STATUSF_IP6)
	106	do_IRQ(RALINK_CPU_IRQ_WIFI);
	107
48b4aba7 GJ	108	else if (pending & STATUSF_IP4)
	109	do_IRQ(RALINK_CPU_IRQ_PCI);
	110
19d3814e JC	111	else if (pending & STATUSF_IP2)
	112	do_IRQ(RALINK_CPU_IRQ_INTC);
	113
	114	else
	115	spurious_interrupt();
	116	}
	117
	118	static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
	119	{
	120	irq_set_chip_and_handler(irq, &ralink_intc_irq_chip, handle_level_irq);
	121
	122	return 0;
	123	}
	124
	125	static const struct irq_domain_ops irq_domain_ops = {
	126	.xlate = irq_domain_xlate_onecell,
	127	.map = intc_map,
	128	};
	129
	130	static int __init intc_of_init(struct device_node *node,
	131	struct device_node *parent)
	132	{
	133	struct resource res;
	134	struct irq_domain *domain;
d3d2b420	135	int irq;
19d3814e	136
d3d2b420 GJ	137	irq = irq_of_parse_and_map(node, 0);
	138	if (!irq)
	139	panic("Failed to get INTC IRQ");
19d3814e JC	140
	141	if (of_address_to_resource(node, 0, &res))
	142	panic("Failed to get intc memory range");
	143
	144	if (request_mem_region(res.start, resource_size(&res),
	145	res.name) < 0)
	146	pr_err("Failed to request intc memory");
	147
	148	rt_intc_membase = ioremap_nocache(res.start,
	149	resource_size(&res));
	150	if (!rt_intc_membase)
	151	panic("Failed to remap intc memory");
	152
	153	/* disable all interrupts */
	154	rt_intc_w32(~0, INTC_REG_DISABLE);
	155
	156	/* route all INTC interrupts to MIPS HW0 interrupt */
	157	rt_intc_w32(0, INTC_REG_TYPE);
	158
	159	domain = irq_domain_add_legacy(node, RALINK_INTC_IRQ_COUNT,
	160	RALINK_INTC_IRQ_BASE, 0, &irq_domain_ops, NULL);
	161	if (!domain)
	162	panic("Failed to add irqdomain");
	163
	164	rt_intc_w32(INTC_INT_GLOBAL, INTC_REG_ENABLE);
	165
d3d2b420 GJ	166	irq_set_chained_handler(irq, ralink_intc_irq_handler);
d3d2b420 GJ	167	irq_set_handler_data(irq, domain);
19d3814e	168
29473822	169	/* tell the kernel which irq is used for performance monitoring */
19d3814e JC	170	cp0_perfcount_irq = irq_create_mapping(domain, 9);
	171
	172	return 0;
	173	}
	174
	175	static struct of_device_id __initdata of_irq_ids[] = {
d3d2b420	176	{ .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_intc_init },
19d3814e JC	177	{ .compatible = "ralink,rt2880-intc", .data = intc_of_init },
	178	{},
	179	};
	180
	181	void __init arch_init_irq(void)
	182	{
	183	of_irq_init(of_irq_ids);
	184	}
	185