Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5fff610b | 2 | /* |
5fff610b JC |
3 | * |
4 | * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> | |
5 | */ | |
6 | ||
7 | #include <linux/io.h> | |
8 | #include <linux/serial_reg.h> | |
9 | ||
10 | #include <asm/addrspace.h> | |
5c93316c | 11 | #include <asm/setup.h> |
5fff610b | 12 | |
5b4500d1 | 13 | #ifdef CONFIG_SOC_RT288X |
a097b13c JC |
14 | #define EARLY_UART_BASE 0x300c00 |
15 | #define CHIPID_BASE 0x300004 | |
16 | #elif defined(CONFIG_SOC_MT7621) | |
17 | #define EARLY_UART_BASE 0x1E000c00 | |
18 | #define CHIPID_BASE 0x1E000004 | |
5b4500d1 | 19 | #else |
a097b13c JC |
20 | #define EARLY_UART_BASE 0x10000c00 |
21 | #define CHIPID_BASE 0x10000004 | |
5b4500d1 | 22 | #endif |
5fff610b | 23 | |
a097b13c JC |
24 | #define MT7628_CHIP_NAME1 0x20203832 |
25 | ||
26 | #define UART_REG_TX 0x04 | |
73afa6c4 | 27 | #define UART_REG_LCR 0x0c |
a097b13c JC |
28 | #define UART_REG_LSR 0x14 |
29 | #define UART_REG_LSR_RT2880 0x1c | |
5fff610b JC |
30 | |
31 | static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE); | |
a097b13c | 32 | static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE); |
73afa6c4 | 33 | static int init_complete; |
5fff610b JC |
34 | |
35 | static inline void uart_w32(u32 val, unsigned reg) | |
36 | { | |
37 | __raw_writel(val, uart_membase + reg); | |
38 | } | |
39 | ||
40 | static inline u32 uart_r32(unsigned reg) | |
41 | { | |
42 | return __raw_readl(uart_membase + reg); | |
43 | } | |
44 | ||
a097b13c JC |
45 | static inline int soc_is_mt7628(void) |
46 | { | |
47 | return IS_ENABLED(CONFIG_SOC_MT7620) && | |
48 | (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1); | |
49 | } | |
50 | ||
73afa6c4 JC |
51 | static void find_uart_base(void) |
52 | { | |
53 | int i; | |
54 | ||
55 | if (!soc_is_mt7628()) | |
56 | return; | |
57 | ||
58 | for (i = 0; i < 3; i++) { | |
59 | u32 reg = uart_r32(UART_REG_LCR + (0x100 * i)); | |
60 | ||
61 | if (!reg) | |
62 | continue; | |
63 | ||
64 | uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + | |
65 | (0x100 * i)); | |
66 | break; | |
67 | } | |
68 | } | |
69 | ||
5c93316c | 70 | void prom_putchar(char ch) |
5fff610b | 71 | { |
73afa6c4 JC |
72 | if (!init_complete) { |
73 | find_uart_base(); | |
74 | init_complete = 1; | |
75 | } | |
76 | ||
a097b13c | 77 | if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) { |
5c93316c | 78 | uart_w32((unsigned char)ch, UART_TX); |
a097b13c JC |
79 | while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0) |
80 | ; | |
81 | } else { | |
82 | while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0) | |
83 | ; | |
5c93316c | 84 | uart_w32((unsigned char)ch, UART_REG_TX); |
a097b13c JC |
85 | while ((uart_r32(UART_REG_LSR_RT2880) & UART_LSR_THRE) == 0) |
86 | ; | |
87 | } | |
5fff610b | 88 | } |