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a3a0f8c8 DV |
1 | /* |
2 | * Locations of devices in the Zeus ASIC | |
3 | * | |
4 | * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | * | |
20 | * Author: Ken Eppinett | |
21 | * David Schleef <ds@schleef.org> | |
22 | * | |
23 | * Description: Defines the platform resources for the SA settop. | |
24 | */ | |
25 | ||
26 | #include <asm/mach-powertv/asic.h> | |
27 | ||
28 | const struct register_map zeus_register_map = { | |
29 | .eic_slow0_strt_add = 0x000000, | |
30 | .eic_cfg_bits = 0x000038, | |
31 | .eic_ready_status = 0x00004c, | |
32 | ||
33 | .chipver3 = 0x280800, | |
34 | .chipver2 = 0x280804, | |
35 | .chipver1 = 0x280808, | |
36 | .chipver0 = 0x28080c, | |
37 | ||
38 | /* The registers of IRBlaster */ | |
39 | .uart1_intstat = 0x281800, | |
40 | .uart1_inten = 0x281804, | |
41 | .uart1_config1 = 0x281808, | |
42 | .uart1_config2 = 0x28180C, | |
43 | .uart1_divisorhi = 0x281810, | |
44 | .uart1_divisorlo = 0x281814, | |
45 | .uart1_data = 0x281818, | |
46 | .uart1_status = 0x28181C, | |
47 | ||
48 | .int_stat_3 = 0x282800, | |
49 | .int_stat_2 = 0x282804, | |
50 | .int_stat_1 = 0x282808, | |
51 | .int_stat_0 = 0x28280c, | |
52 | .int_config = 0x282810, | |
53 | .int_int_scan = 0x282818, | |
54 | .ien_int_3 = 0x282830, | |
55 | .ien_int_2 = 0x282834, | |
56 | .ien_int_1 = 0x282838, | |
57 | .ien_int_0 = 0x28283c, | |
58 | .int_level_3_3 = 0x282880, | |
59 | .int_level_3_2 = 0x282884, | |
60 | .int_level_3_1 = 0x282888, | |
61 | .int_level_3_0 = 0x28288c, | |
62 | .int_level_2_3 = 0x282890, | |
63 | .int_level_2_2 = 0x282894, | |
64 | .int_level_2_1 = 0x282898, | |
65 | .int_level_2_0 = 0x28289c, | |
66 | .int_level_1_3 = 0x2828a0, | |
67 | .int_level_1_2 = 0x2828a4, | |
68 | .int_level_1_1 = 0x2828a8, | |
69 | .int_level_1_0 = 0x2828ac, | |
70 | .int_level_0_3 = 0x2828b0, | |
71 | .int_level_0_2 = 0x2828b4, | |
72 | .int_level_0_1 = 0x2828b8, | |
73 | .int_level_0_0 = 0x2828bc, | |
74 | .int_docsis_en = 0x2828F4, | |
75 | ||
76 | .mips_pll_setup = 0x1a0000, | |
77 | .usb_fs = 0x1a0018, | |
78 | .test_bus = 0x1a0238, | |
79 | .crt_spare = 0x1a0090, | |
80 | .usb2_ohci_int_mask = 0x1e000c, | |
81 | .usb2_strap = 0x1e0014, | |
82 | .ehci_hcapbase = 0x1FFE00, | |
83 | .ohci_hc_revision = 0x1FFC00, | |
84 | .bcm1_bs_lmi_steer = 0x2C0008, | |
85 | .usb2_control = 0x2c01a0, | |
86 | .usb2_stbus_obc = 0x1FFF00, | |
87 | .usb2_stbus_mess_size = 0x1FFF04, | |
88 | .usb2_stbus_chunk_size = 0x1FFF08, | |
89 | ||
90 | .pcie_regs = 0x200000, | |
91 | .tim_ch = 0x282C10, | |
92 | .tim_cl = 0x282C14, | |
93 | .gpio_dout = 0x282c20, | |
94 | .gpio_din = 0x282c24, | |
95 | .gpio_dir = 0x282c2C, | |
96 | .watchdog = 0x282c30, | |
97 | .front_panel = 0x283800, | |
98 | }; |