[linux-2.6-block.git] / arch / mips / pistachio / init.c

/*
 * Pistachio platform setup
 *
 * Copyright (C) 2014 Google, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
#include <linux/of_fdt.h>
#include <linux/of_platform.h>

#include <asm/cacheflush.h>
#include <asm/dma-coherence.h>
#include <asm/fw/fw.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-cm.h>
#include <asm/mips-cpc.h>
#include <asm/prom.h>
#include <asm/smp-ops.h>
#include <asm/traps.h>

const char *get_system_type(void)
{
	return "IMG Pistachio SoC";
}

static void __init plat_setup_iocoherency(void)
{
	/*
	 * Kernel has been configured with software coherency
	 * but we might choose to turn it off and use hardware
	 * coherency instead.
	 */
	if (mips_cm_numiocu() != 0) {
		/* Nothing special needs to be done to enable coherency */
		pr_info("CMP IOCU detected\n");
		hw_coherentio = 1;
		if (coherentio == 0)
			pr_info("Hardware DMA cache coherency disabled\n");
		else
			pr_info("Hardware DMA cache coherency enabled\n");
	} else {
		if (coherentio == 1)
			pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
		else
			pr_info("Software DMA cache coherency enabled\n");
	}
}

void __init plat_mem_setup(void)
{
	if (fw_arg0 != -2)
		panic("Device-tree not present");

	__dt_setup_arch((void *)fw_arg1);
	strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);

	plat_setup_iocoherency();
}

#define DEFAULT_CPC_BASE_ADDR	0x1bde0000
#define DEFAULT_CDMM_BASE_ADDR	0x1bdd0000

phys_addr_t mips_cpc_default_phys_base(void)
{
	return DEFAULT_CPC_BASE_ADDR;
}

phys_addr_t mips_cdmm_phys_base(void)
{
	return DEFAULT_CDMM_BASE_ADDR;
}

static void __init mips_nmi_setup(void)
{
	void *base;
	extern char except_vec_nmi;

	base = cpu_has_veic ?
		(void *)(CAC_BASE + 0xa80) :
		(void *)(CAC_BASE + 0x380);
	memcpy(base, &except_vec_nmi, 0x80);
	flush_icache_range((unsigned long)base,
			   (unsigned long)base + 0x80);
}

static void __init mips_ejtag_setup(void)
{
	void *base;
	extern char except_vec_ejtag_debug;

	base = cpu_has_veic ?
		(void *)(CAC_BASE + 0xa00) :
		(void *)(CAC_BASE + 0x300);
	memcpy(base, &except_vec_ejtag_debug, 0x80);
	flush_icache_range((unsigned long)base,
			   (unsigned long)base + 0x80);
}

void __init prom_init(void)
{
	board_nmi_handler_setup = mips_nmi_setup;
	board_ejtag_handler_setup = mips_ejtag_setup;

	mips_cm_probe();
	mips_cpc_probe();
	register_cps_smp_ops();
}

void __init prom_free_prom_memory(void)
{
}

void __init device_tree_init(void)
{
	if (!initial_boot_params)
		return;

	unflatten_and_copy_device_tree();
}

static int __init plat_of_setup(void)
{
	if (!of_have_populated_dt())
		panic("Device tree not present");

	if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
		panic("Failed to populate DT");

	return 0;
}
arch_initcall(plat_of_setup);
Commit	Line	Data
6a438309 AB	1	/*
	2	* Pistachio platform setup
	3	*
	4	* Copyright (C) 2014 Google, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/init.h>
	12	#include <linux/kernel.h>
	13	#include <linux/of_address.h>
	14	#include <linux/of_fdt.h>
	15	#include <linux/of_platform.h>
	16
	17	#include <asm/cacheflush.h>
	18	#include <asm/dma-coherence.h>
	19	#include <asm/fw/fw.h>
	20	#include <asm/mips-boards/generic.h>
	21	#include <asm/mips-cm.h>
	22	#include <asm/mips-cpc.h>
	23	#include <asm/prom.h>
	24	#include <asm/smp-ops.h>
	25	#include <asm/traps.h>
	26
	27	const char *get_system_type(void)
	28	{
	29	return "IMG Pistachio SoC";
	30	}
	31
	32	static void __init plat_setup_iocoherency(void)
	33	{
	34	/*
	35	* Kernel has been configured with software coherency
	36	* but we might choose to turn it off and use hardware
	37	* coherency instead.
	38	*/
	39	if (mips_cm_numiocu() != 0) {
	40	/* Nothing special needs to be done to enable coherency */
	41	pr_info("CMP IOCU detected\n");
	42	hw_coherentio = 1;
	43	if (coherentio == 0)
	44	pr_info("Hardware DMA cache coherency disabled\n");
	45	else
	46	pr_info("Hardware DMA cache coherency enabled\n");
	47	} else {
	48	if (coherentio == 1)
	49	pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
	50	else
	51	pr_info("Software DMA cache coherency enabled\n");
	52	}
	53	}
	54
	55	void __init plat_mem_setup(void)
	56	{
	57	if (fw_arg0 != -2)
	58	panic("Device-tree not present");
	59
	60	__dt_setup_arch((void *)fw_arg1);
	61	strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
	62
	63	plat_setup_iocoherency();
	64	}
65
6b5e741e JH	66	#define DEFAULT_CPC_BASE_ADDR 0x1bde0000
6b5e741e JH	67	#define DEFAULT_CDMM_BASE_ADDR 0x1bdd0000
6a438309 AB	68
	69	phys_addr_t mips_cpc_default_phys_base(void)
	70	{
	71	return DEFAULT_CPC_BASE_ADDR;
	72	}
	73
6b5e741e JH	74	phys_addr_t mips_cdmm_phys_base(void)
	75	{
	76	return DEFAULT_CDMM_BASE_ADDR;
	77	}
	78
6a438309 AB	79	static void __init mips_nmi_setup(void)
	80	{
	81	void *base;
	82	extern char except_vec_nmi;
	83
	84	base = cpu_has_veic ?
	85	(void *)(CAC_BASE + 0xa80) :
	86	(void *)(CAC_BASE + 0x380);
	87	memcpy(base, &except_vec_nmi, 0x80);
	88	flush_icache_range((unsigned long)base,
	89	(unsigned long)base + 0x80);
	90	}
	91
	92	static void __init mips_ejtag_setup(void)
	93	{
	94	void *base;
	95	extern char except_vec_ejtag_debug;
	96
	97	base = cpu_has_veic ?
	98	(void *)(CAC_BASE + 0xa00) :
	99	(void *)(CAC_BASE + 0x300);
	100	memcpy(base, &except_vec_ejtag_debug, 0x80);
	101	flush_icache_range((unsigned long)base,
	102	(unsigned long)base + 0x80);
	103	}
	104
	105	void __init prom_init(void)
	106	{
	107	board_nmi_handler_setup = mips_nmi_setup;
	108	board_ejtag_handler_setup = mips_ejtag_setup;
	109
	110	mips_cm_probe();
	111	mips_cpc_probe();
	112	register_cps_smp_ops();
	113	}
	114
	115	void __init prom_free_prom_memory(void)
	116	{
	117	}
	118
	119	void __init device_tree_init(void)
	120	{
	121	if (!initial_boot_params)
	122	return;
	123
	124	unflatten_and_copy_device_tree();
	125	}
	126
	127	static int __init plat_of_setup(void)
	128	{
	129	if (!of_have_populated_dt())
	130	panic("Device tree not present");
	131
	132	if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
	133	panic("Failed to populate DT");
	134
	135	return 0;
	136	}
	137	arch_initcall(plat_of_setup);