[linux-block.git] / arch / mips / pci / pci.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *
 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
 * Copyright (C) 2011 Wind River Systems,
 *   written by Ralf Baechle (ralf@linux-mips.org)
 */
#include <linux/bug.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/memblock.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/of_address.h>

#include <asm/cpu-info.h>

unsigned long PCIBIOS_MIN_IO;
EXPORT_SYMBOL(PCIBIOS_MIN_IO);

unsigned long PCIBIOS_MIN_MEM;
EXPORT_SYMBOL(PCIBIOS_MIN_MEM);

static int __init pcibios_set_cache_line_size(void)
{
	unsigned int lsize;

	/*
	 * Set PCI cacheline size to that of the highest level in the
	 * cache hierarchy.
	 */
	lsize = cpu_dcache_line_size();
	lsize = cpu_scache_line_size() ? : lsize;
	lsize = cpu_tcache_line_size() ? : lsize;

	BUG_ON(!lsize);

	pci_dfl_cache_line_size = lsize >> 2;

	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
	return 0;
}
arch_initcall(pcibios_set_cache_line_size);

void pci_resource_to_user(const struct pci_dev *dev, int bar,
			  const struct resource *rsrc, resource_size_t *start,
			  resource_size_t *end)
{
	phys_addr_t size = resource_size(rsrc);

	*start = fixup_bigphys_addr(rsrc->start, size);
	*end = rsrc->start + size - 1;
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4	2	/*
1da177e4	3	*
c539ef7d RB	4	* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
	5	* Copyright (C) 2011 Wind River Systems,
	6	* written by Ralf Baechle (ralf@linux-mips.org)
1da177e4	7	*/
c539ef7d	8	#include <linux/bug.h>
1da177e4 LT	9	#include <linux/kernel.h>
1da177e4 LT	10	#include <linux/mm.h>
57c8a661	11	#include <linux/memblock.h>
cae39d13	12	#include <linux/export.h>
1da177e4 LT	13	#include <linux/init.h>
	14	#include <linux/types.h>
	15	#include <linux/pci.h>
a48cf37a	16	#include <linux/of_address.h>
1da177e4	17
c539ef7d RB	18	#include <asm/cpu-info.h>
c539ef7d RB	19
982f6ffe	20	unsigned long PCIBIOS_MIN_IO;
f8091a88	21	EXPORT_SYMBOL(PCIBIOS_MIN_IO);
639702bd	22
f8091a88 PB	23	unsigned long PCIBIOS_MIN_MEM;
f8091a88 PB	24	EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
1da177e4	25
f474ba9d	26	static int __init pcibios_set_cache_line_size(void)
c539ef7d	27	{
c539ef7d RB	28	unsigned int lsize;
	29
	30	/*
	31	* Set PCI cacheline size to that of the highest level in the
	32	* cache hierarchy.
	33	*/
73530266 MR	34	lsize = cpu_dcache_line_size();
	35	lsize = cpu_scache_line_size() ? : lsize;
	36	lsize = cpu_tcache_line_size() ? : lsize;
c539ef7d RB	37
	38	BUG_ON(!lsize);
	39
	40	pci_dfl_cache_line_size = lsize >> 2;
	41
	42	pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
f474ba9d	43	return 0;
c539ef7d	44	}
f474ba9d	45	arch_initcall(pcibios_set_cache_line_size);
c539ef7d	46
8221a013 BH	47	void pci_resource_to_user(const struct pci_dev *dev, int bar,
	48	const struct resource rsrc, resource_size_t start,
	49	resource_size_t *end)
	50	{
	51	phys_addr_t size = resource_size(rsrc);
	52
	53	*start = fixup_bigphys_addr(rsrc->start, size);
38c0a74f	54	*end = rsrc->start + size - 1;
8221a013	55	}