[linux-2.6-block.git] / arch / mips / pci / pci-rt2880.c

/*
 *  Ralink RT288x SoC PCI register definitions
 *
 *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
 *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
 *
 *  Parts of this file are based on Ralink's 2.6.21 BSP
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 */

#include <linux/delay.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>

#include <asm/mach-ralink/rt288x.h>

#define RT2880_PCI_BASE		0x00440000
#define RT288X_CPU_IRQ_PCI	4

#define RT2880_PCI_MEM_BASE	0x20000000
#define RT2880_PCI_MEM_SIZE	0x10000000
#define RT2880_PCI_IO_BASE	0x00460000
#define RT2880_PCI_IO_SIZE	0x00010000

#define RT2880_PCI_REG_PCICFG_ADDR	0x00
#define RT2880_PCI_REG_PCIMSK_ADDR	0x0c
#define RT2880_PCI_REG_BAR0SETUP_ADDR	0x10
#define RT2880_PCI_REG_IMBASEBAR0_ADDR	0x18
#define RT2880_PCI_REG_CONFIG_ADDR	0x20
#define RT2880_PCI_REG_CONFIG_DATA	0x24
#define RT2880_PCI_REG_MEMBASE		0x28
#define RT2880_PCI_REG_IOBASE		0x2c
#define RT2880_PCI_REG_ID		0x30
#define RT2880_PCI_REG_CLASS		0x34
#define RT2880_PCI_REG_SUBID		0x38
#define RT2880_PCI_REG_ARBCTL		0x80

static void __iomem *rt2880_pci_base;
static DEFINE_SPINLOCK(rt2880_pci_lock);

static u32 rt2880_pci_reg_read(u32 reg)
{
	return readl(rt2880_pci_base + reg);
}

static void rt2880_pci_reg_write(u32 val, u32 reg)
{
	writel(val, rt2880_pci_base + reg);
}

static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
					 unsigned int func, unsigned int where)
{
	return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
		0x80000000);
}

static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
				  int where, int size, u32 *val)
{
	unsigned long flags;
	u32 address;
	u32 data;

	address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
					 PCI_FUNC(devfn), where);

	spin_lock_irqsave(&rt2880_pci_lock, flags);
	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
	data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
	spin_unlock_irqrestore(&rt2880_pci_lock, flags);

	switch (size) {
	case 1:
		*val = (data >> ((where & 3) << 3)) & 0xff;
		break;
	case 2:
		*val = (data >> ((where & 3) << 3)) & 0xffff;
		break;
	case 4:
		*val = data;
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
				   int where, int size, u32 val)
{
	unsigned long flags;
	u32 address;
	u32 data;

	address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
					 PCI_FUNC(devfn), where);

	spin_lock_irqsave(&rt2880_pci_lock, flags);
	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
	data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);

	switch (size) {
	case 1:
		data = (data & ~(0xff << ((where & 3) << 3))) |
		       (val << ((where & 3) << 3));
		break;
	case 2:
		data = (data & ~(0xffff << ((where & 3) << 3))) |
		       (val << ((where & 3) << 3));
		break;
	case 4:
		data = val;
		break;
	}

	rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
	spin_unlock_irqrestore(&rt2880_pci_lock, flags);

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops rt2880_pci_ops = {
	.read	= rt2880_pci_config_read,
	.write	= rt2880_pci_config_write,
};

static struct resource rt2880_pci_mem_resource = {
	.name	= "PCI MEM space",
	.start	= RT2880_PCI_MEM_BASE,
	.end	= RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
	.flags	= IORESOURCE_MEM,
};

static struct resource rt2880_pci_io_resource = {
	.name	= "PCI IO space",
	.start	= RT2880_PCI_IO_BASE,
	.end	= RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
	.flags	= IORESOURCE_IO,
};

static struct pci_controller rt2880_pci_controller = {
	.pci_ops	= &rt2880_pci_ops,
	.mem_resource	= &rt2880_pci_mem_resource,
	.io_resource	= &rt2880_pci_io_resource,
};

static inline u32 rt2880_pci_read_u32(unsigned long reg)
{
	unsigned long flags;
	u32 address;
	u32 ret;

	address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);

	spin_lock_irqsave(&rt2880_pci_lock, flags);
	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
	ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
	spin_unlock_irqrestore(&rt2880_pci_lock, flags);

	return ret;
}

static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
{
	unsigned long flags;
	u32 address;

	address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);

	spin_lock_irqsave(&rt2880_pci_lock, flags);
	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
	rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
}

int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	u16 cmd;
	int irq = -1;

	if (dev->bus->number != 0)
		return irq;

	switch (PCI_SLOT(dev->devfn)) {
	case 0x00:
		rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
		(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
		break;
	case 0x11:
		irq = RT288X_CPU_IRQ_PCI;
		break;
	default:
		pr_err("%s:%s[%d] trying to alloc unknown pci irq\n",
		       __FILE__, __func__, __LINE__);
		BUG();
		break;
	}

	pci_write_config_byte((struct pci_dev *) dev,
		PCI_CACHE_LINE_SIZE, 0x14);
	pci_write_config_byte((struct pci_dev *) dev, PCI_LATENCY_TIMER, 0xFF);
	pci_read_config_word((struct pci_dev *) dev, PCI_COMMAND, &cmd);
	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
		PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
		PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
	pci_write_config_word((struct pci_dev *) dev, PCI_COMMAND, cmd);
	pci_write_config_byte((struct pci_dev *) dev, PCI_INTERRUPT_LINE,
			      dev->irq);
	return irq;
}

static int rt288x_pci_probe(struct platform_device *pdev)
{
	void __iomem *io_map_base;
	int i;

	rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);

	io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
	rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
	set_io_port_base((unsigned long) io_map_base);

	ioport_resource.start = RT2880_PCI_IO_BASE;
	ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;

	rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
	udelay(1);

	rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
	rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
	rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
	rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
	rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
	rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
	rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
	rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
	rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);

	rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
	(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);

	register_pci_controller(&rt2880_pci_controller);
	return 0;
}

int pcibios_plat_dev_init(struct pci_dev *dev)
{
	return 0;
}

static const struct of_device_id rt288x_pci_match[] = {
	{ .compatible = "ralink,rt288x-pci" },
	{},
};
MODULE_DEVICE_TABLE(of, rt288x_pci_match);

static struct platform_driver rt288x_pci_driver = {
	.probe = rt288x_pci_probe,
	.driver = {
		.name = "rt288x-pci",
		.of_match_table = rt288x_pci_match,
	},
};

int __init pcibios_init(void)
{
	int ret = platform_driver_register(&rt288x_pci_driver);

	if (ret)
		pr_info("rt288x-pci: Error registering platform driver!");

	return ret;
}

arch_initcall(pcibios_init);
Commit	Line	Data
187c26dd JC	1	/*
	2	* Ralink RT288x SoC PCI register definitions
	3	*
	4	* Copyright (C) 2009 John Crispin <blogic@openwrt.org>
	5	* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
	6	*
	7	* Parts of this file are based on Ralink's 2.6.21 BSP
	8	*
	9	* This program is free software; you can redistribute it and/or modify it
	10	* under the terms of the GNU General Public License version 2 as published
	11	* by the Free Software Foundation.
	12	*/
	13
c861519f	14	#include <linux/delay.h>
187c26dd JC	15	#include <linux/types.h>
	16	#include <linux/pci.h>
	17	#include <linux/io.h>
	18	#include <linux/init.h>
	19	#include <linux/module.h>
	20	#include <linux/of_platform.h>
	21	#include <linux/of_irq.h>
	22	#include <linux/of_pci.h>
	23
	24	#include <asm/mach-ralink/rt288x.h>
	25
	26	#define RT2880_PCI_BASE 0x00440000
	27	#define RT288X_CPU_IRQ_PCI 4
	28
	29	#define RT2880_PCI_MEM_BASE 0x20000000
	30	#define RT2880_PCI_MEM_SIZE 0x10000000
	31	#define RT2880_PCI_IO_BASE 0x00460000
	32	#define RT2880_PCI_IO_SIZE 0x00010000
	33
	34	#define RT2880_PCI_REG_PCICFG_ADDR 0x00
	35	#define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
	36	#define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
	37	#define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
	38	#define RT2880_PCI_REG_CONFIG_ADDR 0x20
	39	#define RT2880_PCI_REG_CONFIG_DATA 0x24
	40	#define RT2880_PCI_REG_MEMBASE 0x28
	41	#define RT2880_PCI_REG_IOBASE 0x2c
	42	#define RT2880_PCI_REG_ID 0x30
	43	#define RT2880_PCI_REG_CLASS 0x34
	44	#define RT2880_PCI_REG_SUBID 0x38
	45	#define RT2880_PCI_REG_ARBCTL 0x80
	46
	47	static void __iomem *rt2880_pci_base;
	48	static DEFINE_SPINLOCK(rt2880_pci_lock);
	49
	50	static u32 rt2880_pci_reg_read(u32 reg)
	51	{
	52	return readl(rt2880_pci_base + reg);
	53	}
	54
	55	static void rt2880_pci_reg_write(u32 val, u32 reg)
	56	{
	57	writel(val, rt2880_pci_base + reg);
	58	}
	59
	60	static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
	61	unsigned int func, unsigned int where)
	62	{
	63	return ((bus << 16) \| (slot << 11) \| (func << 8) \| (where & 0xfc) \|
	64	0x80000000);
	65	}
	66
	67	static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
	68	int where, int size, u32 *val)
	69	{
	70	unsigned long flags;
	71	u32 address;
	72	u32 data;
	73
	74	address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
	75	PCI_FUNC(devfn), where);
	76
	77	spin_lock_irqsave(&rt2880_pci_lock, flags);
	78	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
79	data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
80	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
81
82	switch (size) {
83	case 1:
84	*val = (data >> ((where & 3) << 3)) & 0xff;
85	break;
86	case 2:
87	*val = (data >> ((where & 3) << 3)) & 0xffff;
88	break;
89	case 4:
90	*val = data;
91	break;
92	}
93
94	return PCIBIOS_SUCCESSFUL;
95	}
96
97	static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
98	int where, int size, u32 val)
99	{
100	unsigned long flags;
101	u32 address;
102	u32 data;
103
104	address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
105	PCI_FUNC(devfn), where);
106
107	spin_lock_irqsave(&rt2880_pci_lock, flags);
108	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
109	data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
110
111	switch (size) {
112	case 1:
113	data = (data & ~(0xff << ((where & 3) << 3))) \|
114	(val << ((where & 3) << 3));
115	break;
116	case 2:
117	data = (data & ~(0xffff << ((where & 3) << 3))) \|
118	(val << ((where & 3) << 3));
119	break;
120	case 4:
121	data = val;
122	break;
123	}
124
125	rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
126	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
127
128	return PCIBIOS_SUCCESSFUL;
129	}
130
131	static struct pci_ops rt2880_pci_ops = {
132	.read = rt2880_pci_config_read,
133	.write = rt2880_pci_config_write,
134	};
135
136	static struct resource rt2880_pci_mem_resource = {
137	.name = "PCI MEM space",
138	.start = RT2880_PCI_MEM_BASE,
139	.end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
140	.flags = IORESOURCE_MEM,
141	};
142
143	static struct resource rt2880_pci_io_resource = {
144	.name = "PCI IO space",
145	.start = RT2880_PCI_IO_BASE,
146	.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
147	.flags = IORESOURCE_IO,
148	};
149
150	static struct pci_controller rt2880_pci_controller = {
151	.pci_ops = &rt2880_pci_ops,
152	.mem_resource = &rt2880_pci_mem_resource,
153	.io_resource = &rt2880_pci_io_resource,
154	};
155
156	static inline u32 rt2880_pci_read_u32(unsigned long reg)
157	{
158	unsigned long flags;
159	u32 address;
160	u32 ret;
161
162	address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
163
164	spin_lock_irqsave(&rt2880_pci_lock, flags);
165	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
166	ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
167	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
168
169	return ret;
170	}
171
172	static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
173	{
174	unsigned long flags;
175	u32 address;
176
177	address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
178
179	spin_lock_irqsave(&rt2880_pci_lock, flags);
180	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
181	rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
182	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
183	}
184
185	int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
186	{
187	u16 cmd;
188	int irq = -1;
189
190	if (dev->bus->number != 0)
191	return irq;
192
193	switch (PCI_SLOT(dev->devfn)) {
194	case 0x00:
195	rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
196	(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
197	break;
198	case 0x11:
199	irq = RT288X_CPU_IRQ_PCI;
200	break;
201	default:
202	pr_err("%s:%s[%d] trying to alloc unknown pci irq\n",
203	__FILE__, __func__, __LINE__);
204	BUG();
205	break;
206	}
207
208	pci_write_config_byte((struct pci_dev *) dev,
209	PCI_CACHE_LINE_SIZE, 0x14);
210	pci_write_config_byte((struct pci_dev *) dev, PCI_LATENCY_TIMER, 0xFF);
211	pci_read_config_word((struct pci_dev *) dev, PCI_COMMAND, &cmd);
212	cmd \|= PCI_COMMAND_MASTER \| PCI_COMMAND_IO \| PCI_COMMAND_MEMORY \|
213	PCI_COMMAND_INVALIDATE \| PCI_COMMAND_FAST_BACK \|
214	PCI_COMMAND_SERR \| PCI_COMMAND_WAIT \| PCI_COMMAND_PARITY;
215	pci_write_config_word((struct pci_dev *) dev, PCI_COMMAND, cmd);
216	pci_write_config_byte((struct pci_dev *) dev, PCI_INTERRUPT_LINE,
217	dev->irq);
218	return irq;
219	}
220
221	static int rt288x_pci_probe(struct platform_device *pdev)
222	{
223	void __iomem *io_map_base;
224	int i;
225
226	rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
227
228	io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
229	rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
230	set_io_port_base((unsigned long) io_map_base);
231
232	ioport_resource.start = RT2880_PCI_IO_BASE;
233	ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
234
235	rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
c861519f	236	udelay(1);
187c26dd JC	237
	238	rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
	239	rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
	240	rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
	241	rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
	242	rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
	243	rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
	244	rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
	245	rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
	246	rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
	247
	248	rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
	249	(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
	250
	251	register_pci_controller(&rt2880_pci_controller);
	252	return 0;
	253	}
	254
	255	int pcibios_plat_dev_init(struct pci_dev *dev)
	256	{
	257	return 0;
	258	}
	259
	260	static const struct of_device_id rt288x_pci_match[] = {
	261	{ .compatible = "ralink,rt288x-pci" },
	262	{},
	263	};
	264	MODULE_DEVICE_TABLE(of, rt288x_pci_match);
	265
	266	static struct platform_driver rt288x_pci_driver = {
	267	.probe = rt288x_pci_probe,
	268	.driver = {
	269	.name = "rt288x-pci",
187c26dd JC	270	.of_match_table = rt288x_pci_match,
	271	},
	272	};
	273
	274	int __init pcibios_init(void)
	275	{
	276	int ret = platform_driver_register(&rt288x_pci_driver);
	277
	278	if (ret)
	279	pr_info("rt288x-pci: Error registering platform driver!");
	280
	281	return ret;
	282	}
	283
	284	arch_initcall(pcibios_init);