Commit | Line | Data |
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7517de34 ML |
1 | /* |
2 | * Alchemy PCI host mode support. | |
3 | * | |
4 | * Copyright 2001-2003, 2007-2008 MontaVista Software Inc. | |
5 | * Author: MontaVista Software, Inc. <source@mvista.com> | |
6 | * | |
7 | * Support for all devices (greater than 16) added by David Gathright. | |
8 | */ | |
9 | ||
71ca8693 | 10 | #include <linux/export.h> |
7517de34 ML |
11 | #include <linux/types.h> |
12 | #include <linux/pci.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
864c6c22 | 16 | #include <linux/syscore_ops.h> |
7517de34 ML |
17 | #include <linux/vmalloc.h> |
18 | ||
19 | #include <asm/mach-au1x00/au1000.h> | |
3d18c983 | 20 | #include <asm/tlbmisc.h> |
7517de34 ML |
21 | |
22 | #ifdef CONFIG_DEBUG_PCI | |
23 | #define DBG(x...) printk(KERN_DEBUG x) | |
24 | #else | |
25 | #define DBG(x...) do {} while (0) | |
26 | #endif | |
27 | ||
28 | #define PCI_ACCESS_READ 0 | |
29 | #define PCI_ACCESS_WRITE 1 | |
30 | ||
31 | struct alchemy_pci_context { | |
32 | struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ | |
33 | void __iomem *regs; /* ctrl base */ | |
34 | /* tools for wired entry for config space access */ | |
35 | unsigned long last_elo0; | |
36 | unsigned long last_elo1; | |
37 | int wired_entry; | |
38 | struct vm_struct *pci_cfg_vm; | |
39 | ||
40 | unsigned long pm[12]; | |
41 | ||
42 | int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); | |
43 | int (*board_pci_idsel)(unsigned int devsel, int assert); | |
44 | }; | |
45 | ||
864c6c22 ML |
46 | /* for syscore_ops. There's only one PCI controller on Alchemy chips, so this |
47 | * should suffice for now. | |
48 | */ | |
49 | static struct alchemy_pci_context *__alchemy_pci_ctx; | |
50 | ||
51 | ||
7517de34 ML |
52 | /* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr |
53 | * in arch/mips/alchemy/common/setup.c | |
54 | */ | |
55 | static struct resource alchemy_pci_def_memres = { | |
56 | .start = ALCHEMY_PCI_MEMWIN_START, | |
57 | .end = ALCHEMY_PCI_MEMWIN_END, | |
58 | .name = "PCI memory space", | |
59 | .flags = IORESOURCE_MEM | |
60 | }; | |
61 | ||
62 | static struct resource alchemy_pci_def_iores = { | |
63 | .start = ALCHEMY_PCI_IOWIN_START, | |
64 | .end = ALCHEMY_PCI_IOWIN_END, | |
65 | .name = "PCI IO space", | |
66 | .flags = IORESOURCE_IO | |
67 | }; | |
68 | ||
69 | static void mod_wired_entry(int entry, unsigned long entrylo0, | |
70 | unsigned long entrylo1, unsigned long entryhi, | |
71 | unsigned long pagemask) | |
72 | { | |
73 | unsigned long old_pagemask; | |
74 | unsigned long old_ctx; | |
75 | ||
76 | /* Save old context and create impossible VPN2 value */ | |
77 | old_ctx = read_c0_entryhi() & 0xff; | |
78 | old_pagemask = read_c0_pagemask(); | |
79 | write_c0_index(entry); | |
80 | write_c0_pagemask(pagemask); | |
81 | write_c0_entryhi(entryhi); | |
82 | write_c0_entrylo0(entrylo0); | |
83 | write_c0_entrylo1(entrylo1); | |
84 | tlb_write_indexed(); | |
85 | write_c0_entryhi(old_ctx); | |
86 | write_c0_pagemask(old_pagemask); | |
87 | } | |
88 | ||
89 | static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx) | |
90 | { | |
91 | ctx->wired_entry = read_c0_wired(); | |
92 | add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); | |
93 | ctx->last_elo0 = ctx->last_elo1 = ~0; | |
94 | } | |
95 | ||
96 | static int config_access(unsigned char access_type, struct pci_bus *bus, | |
97 | unsigned int dev_fn, unsigned char where, u32 *data) | |
98 | { | |
99 | struct alchemy_pci_context *ctx = bus->sysdata; | |
100 | unsigned int device = PCI_SLOT(dev_fn); | |
101 | unsigned int function = PCI_FUNC(dev_fn); | |
102 | unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r; | |
103 | int error = PCIBIOS_SUCCESSFUL; | |
104 | ||
105 | if (device > 19) { | |
106 | *data = 0xffffffff; | |
107 | return -1; | |
108 | } | |
109 | ||
7517de34 ML |
110 | local_irq_save(flags); |
111 | r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; | |
112 | r |= PCI_STATCMD_STATUS(0x2000); | |
113 | __raw_writel(r, ctx->regs + PCI_REG_STATCMD); | |
114 | wmb(); | |
115 | ||
116 | /* Allow board vendors to implement their own off-chip IDSEL. | |
117 | * If it doesn't succeed, may as well bail out at this point. | |
118 | */ | |
119 | if (ctx->board_pci_idsel(device, 1) == 0) { | |
120 | *data = 0xffffffff; | |
121 | local_irq_restore(flags); | |
122 | return -1; | |
123 | } | |
124 | ||
125 | /* Setup the config window */ | |
126 | if (bus->number == 0) | |
127 | cfg_base = (1 << device) << 11; | |
128 | else | |
129 | cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); | |
130 | ||
131 | /* Setup the lower bits of the 36-bit address */ | |
132 | offset = (function << 8) | (where & ~0x3); | |
133 | /* Pick up any address that falls below the page mask */ | |
134 | offset |= cfg_base & ~PAGE_MASK; | |
135 | ||
136 | /* Page boundary */ | |
137 | cfg_base = cfg_base & PAGE_MASK; | |
138 | ||
139 | /* To improve performance, if the current device is the same as | |
140 | * the last device accessed, we don't touch the TLB. | |
141 | */ | |
142 | entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; | |
143 | entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; | |
144 | if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) { | |
145 | mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1, | |
146 | (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); | |
147 | ctx->last_elo0 = entryLo0; | |
148 | ctx->last_elo1 = entryLo1; | |
149 | } | |
150 | ||
151 | if (access_type == PCI_ACCESS_WRITE) | |
152 | __raw_writel(*data, ctx->pci_cfg_vm->addr + offset); | |
153 | else | |
154 | *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); | |
155 | wmb(); | |
156 | ||
157 | DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n", | |
158 | access_type, bus->number, device, where, *data, offset); | |
159 | ||
160 | /* check for errors, master abort */ | |
161 | status = __raw_readl(ctx->regs + PCI_REG_STATCMD); | |
162 | if (status & (1 << 29)) { | |
163 | *data = 0xffffffff; | |
164 | error = -1; | |
165 | DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d", | |
166 | access_type, bus->number, device); | |
167 | } else if ((status >> 28) & 0xf) { | |
168 | DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", | |
169 | device, (status >> 28) & 0xf); | |
170 | ||
171 | /* clear errors */ | |
172 | __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); | |
173 | ||
174 | *data = 0xffffffff; | |
175 | error = -1; | |
176 | } | |
177 | ||
178 | /* Take away the IDSEL. */ | |
179 | (void)ctx->board_pci_idsel(device, 0); | |
180 | ||
181 | local_irq_restore(flags); | |
182 | return error; | |
183 | } | |
184 | ||
185 | static int read_config_byte(struct pci_bus *bus, unsigned int devfn, | |
186 | int where, u8 *val) | |
187 | { | |
188 | u32 data; | |
189 | int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); | |
190 | ||
191 | if (where & 1) | |
192 | data >>= 8; | |
193 | if (where & 2) | |
194 | data >>= 16; | |
195 | *val = data & 0xff; | |
196 | return ret; | |
197 | } | |
198 | ||
199 | static int read_config_word(struct pci_bus *bus, unsigned int devfn, | |
200 | int where, u16 *val) | |
201 | { | |
202 | u32 data; | |
203 | int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); | |
204 | ||
205 | if (where & 2) | |
206 | data >>= 16; | |
207 | *val = data & 0xffff; | |
208 | return ret; | |
209 | } | |
210 | ||
211 | static int read_config_dword(struct pci_bus *bus, unsigned int devfn, | |
212 | int where, u32 *val) | |
213 | { | |
214 | return config_access(PCI_ACCESS_READ, bus, devfn, where, val); | |
215 | } | |
216 | ||
217 | static int write_config_byte(struct pci_bus *bus, unsigned int devfn, | |
218 | int where, u8 val) | |
219 | { | |
220 | u32 data = 0; | |
221 | ||
222 | if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) | |
223 | return -1; | |
224 | ||
225 | data = (data & ~(0xff << ((where & 3) << 3))) | | |
226 | (val << ((where & 3) << 3)); | |
227 | ||
228 | if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) | |
229 | return -1; | |
230 | ||
231 | return PCIBIOS_SUCCESSFUL; | |
232 | } | |
233 | ||
234 | static int write_config_word(struct pci_bus *bus, unsigned int devfn, | |
235 | int where, u16 val) | |
236 | { | |
237 | u32 data = 0; | |
238 | ||
239 | if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) | |
240 | return -1; | |
241 | ||
242 | data = (data & ~(0xffff << ((where & 3) << 3))) | | |
243 | (val << ((where & 3) << 3)); | |
244 | ||
245 | if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) | |
246 | return -1; | |
247 | ||
248 | return PCIBIOS_SUCCESSFUL; | |
249 | } | |
250 | ||
251 | static int write_config_dword(struct pci_bus *bus, unsigned int devfn, | |
252 | int where, u32 val) | |
253 | { | |
254 | return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val); | |
255 | } | |
256 | ||
257 | static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn, | |
258 | int where, int size, u32 *val) | |
259 | { | |
260 | switch (size) { | |
261 | case 1: { | |
262 | u8 _val; | |
263 | int rc = read_config_byte(bus, devfn, where, &_val); | |
264 | ||
265 | *val = _val; | |
266 | return rc; | |
267 | } | |
268 | case 2: { | |
269 | u16 _val; | |
270 | int rc = read_config_word(bus, devfn, where, &_val); | |
271 | ||
272 | *val = _val; | |
273 | return rc; | |
274 | } | |
275 | default: | |
276 | return read_config_dword(bus, devfn, where, val); | |
277 | } | |
278 | } | |
279 | ||
280 | static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn, | |
281 | int where, int size, u32 val) | |
282 | { | |
283 | switch (size) { | |
284 | case 1: | |
285 | return write_config_byte(bus, devfn, where, (u8) val); | |
286 | case 2: | |
287 | return write_config_word(bus, devfn, where, (u16) val); | |
288 | default: | |
289 | return write_config_dword(bus, devfn, where, val); | |
290 | } | |
291 | } | |
292 | ||
293 | static struct pci_ops alchemy_pci_ops = { | |
294 | .read = alchemy_pci_read, | |
295 | .write = alchemy_pci_write, | |
296 | }; | |
297 | ||
298 | static int alchemy_pci_def_idsel(unsigned int devsel, int assert) | |
299 | { | |
300 | return 1; /* success */ | |
301 | } | |
302 | ||
864c6c22 ML |
303 | /* save PCI controller register contents. */ |
304 | static int alchemy_pci_suspend(void) | |
305 | { | |
306 | struct alchemy_pci_context *ctx = __alchemy_pci_ctx; | |
307 | if (!ctx) | |
308 | return 0; | |
309 | ||
310 | ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); | |
311 | ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; | |
312 | ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); | |
313 | ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); | |
314 | ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); | |
315 | ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); | |
316 | ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); | |
317 | ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); | |
318 | ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); | |
319 | ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); | |
320 | ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); | |
321 | ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
326 | static void alchemy_pci_resume(void) | |
327 | { | |
328 | struct alchemy_pci_context *ctx = __alchemy_pci_ctx; | |
329 | if (!ctx) | |
330 | return; | |
331 | ||
332 | __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); | |
333 | __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); | |
334 | __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); | |
335 | __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); | |
336 | __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); | |
337 | __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); | |
338 | __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); | |
339 | __raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); | |
340 | __raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); | |
341 | __raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); | |
342 | __raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); | |
343 | wmb(); | |
344 | __raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); | |
345 | wmb(); | |
346 | ||
347 | /* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired | |
348 | * on resume, making it necessary to recreate it as soon as possible. | |
349 | */ | |
350 | ctx->wired_entry = 8191; /* impossibly high value */ | |
351 | alchemy_pci_wired_entry(ctx); /* install it */ | |
352 | } | |
353 | ||
354 | static struct syscore_ops alchemy_pci_pmops = { | |
355 | .suspend = alchemy_pci_suspend, | |
356 | .resume = alchemy_pci_resume, | |
357 | }; | |
358 | ||
28eb0e46 | 359 | static int alchemy_pci_probe(struct platform_device *pdev) |
7517de34 ML |
360 | { |
361 | struct alchemy_pci_platdata *pd = pdev->dev.platform_data; | |
362 | struct alchemy_pci_context *ctx; | |
363 | void __iomem *virt_io; | |
364 | unsigned long val; | |
365 | struct resource *r; | |
366 | int ret; | |
367 | ||
368 | /* need at least PCI IRQ mapping table */ | |
369 | if (!pd) { | |
370 | dev_err(&pdev->dev, "need platform data for PCI setup\n"); | |
371 | ret = -ENODEV; | |
372 | goto out; | |
373 | } | |
374 | ||
375 | ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); | |
376 | if (!ctx) { | |
377 | dev_err(&pdev->dev, "no memory for pcictl context\n"); | |
378 | ret = -ENOMEM; | |
379 | goto out; | |
380 | } | |
381 | ||
382 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
383 | if (!r) { | |
384 | dev_err(&pdev->dev, "no pcictl ctrl regs resource\n"); | |
385 | ret = -ENODEV; | |
386 | goto out1; | |
387 | } | |
388 | ||
389 | if (!request_mem_region(r->start, resource_size(r), pdev->name)) { | |
390 | dev_err(&pdev->dev, "cannot claim pci regs\n"); | |
391 | ret = -ENODEV; | |
392 | goto out1; | |
393 | } | |
394 | ||
395 | ctx->regs = ioremap_nocache(r->start, resource_size(r)); | |
396 | if (!ctx->regs) { | |
397 | dev_err(&pdev->dev, "cannot map pci regs\n"); | |
398 | ret = -ENODEV; | |
399 | goto out2; | |
400 | } | |
401 | ||
402 | /* map parts of the PCI IO area */ | |
403 | /* REVISIT: if this changes with a newer variant (doubt it) make this | |
404 | * a platform resource. | |
405 | */ | |
406 | virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000); | |
407 | if (!virt_io) { | |
408 | dev_err(&pdev->dev, "cannot remap pci io space\n"); | |
409 | ret = -ENODEV; | |
410 | goto out3; | |
411 | } | |
412 | ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; | |
413 | ||
414 | #ifdef CONFIG_DMA_NONCOHERENT | |
415 | /* Au1500 revisions older than AD have borked coherent PCI */ | |
416 | if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && | |
417 | (read_c0_prid() < 0x01030202)) { | |
418 | val = __raw_readl(ctx->regs + PCI_REG_CONFIG); | |
419 | val |= PCI_CONFIG_NC; | |
420 | __raw_writel(val, ctx->regs + PCI_REG_CONFIG); | |
421 | wmb(); | |
422 | dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n"); | |
423 | } | |
424 | #endif | |
425 | ||
426 | if (pd->board_map_irq) | |
427 | ctx->board_map_irq = pd->board_map_irq; | |
428 | ||
429 | if (pd->board_pci_idsel) | |
430 | ctx->board_pci_idsel = pd->board_pci_idsel; | |
431 | else | |
432 | ctx->board_pci_idsel = alchemy_pci_def_idsel; | |
433 | ||
434 | /* fill in relevant pci_controller members */ | |
435 | ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops; | |
436 | ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres; | |
437 | ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores; | |
438 | ||
439 | /* we can't ioremap the entire pci config space because it's too large, | |
440 | * nor can we dynamically ioremap it because some drivers use the | |
441 | * PCI config routines from within atomic contex and that becomes a | |
442 | * problem in get_vm_area(). Instead we use one wired TLB entry to | |
443 | * handle all config accesses for all busses. | |
444 | */ | |
445 | ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); | |
446 | if (!ctx->pci_cfg_vm) { | |
447 | dev_err(&pdev->dev, "unable to get vm area\n"); | |
448 | ret = -ENOMEM; | |
449 | goto out4; | |
450 | } | |
864c6c22 ML |
451 | ctx->wired_entry = 8191; /* impossibly high value */ |
452 | alchemy_pci_wired_entry(ctx); /* install it */ | |
7517de34 ML |
453 | |
454 | set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); | |
455 | ||
456 | /* board may want to modify bits in the config register, do it now */ | |
457 | val = __raw_readl(ctx->regs + PCI_REG_CONFIG); | |
458 | val &= ~pd->pci_cfg_clr; | |
459 | val |= pd->pci_cfg_set; | |
460 | val &= ~PCI_CONFIG_PD; /* clear disable bit */ | |
461 | __raw_writel(val, ctx->regs + PCI_REG_CONFIG); | |
462 | wmb(); | |
463 | ||
864c6c22 | 464 | __alchemy_pci_ctx = ctx; |
7517de34 | 465 | platform_set_drvdata(pdev, ctx); |
864c6c22 | 466 | register_syscore_ops(&alchemy_pci_pmops); |
7517de34 ML |
467 | register_pci_controller(&ctx->alchemy_pci_ctrl); |
468 | ||
469 | return 0; | |
470 | ||
471 | out4: | |
472 | iounmap(virt_io); | |
473 | out3: | |
474 | iounmap(ctx->regs); | |
475 | out2: | |
476 | release_mem_region(r->start, resource_size(r)); | |
477 | out1: | |
478 | kfree(ctx); | |
479 | out: | |
480 | return ret; | |
481 | } | |
482 | ||
7517de34 ML |
483 | static struct platform_driver alchemy_pcictl_driver = { |
484 | .probe = alchemy_pci_probe, | |
485 | .driver = { | |
486 | .name = "alchemy-pci", | |
487 | .owner = THIS_MODULE, | |
7517de34 ML |
488 | }, |
489 | }; | |
490 | ||
491 | static int __init alchemy_pci_init(void) | |
492 | { | |
493 | /* Au1500/Au1550 have PCI */ | |
494 | switch (alchemy_get_cputype()) { | |
495 | case ALCHEMY_CPU_AU1500: | |
496 | case ALCHEMY_CPU_AU1550: | |
497 | return platform_driver_register(&alchemy_pcictl_driver); | |
498 | } | |
499 | return 0; | |
500 | } | |
501 | arch_initcall(alchemy_pci_init); | |
502 | ||
503 | ||
504 | int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | |
505 | { | |
506 | struct alchemy_pci_context *ctx = dev->sysdata; | |
507 | if (ctx && ctx->board_map_irq) | |
508 | return ctx->board_map_irq(dev, slot, pin); | |
509 | return -1; | |
510 | } | |
511 | ||
512 | int pcibios_plat_dev_init(struct pci_dev *dev) | |
513 | { | |
514 | return 0; | |
515 | } |