[linux-2.6-block.git] / arch / mips / oprofile / op_model_mipsxx.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004, 05, 06 by Ralf Baechle
 * Copyright (C) 2005 by MIPS Technologies, Inc.
 */
#include <linux/cpumask.h>
#include <linux/oprofile.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <asm/irq_regs.h>
#include <asm/time.h>

#include "op_impl.h"

#define M_PERFCTL_EVENT(event)		(((event) << MIPS_PERFCTRL_EVENT_S) & \
					 MIPS_PERFCTRL_EVENT)
#define M_PERFCTL_VPEID(vpe)		((vpe)	  << MIPS_PERFCTRL_VPEID_S)

#define M_COUNTER_OVERFLOW		(1UL	  << 31)

static int (*save_perf_irq)(void);
static int perfcount_irq;

/*
 * XLR has only one set of counters per core. Designate the
 * first hardware thread in the core for setup and init.
 * Skip CPUs with non-zero hardware thread id (4 hwt per core)
 */
#if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
#define oprofile_skip_cpu(c)	((cpu_logical_map(c) & 0x3) != 0)
#else
#define oprofile_skip_cpu(c)	0
#endif

#ifdef CONFIG_MIPS_MT_SMP
#define WHAT		(MIPS_PERFCTRL_MT_EN_VPE | \
			 M_PERFCTL_VPEID(cpu_vpe_id(&current_cpu_data)))
#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
			0 : cpu_vpe_id(&current_cpu_data))

/*
 * The number of bits to shift to convert between counters per core and
 * counters per VPE.  There is no reasonable interface atm to obtain the
 * number of VPEs used by Linux and in the 34K this number is fixed to two
 * anyways so we hardcore a few things here for the moment.  The way it's
 * done here will ensure that oprofile VSMP kernel will run right on a lesser
 * core like a 24K also or with maxcpus=1.
 */
static inline unsigned int vpe_shift(void)
{
	if (num_possible_cpus() > 1)
		return 1;

	return 0;
}

#else

#define WHAT		0
#define vpe_id()	0

static inline unsigned int vpe_shift(void)
{
	return 0;
}

#endif

static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
{
	return counters >> vpe_shift();
}

static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
{
	return counters << vpe_shift();
}

#define __define_perf_accessors(r, n, np)				\
									\
static inline unsigned int r_c0_ ## r ## n(void)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		return read_c0_ ## r ## n();				\
	case 1:								\
		return read_c0_ ## r ## np();				\
	default:							\
		BUG();							\
	}								\
	return 0;							\
}									\
									\
static inline void w_c0_ ## r ## n(unsigned int value)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		write_c0_ ## r ## n(value);				\
		return;							\
	case 1:								\
		write_c0_ ## r ## np(value);				\
		return;							\
	default:							\
		BUG();							\
	}								\
	return;								\
}									\

__define_perf_accessors(perfcntr, 0, 2)
__define_perf_accessors(perfcntr, 1, 3)
__define_perf_accessors(perfcntr, 2, 0)
__define_perf_accessors(perfcntr, 3, 1)

__define_perf_accessors(perfctrl, 0, 2)
__define_perf_accessors(perfctrl, 1, 3)
__define_perf_accessors(perfctrl, 2, 0)
__define_perf_accessors(perfctrl, 3, 1)

struct op_mips_model op_model_mipsxx_ops;

static struct mipsxx_register_config {
	unsigned int control[4];
	unsigned int counter[4];
} reg;

/* Compute all of the registers in preparation for enabling profiling.	*/

static void mipsxx_reg_setup(struct op_counter_config *ctr)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	int i;

	/* Compute the performance counter control word.  */
	for (i = 0; i < counters; i++) {
		reg.control[i] = 0;
		reg.counter[i] = 0;

		if (!ctr[i].enabled)
			continue;

		reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
				 MIPS_PERFCTRL_IE;
		if (ctr[i].kernel)
			reg.control[i] |= MIPS_PERFCTRL_K;
		if (ctr[i].user)
			reg.control[i] |= MIPS_PERFCTRL_U;
		if (ctr[i].exl)
			reg.control[i] |= MIPS_PERFCTRL_EXL;
		if (boot_cpu_type() == CPU_XLR)
			reg.control[i] |= XLR_PERFCTRL_ALLTHREADS;
		reg.counter[i] = 0x80000000 - ctr[i].count;
	}
}

/* Program all of the registers in preparation for enabling profiling.	*/

static void mipsxx_cpu_setup(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	if (oprofile_skip_cpu(smp_processor_id()))
		return;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(reg.counter[3]);
		/* fall through */
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(reg.counter[2]);
		/* fall through */
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(reg.counter[1]);
		/* fall through */
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(reg.counter[0]);
	}
}

/* Start all counters on current CPU */
static void mipsxx_cpu_start(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	if (oprofile_skip_cpu(smp_processor_id()))
		return;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(WHAT | reg.control[3]);
		/* fall through */
	case 3:
		w_c0_perfctrl2(WHAT | reg.control[2]);
		/* fall through */
	case 2:
		w_c0_perfctrl1(WHAT | reg.control[1]);
		/* fall through */
	case 1:
		w_c0_perfctrl0(WHAT | reg.control[0]);
	}
}

/* Stop all counters on current CPU */
static void mipsxx_cpu_stop(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	if (oprofile_skip_cpu(smp_processor_id()))
		return;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		/* fall through */
	case 3:
		w_c0_perfctrl2(0);
		/* fall through */
	case 2:
		w_c0_perfctrl1(0);
		/* fall through */
	case 1:
		w_c0_perfctrl0(0);
	}
}

static int mipsxx_perfcount_handler(void)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	unsigned int control;
	unsigned int counter;
	int handled = IRQ_NONE;

	if (cpu_has_mips_r2 && !(read_c0_cause() & CAUSEF_PCI))
		return handled;

	switch (counters) {
#define HANDLE_COUNTER(n)						\
	/* fall through */						\
	case n + 1:							\
		control = r_c0_perfctrl ## n();				\
		counter = r_c0_perfcntr ## n();				\
		if ((control & MIPS_PERFCTRL_IE) &&			\
		    (counter & M_COUNTER_OVERFLOW)) {			\
			oprofile_add_sample(get_irq_regs(), n);		\
			w_c0_perfcntr ## n(reg.counter[n]);		\
			handled = IRQ_HANDLED;				\
		}
	HANDLE_COUNTER(3)
	HANDLE_COUNTER(2)
	HANDLE_COUNTER(1)
	HANDLE_COUNTER(0)
	}

	return handled;
}

static inline int __n_counters(void)
{
	if (!cpu_has_perf)
		return 0;
	if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
		return 1;
	if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
		return 2;
	if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
		return 3;

	return 4;
}

static inline int n_counters(void)
{
	int counters;

	switch (current_cpu_type()) {
	case CPU_R10000:
		counters = 2;
		break;

	case CPU_R12000:
	case CPU_R14000:
	case CPU_R16000:
		counters = 4;
		break;

	default:
		counters = __n_counters();
	}

	return counters;
}

static void reset_counters(void *arg)
{
	int counters = (int)(long)arg;
	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(0);
		/* fall through */
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(0);
		/* fall through */
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(0);
		/* fall through */
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(0);
	}
}

static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
{
	return mipsxx_perfcount_handler();
}

static int __init mipsxx_init(void)
{
	int counters;

	counters = n_counters();
	if (counters == 0) {
		printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
		return -ENODEV;
	}

#ifdef CONFIG_MIPS_MT_SMP
	if (!cpu_has_mipsmt_pertccounters)
		counters = counters_total_to_per_cpu(counters);
#endif
	on_each_cpu(reset_counters, (void *)(long)counters, 1);

	op_model_mipsxx_ops.num_counters = counters;
	switch (current_cpu_type()) {
	case CPU_M14KC:
		op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
		break;

	case CPU_M14KEC:
		op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
		break;

	case CPU_20KC:
		op_model_mipsxx_ops.cpu_type = "mips/20K";
		break;

	case CPU_24K:
		op_model_mipsxx_ops.cpu_type = "mips/24K";
		break;

	case CPU_25KF:
		op_model_mipsxx_ops.cpu_type = "mips/25K";
		break;

	case CPU_1004K:
	case CPU_34K:
		op_model_mipsxx_ops.cpu_type = "mips/34K";
		break;

	case CPU_1074K:
	case CPU_74K:
		op_model_mipsxx_ops.cpu_type = "mips/74K";
		break;

	case CPU_INTERAPTIV:
		op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
		break;

	case CPU_PROAPTIV:
		op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
		break;

	case CPU_P5600:
		op_model_mipsxx_ops.cpu_type = "mips/P5600";
		break;

	case CPU_I6400:
		op_model_mipsxx_ops.cpu_type = "mips/I6400";
		break;

	case CPU_M5150:
		op_model_mipsxx_ops.cpu_type = "mips/M5150";
		break;

	case CPU_5KC:
		op_model_mipsxx_ops.cpu_type = "mips/5K";
		break;

	case CPU_R10000:
		if ((current_cpu_data.processor_id & 0xff) == 0x20)
			op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
		else
			op_model_mipsxx_ops.cpu_type = "mips/r10000";
		break;

	case CPU_R12000:
	case CPU_R14000:
		op_model_mipsxx_ops.cpu_type = "mips/r12000";
		break;

	case CPU_R16000:
		op_model_mipsxx_ops.cpu_type = "mips/r16000";
		break;

	case CPU_SB1:
	case CPU_SB1A:
		op_model_mipsxx_ops.cpu_type = "mips/sb1";
		break;

	case CPU_LOONGSON32:
		op_model_mipsxx_ops.cpu_type = "mips/loongson1";
		break;

	case CPU_XLR:
		op_model_mipsxx_ops.cpu_type = "mips/xlr";
		break;

	default:
		printk(KERN_ERR "Profiling unsupported for this CPU\n");

		return -ENODEV;
	}

	save_perf_irq = perf_irq;
	perf_irq = mipsxx_perfcount_handler;

	if (get_c0_perfcount_int)
		perfcount_irq = get_c0_perfcount_int();
	else if (cp0_perfcount_irq >= 0)
		perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
	else
		perfcount_irq = -1;

	if (perfcount_irq >= 0)
		return request_irq(perfcount_irq, mipsxx_perfcount_int,
				   IRQF_PERCPU | IRQF_NOBALANCING |
				   IRQF_NO_THREAD | IRQF_NO_SUSPEND |
				   IRQF_SHARED,
				   "Perfcounter", save_perf_irq);

	return 0;
}

static void mipsxx_exit(void)
{
	int counters = op_model_mipsxx_ops.num_counters;

	if (perfcount_irq >= 0)
		free_irq(perfcount_irq, save_perf_irq);

	counters = counters_per_cpu_to_total(counters);
	on_each_cpu(reset_counters, (void *)(long)counters, 1);

	perf_irq = save_perf_irq;
}

struct op_mips_model op_model_mipsxx_ops = {
	.reg_setup	= mipsxx_reg_setup,
	.cpu_setup	= mipsxx_cpu_setup,
	.init		= mipsxx_init,
	.exit		= mipsxx_exit,
	.cpu_start	= mipsxx_cpu_start,
	.cpu_stop	= mipsxx_cpu_stop,
};
Commit	Line	Data
54176736 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
937a8015	6	* Copyright (C) 2004, 05, 06 by Ralf Baechle
54176736 RB	7	* Copyright (C) 2005 by MIPS Technologies, Inc.
54176736 RB	8	*/
5e2862eb	9	#include <linux/cpumask.h>
54176736 RB	10	#include <linux/oprofile.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/smp.h>
937a8015	13	#include <asm/irq_regs.h>
a669efc4	14	#include <asm/time.h>
54176736 RB	15
	16	#include "op_impl.h"
	17
2654294b JH	18	#define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
	19	MIPS_PERFCTRL_EVENT)
	20	#define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)
92c7b62f	21
70342287	22	#define M_COUNTER_OVERFLOW (1UL << 31)
92c7b62f	23
46684734	24	static int (*save_perf_irq)(void);
a669efc4	25	static int perfcount_irq;
46684734	26
c783390a MB	27	/*
	28	* XLR has only one set of counters per core. Designate the
	29	* first hardware thread in the core for setup and init.
	30	* Skip CPUs with non-zero hardware thread id (4 hwt per core)
	31	*/
83a18415	32	#if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
c783390a MB	33	#define oprofile_skip_cpu(c) ((cpu_logical_map(c) & 0x3) != 0)
	34	#else
	35	#define oprofile_skip_cpu(c) 0
	36	#endif
	37
92c7b62f	38	#ifdef CONFIG_MIPS_MT_SMP
2654294b	39	#define WHAT (MIPS_PERFCTRL_MT_EN_VPE \| \
f875a832	40	M_PERFCTL_VPEID(cpu_vpe_id(&current_cpu_data)))
39b8d525	41	#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
f875a832	42	0 : cpu_vpe_id(&current_cpu_data))
5e2862eb RB	43
	44	/*
	45	* The number of bits to shift to convert between counters per core and
	46	* counters per VPE. There is no reasonable interface atm to obtain the
	47	* number of VPEs used by Linux and in the 34K this number is fixed to two
	48	* anyways so we hardcore a few things here for the moment. The way it's
	49	* done here will ensure that oprofile VSMP kernel will run right on a lesser
	50	* core like a 24K also or with maxcpus=1.
	51	*/
	52	static inline unsigned int vpe_shift(void)
	53	{
	54	if (num_possible_cpus() > 1)
	55	return 1;
	56
	57	return 0;
	58	}
	59
92c7b62f	60	#else
5e2862eb	61
be609f35	62	#define WHAT 0
6f4c5bde	63	#define vpe_id() 0
5e2862eb RB	64
	65	static inline unsigned int vpe_shift(void)
	66	{
	67	return 0;
	68	}
	69
92c7b62f	70	#endif
54176736	71
5e2862eb RB	72	static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
	73	{
	74	return counters >> vpe_shift();
	75	}
	76
	77	static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
	78	{
	79	return counters << vpe_shift();
	80	}
	81
92c7b62f RB	82	#define __define_perf_accessors(r, n, np) \
	83	\
	84	static inline unsigned int r_c0_ ## r ## n(void) \
	85	{ \
be609f35	86	unsigned int cpu = vpe_id(); \
92c7b62f RB	87	\
	88	switch (cpu) { \
	89	case 0: \
	90	return read_c0_ ## r ## n(); \
	91	case 1: \
	92	return read_c0_ ## r ## np(); \
	93	default: \
	94	BUG(); \
	95	} \
30f244ae	96	return 0; \
92c7b62f RB	97	} \
	98	\
	99	static inline void w_c0_ ## r ## n(unsigned int value) \
	100	{ \
be609f35	101	unsigned int cpu = vpe_id(); \
92c7b62f RB	102	\
	103	switch (cpu) { \
	104	case 0: \
	105	write_c0_ ## r ## n(value); \
	106	return; \
	107	case 1: \
	108	write_c0_ ## r ## np(value); \
	109	return; \
	110	default: \
	111	BUG(); \
	112	} \
30f244ae	113	return; \
92c7b62f RB	114	} \
	115
	116	__define_perf_accessors(perfcntr, 0, 2)
	117	__define_perf_accessors(perfcntr, 1, 3)
795a2258 CD	118	__define_perf_accessors(perfcntr, 2, 0)
795a2258 CD	119	__define_perf_accessors(perfcntr, 3, 1)
92c7b62f RB	120
	121	__define_perf_accessors(perfctrl, 0, 2)
	122	__define_perf_accessors(perfctrl, 1, 3)
795a2258 CD	123	__define_perf_accessors(perfctrl, 2, 0)
795a2258 CD	124	__define_perf_accessors(perfctrl, 3, 1)
54176736	125
1acf1ca7	126	struct op_mips_model op_model_mipsxx_ops;
54176736 RB	127
	128	static struct mipsxx_register_config {
	129	unsigned int control[4];
	130	unsigned int counter[4];
	131	} reg;
	132
70342287	133	/* Compute all of the registers in preparation for enabling profiling. */
54176736 RB	134
	135	static void mipsxx_reg_setup(struct op_counter_config *ctr)
	136	{
1acf1ca7	137	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	138	int i;
	139
	140	/* Compute the performance counter control word. */
54176736 RB	141	for (i = 0; i < counters; i++) {
	142	reg.control[i] = 0;
	143	reg.counter[i] = 0;
	144
	145	if (!ctr[i].enabled)
	146	continue;
	147
	148	reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) \|
2654294b	149	MIPS_PERFCTRL_IE;
54176736	150	if (ctr[i].kernel)
2654294b	151	reg.control[i] \|= MIPS_PERFCTRL_K;
54176736	152	if (ctr[i].user)
2654294b	153	reg.control[i] \|= MIPS_PERFCTRL_U;
54176736	154	if (ctr[i].exl)
2654294b	155	reg.control[i] \|= MIPS_PERFCTRL_EXL;
cf5b2d23	156	if (boot_cpu_type() == CPU_XLR)
2654294b	157	reg.control[i] \|= XLR_PERFCTRL_ALLTHREADS;
54176736 RB	158	reg.counter[i] = 0x80000000 - ctr[i].count;
	159	}
	160	}
	161
70342287	162	/* Program all of the registers in preparation for enabling profiling. */
54176736	163
49a89efb	164	static void mipsxx_cpu_setup(void *args)
54176736	165	{
1acf1ca7	166	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736	167
c783390a MB	168	if (oprofile_skip_cpu(smp_processor_id()))
	169	return;
	170
54176736 RB	171	switch (counters) {
54176736 RB	172	case 4:
92c7b62f RB	173	w_c0_perfctrl3(0);
92c7b62f RB	174	w_c0_perfcntr3(reg.counter[3]);
2d291e6c	175	/* fall through */
54176736	176	case 3:
92c7b62f RB	177	w_c0_perfctrl2(0);
92c7b62f RB	178	w_c0_perfcntr2(reg.counter[2]);
2d291e6c	179	/* fall through */
54176736	180	case 2:
92c7b62f RB	181	w_c0_perfctrl1(0);
92c7b62f RB	182	w_c0_perfcntr1(reg.counter[1]);
2d291e6c	183	/* fall through */
54176736	184	case 1:
92c7b62f RB	185	w_c0_perfctrl0(0);
92c7b62f RB	186	w_c0_perfcntr0(reg.counter[0]);
54176736 RB	187	}
	188	}
	189
	190	/* Start all counters on current CPU */
	191	static void mipsxx_cpu_start(void *args)
	192	{
1acf1ca7	193	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736	194
c783390a MB	195	if (oprofile_skip_cpu(smp_processor_id()))
	196	return;
	197
54176736 RB	198	switch (counters) {
54176736 RB	199	case 4:
92c7b62f	200	w_c0_perfctrl3(WHAT \| reg.control[3]);
2d291e6c	201	/* fall through */
54176736	202	case 3:
92c7b62f	203	w_c0_perfctrl2(WHAT \| reg.control[2]);
2d291e6c	204	/* fall through */
54176736	205	case 2:
92c7b62f	206	w_c0_perfctrl1(WHAT \| reg.control[1]);
2d291e6c	207	/* fall through */
54176736	208	case 1:
92c7b62f	209	w_c0_perfctrl0(WHAT \| reg.control[0]);
54176736 RB	210	}
	211	}
	212
	213	/* Stop all counters on current CPU */
	214	static void mipsxx_cpu_stop(void *args)
	215	{
1acf1ca7	216	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736	217
c783390a MB	218	if (oprofile_skip_cpu(smp_processor_id()))
	219	return;
	220
54176736 RB	221	switch (counters) {
54176736 RB	222	case 4:
92c7b62f	223	w_c0_perfctrl3(0);
2d291e6c	224	/* fall through */
54176736	225	case 3:
92c7b62f	226	w_c0_perfctrl2(0);
2d291e6c	227	/* fall through */
54176736	228	case 2:
92c7b62f	229	w_c0_perfctrl1(0);
2d291e6c	230	/* fall through */
54176736	231	case 1:
92c7b62f	232	w_c0_perfctrl0(0);
54176736 RB	233	}
	234	}
	235
937a8015	236	static int mipsxx_perfcount_handler(void)
54176736	237	{
1acf1ca7	238	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	239	unsigned int control;
54176736 RB	240	unsigned int counter;
ffe9ee47 CD	241	int handled = IRQ_NONE;
ffe9ee47 CD	242
3ba5040a	243	if (cpu_has_mips_r2 && !(read_c0_cause() & CAUSEF_PCI))
ffe9ee47	244	return handled;
54176736 RB	245
	246	switch (counters) {
	247	#define HANDLE_COUNTER(n) \
2d291e6c	248	/* fall through */ \
54176736	249	case n + 1: \
92c7b62f RB	250	control = r_c0_perfctrl ## n(); \
92c7b62f RB	251	counter = r_c0_perfcntr ## n(); \
2654294b	252	if ((control & MIPS_PERFCTRL_IE) && \
54176736	253	(counter & M_COUNTER_OVERFLOW)) { \
937a8015	254	oprofile_add_sample(get_irq_regs(), n); \
92c7b62f	255	w_c0_perfcntr ## n(reg.counter[n]); \
ffe9ee47	256	handled = IRQ_HANDLED; \
54176736 RB	257	}
	258	HANDLE_COUNTER(3)
	259	HANDLE_COUNTER(2)
	260	HANDLE_COUNTER(1)
	261	HANDLE_COUNTER(0)
	262	}
ba339c03 RB	263
ba339c03 RB	264	return handled;
54176736 RB	265	}
54176736 RB	266
92c7b62f	267	static inline int __n_counters(void)
54176736	268	{
30228c40	269	if (!cpu_has_perf)
54176736	270	return 0;
2654294b	271	if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
54176736	272	return 1;
2654294b	273	if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
54176736	274	return 2;
2654294b	275	if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
54176736 RB	276	return 3;
	277
	278	return 4;
	279	}
	280
92c7b62f RB	281	static inline int n_counters(void)
92c7b62f RB	282	{
714cfe78 RB	283	int counters;
714cfe78 RB	284
10cc3529	285	switch (current_cpu_type()) {
714cfe78 RB	286	case CPU_R10000:
714cfe78 RB	287	counters = 2;
148171b2	288	break;
714cfe78 RB	289
	290	case CPU_R12000:
	291	case CPU_R14000:
30577391	292	case CPU_R16000:
714cfe78	293	counters = 4;
148171b2	294	break;
714cfe78 RB	295
	296	default:
	297	counters = __n_counters();
	298	}
92c7b62f	299
92c7b62f RB	300	return counters;
	301	}
	302
39b8d525	303	static void reset_counters(void *arg)
54176736	304	{
005ca9a3	305	int counters = (int)(long)arg;
54176736 RB	306	switch (counters) {
54176736 RB	307	case 4:
92c7b62f RB	308	w_c0_perfctrl3(0);
92c7b62f RB	309	w_c0_perfcntr3(0);
2d291e6c	310	/* fall through */
54176736	311	case 3:
92c7b62f RB	312	w_c0_perfctrl2(0);
92c7b62f RB	313	w_c0_perfcntr2(0);
2d291e6c	314	/* fall through */
54176736	315	case 2:
92c7b62f RB	316	w_c0_perfctrl1(0);
92c7b62f RB	317	w_c0_perfcntr1(0);
2d291e6c	318	/* fall through */
54176736	319	case 1:
92c7b62f RB	320	w_c0_perfctrl0(0);
92c7b62f RB	321	w_c0_perfcntr0(0);
54176736 RB	322	}
	323	}
	324
3572a2c3 FF	325	static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
	326	{
	327	return mipsxx_perfcount_handler();
	328	}
	329
54176736 RB	330	static int __init mipsxx_init(void)
	331	{
	332	int counters;
	333
	334	counters = n_counters();
9efeae9a RB	335	if (counters == 0) {
9efeae9a RB	336	printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
54176736	337	return -ENODEV;
9efeae9a	338	}
54176736	339
39b8d525	340	#ifdef CONFIG_MIPS_MT_SMP
39b8d525 RB	341	if (!cpu_has_mipsmt_pertccounters)
	342	counters = counters_total_to_per_cpu(counters);
	343	#endif
f6f88e9b	344	on_each_cpu(reset_counters, (void *)(long)counters, 1);
795a2258	345
1acf1ca7	346	op_model_mipsxx_ops.num_counters = counters;
10cc3529	347	switch (current_cpu_type()) {
113c62d9 SH	348	case CPU_M14KC:
	349	op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
	350	break;
	351
f8fa4811 SH	352	case CPU_M14KEC:
	353	op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
	354	break;
	355
2065988e	356	case CPU_20KC:
1acf1ca7	357	op_model_mipsxx_ops.cpu_type = "mips/20K";
2065988e RB	358	break;
2065988e RB	359
54176736	360	case CPU_24K:
1acf1ca7	361	op_model_mipsxx_ops.cpu_type = "mips/24K";
54176736 RB	362	break;
54176736 RB	363
2065988e	364	case CPU_25KF:
1acf1ca7	365	op_model_mipsxx_ops.cpu_type = "mips/25K";
2065988e RB	366	break;
2065988e RB	367
39b8d525	368	case CPU_1004K:
fcfd980c	369	case CPU_34K:
1acf1ca7	370	op_model_mipsxx_ops.cpu_type = "mips/34K";
fcfd980c	371	break;
c620953c	372
442e14a2	373	case CPU_1074K:
c620953c	374	case CPU_74K:
1acf1ca7	375	op_model_mipsxx_ops.cpu_type = "mips/74K";
c620953c	376	break;
fcfd980c	377
26ab96df LY	378	case CPU_INTERAPTIV:
	379	op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
	380	break;
	381
708ac4b8 LY	382	case CPU_PROAPTIV:
	383	op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
	384	break;
	385
8c7f6ba3 JH	386	case CPU_P5600:
	387	op_model_mipsxx_ops.cpu_type = "mips/P5600";
	388	break;
	389
4e88a862 MC	390	case CPU_I6400:
	391	op_model_mipsxx_ops.cpu_type = "mips/I6400";
	392	break;
	393
f36c4720 LY	394	case CPU_M5150:
	395	op_model_mipsxx_ops.cpu_type = "mips/M5150";
	396	break;
	397
2065988e	398	case CPU_5KC:
1acf1ca7	399	op_model_mipsxx_ops.cpu_type = "mips/5K";
2065988e RB	400	break;
2065988e RB	401
714cfe78 RB	402	case CPU_R10000:
	403	if ((current_cpu_data.processor_id & 0xff) == 0x20)
	404	op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
	405	else
	406	op_model_mipsxx_ops.cpu_type = "mips/r10000";
	407	break;
	408
	409	case CPU_R12000:
	410	case CPU_R14000:
	411	op_model_mipsxx_ops.cpu_type = "mips/r12000";
	412	break;
	413
30577391 JK	414	case CPU_R16000:
	415	op_model_mipsxx_ops.cpu_type = "mips/r16000";
	416	break;
	417
c03bc121 MM	418	case CPU_SB1:
c03bc121 MM	419	case CPU_SB1A:
1acf1ca7	420	op_model_mipsxx_ops.cpu_type = "mips/sb1";
c03bc121 MM	421	break;
c03bc121 MM	422
b2afb64c	423	case CPU_LOONGSON32:
2fa36399 KC	424	op_model_mipsxx_ops.cpu_type = "mips/loongson1";
	425	break;
	426
c783390a MB	427	case CPU_XLR:
	428	op_model_mipsxx_ops.cpu_type = "mips/xlr";
	429	break;
	430
54176736 RB	431	default:
	432	printk(KERN_ERR "Profiling unsupported for this CPU\n");
	433
	434	return -ENODEV;
	435	}
	436
46684734	437	save_perf_irq = perf_irq;
54176736 RB	438	perf_irq = mipsxx_perfcount_handler;
54176736 RB	439
a669efc4 AB	440	if (get_c0_perfcount_int)
a669efc4 AB	441	perfcount_irq = get_c0_perfcount_int();
7eca5b14	442	else if (cp0_perfcount_irq >= 0)
a669efc4 AB	443	perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
	444	else
	445	perfcount_irq = -1;
	446
	447	if (perfcount_irq >= 0)
	448	return request_irq(perfcount_irq, mipsxx_perfcount_int,
369a93bb JH	449	IRQF_PERCPU \| IRQF_NOBALANCING \|
	450	IRQF_NO_THREAD \| IRQF_NO_SUSPEND \|
	451	IRQF_SHARED,
	452	"Perfcounter", save_perf_irq);
3572a2c3	453
54176736 RB	454	return 0;
	455	}
	456
	457	static void mipsxx_exit(void)
	458	{
795a2258	459	int counters = op_model_mipsxx_ops.num_counters;
5e2862eb	460
a669efc4 AB	461	if (perfcount_irq >= 0)
a669efc4 AB	462	free_irq(perfcount_irq, save_perf_irq);
3572a2c3	463
5e2862eb	464	counters = counters_per_cpu_to_total(counters);
f6f88e9b	465	on_each_cpu(reset_counters, (void *)(long)counters, 1);
54176736	466
46684734	467	perf_irq = save_perf_irq;
54176736 RB	468	}
54176736 RB	469
1acf1ca7	470	struct op_mips_model op_model_mipsxx_ops = {
54176736 RB	471	.reg_setup = mipsxx_reg_setup,
	472	.cpu_setup = mipsxx_cpu_setup,
	473	.init = mipsxx_init,
	474	.exit = mipsxx_exit,
	475	.cpu_start = mipsxx_cpu_start,
	476	.cpu_stop = mipsxx_cpu_stop,
	477	};