[linux-2.6-block.git] / arch / mips / oprofile / op_model_mipsxx.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004, 05, 06 by Ralf Baechle
 * Copyright (C) 2005 by MIPS Technologies, Inc.
 */
#include <linux/cpumask.h>
#include <linux/oprofile.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <asm/irq_regs.h>
#include <asm/time.h>

#include "op_impl.h"

#define M_PERFCTL_EXL			(1UL	  <<  0)
#define M_PERFCTL_KERNEL		(1UL	  <<  1)
#define M_PERFCTL_SUPERVISOR		(1UL	  <<  2)
#define M_PERFCTL_USER			(1UL	  <<  3)
#define M_PERFCTL_INTERRUPT_ENABLE	(1UL	  <<  4)
#define M_PERFCTL_EVENT(event)		(((event) & 0x3ff)  << 5)
#define M_PERFCTL_VPEID(vpe)		((vpe)	  << 16)
#define M_PERFCTL_MT_EN(filter)		((filter) << 20)
#define	   M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
#define	   M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
#define	   M_TC_EN_TC			M_PERFCTL_MT_EN(2)
#define M_PERFCTL_TCID(tcid)		((tcid)	  << 22)
#define M_PERFCTL_WIDE			(1UL	  << 30)
#define M_PERFCTL_MORE			(1UL	  << 31)

#define M_COUNTER_OVERFLOW		(1UL	  << 31)

/* Netlogic XLR specific, count events in all threads in a core */
#define M_PERFCTL_COUNT_ALL_THREADS	(1UL	  << 13)

static int (*save_perf_irq)(void);
static int perfcount_irq;

/*
 * XLR has only one set of counters per core. Designate the
 * first hardware thread in the core for setup and init.
 * Skip CPUs with non-zero hardware thread id (4 hwt per core)
 */
#if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
#define oprofile_skip_cpu(c)	((cpu_logical_map(c) & 0x3) != 0)
#else
#define oprofile_skip_cpu(c)	0
#endif

#ifdef CONFIG_MIPS_MT_SMP
static int cpu_has_mipsmt_pertccounters;
#define WHAT		(M_TC_EN_VPE | \
			 M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
			0 : cpu_data[smp_processor_id()].vpe_id)

/*
 * The number of bits to shift to convert between counters per core and
 * counters per VPE.  There is no reasonable interface atm to obtain the
 * number of VPEs used by Linux and in the 34K this number is fixed to two
 * anyways so we hardcore a few things here for the moment.  The way it's
 * done here will ensure that oprofile VSMP kernel will run right on a lesser
 * core like a 24K also or with maxcpus=1.
 */
static inline unsigned int vpe_shift(void)
{
	if (num_possible_cpus() > 1)
		return 1;

	return 0;
}

#else

#define WHAT		0
#define vpe_id()	0

static inline unsigned int vpe_shift(void)
{
	return 0;
}

#endif

static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
{
	return counters >> vpe_shift();
}

static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
{
	return counters << vpe_shift();
}

#define __define_perf_accessors(r, n, np)				\
									\
static inline unsigned int r_c0_ ## r ## n(void)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		return read_c0_ ## r ## n();				\
	case 1:								\
		return read_c0_ ## r ## np();				\
	default:							\
		BUG();							\
	}								\
	return 0;							\
}									\
									\
static inline void w_c0_ ## r ## n(unsigned int value)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		write_c0_ ## r ## n(value);				\
		return;							\
	case 1:								\
		write_c0_ ## r ## np(value);				\
		return;							\
	default:							\
		BUG();							\
	}								\
	return;								\
}									\

__define_perf_accessors(perfcntr, 0, 2)
__define_perf_accessors(perfcntr, 1, 3)
__define_perf_accessors(perfcntr, 2, 0)
__define_perf_accessors(perfcntr, 3, 1)

__define_perf_accessors(perfctrl, 0, 2)
__define_perf_accessors(perfctrl, 1, 3)
__define_perf_accessors(perfctrl, 2, 0)
__define_perf_accessors(perfctrl, 3, 1)

struct op_mips_model op_model_mipsxx_ops;

static struct mipsxx_register_config {
	unsigned int control[4];
	unsigned int counter[4];
} reg;

/* Compute all of the registers in preparation for enabling profiling.	*/

static void mipsxx_reg_setup(struct op_counter_config *ctr)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	int i;

	/* Compute the performance counter control word.  */
	for (i = 0; i < counters; i++) {
		reg.control[i] = 0;
		reg.counter[i] = 0;

		if (!ctr[i].enabled)
			continue;

		reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
				 M_PERFCTL_INTERRUPT_ENABLE;
		if (ctr[i].kernel)
			reg.control[i] |= M_PERFCTL_KERNEL;
		if (ctr[i].user)
			reg.control[i] |= M_PERFCTL_USER;
		if (ctr[i].exl)
			reg.control[i] |= M_PERFCTL_EXL;
		if (boot_cpu_type() == CPU_XLR)
			reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS;
		reg.counter[i] = 0x80000000 - ctr[i].count;
	}
}

/* Program all of the registers in preparation for enabling profiling.	*/

static void mipsxx_cpu_setup(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	if (oprofile_skip_cpu(smp_processor_id()))
		return;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(reg.counter[3]);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(reg.counter[2]);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(reg.counter[1]);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(reg.counter[0]);
	}
}

/* Start all counters on current CPU */
static void mipsxx_cpu_start(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	if (oprofile_skip_cpu(smp_processor_id()))
		return;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(WHAT | reg.control[3]);
	case 3:
		w_c0_perfctrl2(WHAT | reg.control[2]);
	case 2:
		w_c0_perfctrl1(WHAT | reg.control[1]);
	case 1:
		w_c0_perfctrl0(WHAT | reg.control[0]);
	}
}

/* Stop all counters on current CPU */
static void mipsxx_cpu_stop(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	if (oprofile_skip_cpu(smp_processor_id()))
		return;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
	case 3:
		w_c0_perfctrl2(0);
	case 2:
		w_c0_perfctrl1(0);
	case 1:
		w_c0_perfctrl0(0);
	}
}

static int mipsxx_perfcount_handler(void)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	unsigned int control;
	unsigned int counter;
	int handled = IRQ_NONE;

	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
		return handled;

	switch (counters) {
#define HANDLE_COUNTER(n)						\
	case n + 1:							\
		control = r_c0_perfctrl ## n();				\
		counter = r_c0_perfcntr ## n();				\
		if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&		\
		    (counter & M_COUNTER_OVERFLOW)) {			\
			oprofile_add_sample(get_irq_regs(), n);		\
			w_c0_perfcntr ## n(reg.counter[n]);		\
			handled = IRQ_HANDLED;				\
		}
	HANDLE_COUNTER(3)
	HANDLE_COUNTER(2)
	HANDLE_COUNTER(1)
	HANDLE_COUNTER(0)
	}

	return handled;
}

#define M_CONFIG1_PC	(1 << 4)

static inline int __n_counters(void)
{
	if (!(read_c0_config1() & M_CONFIG1_PC))
		return 0;
	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
		return 1;
	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
		return 2;
	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
		return 3;

	return 4;
}

static inline int n_counters(void)
{
	int counters;

	switch (current_cpu_type()) {
	case CPU_R10000:
		counters = 2;
		break;

	case CPU_R12000:
	case CPU_R14000:
		counters = 4;
		break;

	default:
		counters = __n_counters();
	}

	return counters;
}

static void reset_counters(void *arg)
{
	int counters = (int)(long)arg;
	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(0);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(0);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(0);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(0);
	}
}

static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
{
	return mipsxx_perfcount_handler();
}

static int __init mipsxx_init(void)
{
	int counters;

	counters = n_counters();
	if (counters == 0) {
		printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
		return -ENODEV;
	}

#ifdef CONFIG_MIPS_MT_SMP
	cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
	if (!cpu_has_mipsmt_pertccounters)
		counters = counters_total_to_per_cpu(counters);
#endif
	on_each_cpu(reset_counters, (void *)(long)counters, 1);

	op_model_mipsxx_ops.num_counters = counters;
	switch (current_cpu_type()) {
	case CPU_M14KC:
		op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
		break;

	case CPU_M14KEC:
		op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
		break;

	case CPU_20KC:
		op_model_mipsxx_ops.cpu_type = "mips/20K";
		break;

	case CPU_24K:
		op_model_mipsxx_ops.cpu_type = "mips/24K";
		break;

	case CPU_25KF:
		op_model_mipsxx_ops.cpu_type = "mips/25K";
		break;

	case CPU_1004K:
	case CPU_34K:
		op_model_mipsxx_ops.cpu_type = "mips/34K";
		break;

	case CPU_1074K:
	case CPU_74K:
		op_model_mipsxx_ops.cpu_type = "mips/74K";
		break;

	case CPU_INTERAPTIV:
		op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
		break;

	case CPU_PROAPTIV:
		op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
		break;

	case CPU_P5600:
		op_model_mipsxx_ops.cpu_type = "mips/P5600";
		break;

	case CPU_M5150:
		op_model_mipsxx_ops.cpu_type = "mips/M5150";
		break;

	case CPU_5KC:
		op_model_mipsxx_ops.cpu_type = "mips/5K";
		break;

	case CPU_R10000:
		if ((current_cpu_data.processor_id & 0xff) == 0x20)
			op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
		else
			op_model_mipsxx_ops.cpu_type = "mips/r10000";
		break;

	case CPU_R12000:
	case CPU_R14000:
		op_model_mipsxx_ops.cpu_type = "mips/r12000";
		break;

	case CPU_SB1:
	case CPU_SB1A:
		op_model_mipsxx_ops.cpu_type = "mips/sb1";
		break;

	case CPU_LOONGSON1:
		op_model_mipsxx_ops.cpu_type = "mips/loongson1";
		break;

	case CPU_XLR:
		op_model_mipsxx_ops.cpu_type = "mips/xlr";
		break;

	default:
		printk(KERN_ERR "Profiling unsupported for this CPU\n");

		return -ENODEV;
	}

	save_perf_irq = perf_irq;
	perf_irq = mipsxx_perfcount_handler;

	if (get_c0_perfcount_int)
		perfcount_irq = get_c0_perfcount_int();
	else if ((cp0_perfcount_irq >= 0) &&
		 (cp0_compare_irq != cp0_perfcount_irq))
		perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
	else
		perfcount_irq = -1;

	if (perfcount_irq >= 0)
		return request_irq(perfcount_irq, mipsxx_perfcount_int,
			0, "Perfcounter", save_perf_irq);

	return 0;
}

static void mipsxx_exit(void)
{
	int counters = op_model_mipsxx_ops.num_counters;

	if (perfcount_irq >= 0)
		free_irq(perfcount_irq, save_perf_irq);

	counters = counters_per_cpu_to_total(counters);
	on_each_cpu(reset_counters, (void *)(long)counters, 1);

	perf_irq = save_perf_irq;
}

struct op_mips_model op_model_mipsxx_ops = {
	.reg_setup	= mipsxx_reg_setup,
	.cpu_setup	= mipsxx_cpu_setup,
	.init		= mipsxx_init,
	.exit		= mipsxx_exit,
	.cpu_start	= mipsxx_cpu_start,
	.cpu_stop	= mipsxx_cpu_stop,
};
Commit	Line	Data
54176736 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
937a8015	6	* Copyright (C) 2004, 05, 06 by Ralf Baechle
54176736 RB	7	* Copyright (C) 2005 by MIPS Technologies, Inc.
54176736 RB	8	*/
5e2862eb	9	#include <linux/cpumask.h>
54176736 RB	10	#include <linux/oprofile.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/smp.h>
937a8015	13	#include <asm/irq_regs.h>
a669efc4	14	#include <asm/time.h>
54176736 RB	15
	16	#include "op_impl.h"
	17
70342287 RB	18	#define M_PERFCTL_EXL (1UL << 0)
	19	#define M_PERFCTL_KERNEL (1UL << 1)
	20	#define M_PERFCTL_SUPERVISOR (1UL << 2)
	21	#define M_PERFCTL_USER (1UL << 3)
	22	#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
39a51109	23	#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
70342287	24	#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
92c7b62f	25	#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
70342287 RB	26	#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
	27	#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
	28	#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
	29	#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
	30	#define M_PERFCTL_WIDE (1UL << 30)
	31	#define M_PERFCTL_MORE (1UL << 31)
92c7b62f	32
70342287	33	#define M_COUNTER_OVERFLOW (1UL << 31)
92c7b62f	34
c783390a	35	/* Netlogic XLR specific, count events in all threads in a core */
70342287	36	#define M_PERFCTL_COUNT_ALL_THREADS (1UL << 13)
c783390a	37
46684734	38	static int (*save_perf_irq)(void);
a669efc4	39	static int perfcount_irq;
46684734	40
c783390a MB	41	/*
	42	* XLR has only one set of counters per core. Designate the
	43	* first hardware thread in the core for setup and init.
	44	* Skip CPUs with non-zero hardware thread id (4 hwt per core)
	45	*/
83a18415	46	#if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
c783390a MB	47	#define oprofile_skip_cpu(c) ((cpu_logical_map(c) & 0x3) != 0)
	48	#else
	49	#define oprofile_skip_cpu(c) 0
	50	#endif
	51
92c7b62f	52	#ifdef CONFIG_MIPS_MT_SMP
39b8d525 RB	53	static int cpu_has_mipsmt_pertccounters;
	54	#define WHAT (M_TC_EN_VPE \| \
	55	M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
	56	#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
	57	0 : cpu_data[smp_processor_id()].vpe_id)
5e2862eb RB	58
	59	/*
	60	* The number of bits to shift to convert between counters per core and
	61	* counters per VPE. There is no reasonable interface atm to obtain the
	62	* number of VPEs used by Linux and in the 34K this number is fixed to two
	63	* anyways so we hardcore a few things here for the moment. The way it's
	64	* done here will ensure that oprofile VSMP kernel will run right on a lesser
	65	* core like a 24K also or with maxcpus=1.
	66	*/
	67	static inline unsigned int vpe_shift(void)
	68	{
	69	if (num_possible_cpus() > 1)
	70	return 1;
	71
	72	return 0;
	73	}
	74
92c7b62f	75	#else
5e2862eb	76
be609f35	77	#define WHAT 0
6f4c5bde	78	#define vpe_id() 0
5e2862eb RB	79
	80	static inline unsigned int vpe_shift(void)
	81	{
	82	return 0;
	83	}
	84
92c7b62f	85	#endif
54176736	86
5e2862eb RB	87	static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
	88	{
	89	return counters >> vpe_shift();
	90	}
	91
	92	static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
	93	{
	94	return counters << vpe_shift();
	95	}
	96
92c7b62f RB	97	#define __define_perf_accessors(r, n, np) \
	98	\
	99	static inline unsigned int r_c0_ ## r ## n(void) \
	100	{ \
be609f35	101	unsigned int cpu = vpe_id(); \
92c7b62f RB	102	\
	103	switch (cpu) { \
	104	case 0: \
	105	return read_c0_ ## r ## n(); \
	106	case 1: \
	107	return read_c0_ ## r ## np(); \
	108	default: \
	109	BUG(); \
	110	} \
30f244ae	111	return 0; \
92c7b62f RB	112	} \
	113	\
	114	static inline void w_c0_ ## r ## n(unsigned int value) \
	115	{ \
be609f35	116	unsigned int cpu = vpe_id(); \
92c7b62f RB	117	\
	118	switch (cpu) { \
	119	case 0: \
	120	write_c0_ ## r ## n(value); \
	121	return; \
	122	case 1: \
	123	write_c0_ ## r ## np(value); \
	124	return; \
	125	default: \
	126	BUG(); \
	127	} \
30f244ae	128	return; \
92c7b62f RB	129	} \
	130
	131	__define_perf_accessors(perfcntr, 0, 2)
	132	__define_perf_accessors(perfcntr, 1, 3)
795a2258 CD	133	__define_perf_accessors(perfcntr, 2, 0)
795a2258 CD	134	__define_perf_accessors(perfcntr, 3, 1)
92c7b62f RB	135
	136	__define_perf_accessors(perfctrl, 0, 2)
	137	__define_perf_accessors(perfctrl, 1, 3)
795a2258 CD	138	__define_perf_accessors(perfctrl, 2, 0)
795a2258 CD	139	__define_perf_accessors(perfctrl, 3, 1)
54176736	140
1acf1ca7	141	struct op_mips_model op_model_mipsxx_ops;
54176736 RB	142
	143	static struct mipsxx_register_config {
	144	unsigned int control[4];
	145	unsigned int counter[4];
	146	} reg;
	147
70342287	148	/* Compute all of the registers in preparation for enabling profiling. */
54176736 RB	149
	150	static void mipsxx_reg_setup(struct op_counter_config *ctr)
	151	{
1acf1ca7	152	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	153	int i;
	154
	155	/* Compute the performance counter control word. */
54176736 RB	156	for (i = 0; i < counters; i++) {
	157	reg.control[i] = 0;
	158	reg.counter[i] = 0;
	159
	160	if (!ctr[i].enabled)
	161	continue;
	162
	163	reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) \|
70342287	164	M_PERFCTL_INTERRUPT_ENABLE;
54176736 RB	165	if (ctr[i].kernel)
	166	reg.control[i] \|= M_PERFCTL_KERNEL;
	167	if (ctr[i].user)
	168	reg.control[i] \|= M_PERFCTL_USER;
	169	if (ctr[i].exl)
	170	reg.control[i] \|= M_PERFCTL_EXL;
cf5b2d23	171	if (boot_cpu_type() == CPU_XLR)
c783390a	172	reg.control[i] \|= M_PERFCTL_COUNT_ALL_THREADS;
54176736 RB	173	reg.counter[i] = 0x80000000 - ctr[i].count;
	174	}
	175	}
	176
70342287	177	/* Program all of the registers in preparation for enabling profiling. */
54176736	178
49a89efb	179	static void mipsxx_cpu_setup(void *args)
54176736	180	{
1acf1ca7	181	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736	182
c783390a MB	183	if (oprofile_skip_cpu(smp_processor_id()))
	184	return;
	185
54176736 RB	186	switch (counters) {
54176736 RB	187	case 4:
92c7b62f RB	188	w_c0_perfctrl3(0);
92c7b62f RB	189	w_c0_perfcntr3(reg.counter[3]);
54176736	190	case 3:
92c7b62f RB	191	w_c0_perfctrl2(0);
92c7b62f RB	192	w_c0_perfcntr2(reg.counter[2]);
54176736	193	case 2:
92c7b62f RB	194	w_c0_perfctrl1(0);
92c7b62f RB	195	w_c0_perfcntr1(reg.counter[1]);
54176736	196	case 1:
92c7b62f RB	197	w_c0_perfctrl0(0);
92c7b62f RB	198	w_c0_perfcntr0(reg.counter[0]);
54176736 RB	199	}
	200	}
	201
	202	/* Start all counters on current CPU */
	203	static void mipsxx_cpu_start(void *args)
	204	{
1acf1ca7	205	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736	206
c783390a MB	207	if (oprofile_skip_cpu(smp_processor_id()))
	208	return;
	209
54176736 RB	210	switch (counters) {
54176736 RB	211	case 4:
92c7b62f	212	w_c0_perfctrl3(WHAT \| reg.control[3]);
54176736	213	case 3:
92c7b62f	214	w_c0_perfctrl2(WHAT \| reg.control[2]);
54176736	215	case 2:
92c7b62f	216	w_c0_perfctrl1(WHAT \| reg.control[1]);
54176736	217	case 1:
92c7b62f	218	w_c0_perfctrl0(WHAT \| reg.control[0]);
54176736 RB	219	}
	220	}
	221
	222	/* Stop all counters on current CPU */
	223	static void mipsxx_cpu_stop(void *args)
	224	{
1acf1ca7	225	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736	226
c783390a MB	227	if (oprofile_skip_cpu(smp_processor_id()))
	228	return;
	229
54176736 RB	230	switch (counters) {
54176736 RB	231	case 4:
92c7b62f	232	w_c0_perfctrl3(0);
54176736	233	case 3:
92c7b62f	234	w_c0_perfctrl2(0);
54176736	235	case 2:
92c7b62f	236	w_c0_perfctrl1(0);
54176736	237	case 1:
92c7b62f	238	w_c0_perfctrl0(0);
54176736 RB	239	}
	240	}
	241
937a8015	242	static int mipsxx_perfcount_handler(void)
54176736	243	{
1acf1ca7	244	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	245	unsigned int control;
54176736 RB	246	unsigned int counter;
ffe9ee47 CD	247	int handled = IRQ_NONE;
	248
	249	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
	250	return handled;
54176736 RB	251
	252	switch (counters) {
	253	#define HANDLE_COUNTER(n) \
	254	case n + 1: \
92c7b62f RB	255	control = r_c0_perfctrl ## n(); \
92c7b62f RB	256	counter = r_c0_perfcntr ## n(); \
54176736 RB	257	if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
54176736 RB	258	(counter & M_COUNTER_OVERFLOW)) { \
937a8015	259	oprofile_add_sample(get_irq_regs(), n); \
92c7b62f	260	w_c0_perfcntr ## n(reg.counter[n]); \
ffe9ee47	261	handled = IRQ_HANDLED; \
54176736 RB	262	}
	263	HANDLE_COUNTER(3)
	264	HANDLE_COUNTER(2)
	265	HANDLE_COUNTER(1)
	266	HANDLE_COUNTER(0)
	267	}
ba339c03 RB	268
ba339c03 RB	269	return handled;
54176736 RB	270	}
	271
	272	#define M_CONFIG1_PC (1 << 4)
	273
92c7b62f	274	static inline int __n_counters(void)
54176736 RB	275	{
	276	if (!(read_c0_config1() & M_CONFIG1_PC))
	277	return 0;
39b8d525	278	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
54176736	279	return 1;
39b8d525	280	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
54176736	281	return 2;
39b8d525	282	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
54176736 RB	283	return 3;
	284
	285	return 4;
	286	}
	287
92c7b62f RB	288	static inline int n_counters(void)
92c7b62f RB	289	{
714cfe78 RB	290	int counters;
714cfe78 RB	291
10cc3529	292	switch (current_cpu_type()) {
714cfe78 RB	293	case CPU_R10000:
714cfe78 RB	294	counters = 2;
148171b2	295	break;
714cfe78 RB	296
	297	case CPU_R12000:
	298	case CPU_R14000:
	299	counters = 4;
148171b2	300	break;
714cfe78 RB	301
	302	default:
	303	counters = __n_counters();
	304	}
92c7b62f	305
92c7b62f RB	306	return counters;
	307	}
	308
39b8d525	309	static void reset_counters(void *arg)
54176736	310	{
005ca9a3	311	int counters = (int)(long)arg;
54176736 RB	312	switch (counters) {
54176736 RB	313	case 4:
92c7b62f RB	314	w_c0_perfctrl3(0);
92c7b62f RB	315	w_c0_perfcntr3(0);
54176736	316	case 3:
92c7b62f RB	317	w_c0_perfctrl2(0);
92c7b62f RB	318	w_c0_perfcntr2(0);
54176736	319	case 2:
92c7b62f RB	320	w_c0_perfctrl1(0);
92c7b62f RB	321	w_c0_perfcntr1(0);
54176736	322	case 1:
92c7b62f RB	323	w_c0_perfctrl0(0);
92c7b62f RB	324	w_c0_perfcntr0(0);
54176736 RB	325	}
	326	}
	327
3572a2c3 FF	328	static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
	329	{
	330	return mipsxx_perfcount_handler();
	331	}
	332
54176736 RB	333	static int __init mipsxx_init(void)
	334	{
	335	int counters;
	336
	337	counters = n_counters();
9efeae9a RB	338	if (counters == 0) {
9efeae9a RB	339	printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
54176736	340	return -ENODEV;
9efeae9a	341	}
54176736	342
39b8d525 RB	343	#ifdef CONFIG_MIPS_MT_SMP
	344	cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
	345	if (!cpu_has_mipsmt_pertccounters)
	346	counters = counters_total_to_per_cpu(counters);
	347	#endif
f6f88e9b	348	on_each_cpu(reset_counters, (void *)(long)counters, 1);
795a2258	349
1acf1ca7	350	op_model_mipsxx_ops.num_counters = counters;
10cc3529	351	switch (current_cpu_type()) {
113c62d9 SH	352	case CPU_M14KC:
	353	op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
	354	break;
	355
f8fa4811 SH	356	case CPU_M14KEC:
	357	op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
	358	break;
	359
2065988e	360	case CPU_20KC:
1acf1ca7	361	op_model_mipsxx_ops.cpu_type = "mips/20K";
2065988e RB	362	break;
2065988e RB	363
54176736	364	case CPU_24K:
1acf1ca7	365	op_model_mipsxx_ops.cpu_type = "mips/24K";
54176736 RB	366	break;
54176736 RB	367
2065988e	368	case CPU_25KF:
1acf1ca7	369	op_model_mipsxx_ops.cpu_type = "mips/25K";
2065988e RB	370	break;
2065988e RB	371
39b8d525	372	case CPU_1004K:
fcfd980c	373	case CPU_34K:
1acf1ca7	374	op_model_mipsxx_ops.cpu_type = "mips/34K";
fcfd980c	375	break;
c620953c	376
442e14a2	377	case CPU_1074K:
c620953c	378	case CPU_74K:
1acf1ca7	379	op_model_mipsxx_ops.cpu_type = "mips/74K";
c620953c	380	break;
fcfd980c	381
26ab96df LY	382	case CPU_INTERAPTIV:
	383	op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
	384	break;
	385
708ac4b8 LY	386	case CPU_PROAPTIV:
	387	op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
	388	break;
	389
8c7f6ba3 JH	390	case CPU_P5600:
	391	op_model_mipsxx_ops.cpu_type = "mips/P5600";
	392	break;
	393
f36c4720 LY	394	case CPU_M5150:
	395	op_model_mipsxx_ops.cpu_type = "mips/M5150";
	396	break;
	397
2065988e	398	case CPU_5KC:
1acf1ca7	399	op_model_mipsxx_ops.cpu_type = "mips/5K";
2065988e RB	400	break;
2065988e RB	401
714cfe78 RB	402	case CPU_R10000:
	403	if ((current_cpu_data.processor_id & 0xff) == 0x20)
	404	op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
	405	else
	406	op_model_mipsxx_ops.cpu_type = "mips/r10000";
	407	break;
	408
	409	case CPU_R12000:
	410	case CPU_R14000:
	411	op_model_mipsxx_ops.cpu_type = "mips/r12000";
	412	break;
	413
c03bc121 MM	414	case CPU_SB1:
c03bc121 MM	415	case CPU_SB1A:
1acf1ca7	416	op_model_mipsxx_ops.cpu_type = "mips/sb1";
c03bc121 MM	417	break;
c03bc121 MM	418
2fa36399 KC	419	case CPU_LOONGSON1:
	420	op_model_mipsxx_ops.cpu_type = "mips/loongson1";
	421	break;
	422
c783390a MB	423	case CPU_XLR:
	424	op_model_mipsxx_ops.cpu_type = "mips/xlr";
	425	break;
	426
54176736 RB	427	default:
	428	printk(KERN_ERR "Profiling unsupported for this CPU\n");
	429
	430	return -ENODEV;
	431	}
	432
46684734	433	save_perf_irq = perf_irq;
54176736 RB	434	perf_irq = mipsxx_perfcount_handler;
54176736 RB	435
a669efc4 AB	436	if (get_c0_perfcount_int)
	437	perfcount_irq = get_c0_perfcount_int();
	438	else if ((cp0_perfcount_irq >= 0) &&
	439	(cp0_compare_irq != cp0_perfcount_irq))
	440	perfcount_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
	441	else
	442	perfcount_irq = -1;
	443
	444	if (perfcount_irq >= 0)
	445	return request_irq(perfcount_irq, mipsxx_perfcount_int,
3572a2c3 FF	446	0, "Perfcounter", save_perf_irq);
3572a2c3 FF	447
54176736 RB	448	return 0;
	449	}
	450
	451	static void mipsxx_exit(void)
	452	{
795a2258	453	int counters = op_model_mipsxx_ops.num_counters;
5e2862eb	454
a669efc4 AB	455	if (perfcount_irq >= 0)
a669efc4 AB	456	free_irq(perfcount_irq, save_perf_irq);
3572a2c3	457
5e2862eb	458	counters = counters_per_cpu_to_total(counters);
f6f88e9b	459	on_each_cpu(reset_counters, (void *)(long)counters, 1);
54176736	460
46684734	461	perf_irq = save_perf_irq;
54176736 RB	462	}
54176736 RB	463
1acf1ca7	464	struct op_mips_model op_model_mipsxx_ops = {
54176736 RB	465	.reg_setup = mipsxx_reg_setup,
	466	.cpu_setup = mipsxx_cpu_setup,
	467	.init = mipsxx_init,
	468	.exit = mipsxx_exit,
	469	.cpu_start = mipsxx_cpu_start,
	470	.cpu_stop = mipsxx_cpu_stop,
	471	};