[linux-2.6-block.git] / arch / mips / oprofile / op_model_mipsxx.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2004, 05, 06 by Ralf Baechle
 * Copyright (C) 2005 by MIPS Technologies, Inc.
 */
#include <linux/cpumask.h>
#include <linux/oprofile.h>
#include <linux/interrupt.h>
#include <linux/smp.h>
#include <asm/irq_regs.h>

#include "op_impl.h"

#define M_PERFCTL_EXL			(1UL	  <<  0)
#define M_PERFCTL_KERNEL		(1UL	  <<  1)
#define M_PERFCTL_SUPERVISOR		(1UL	  <<  2)
#define M_PERFCTL_USER			(1UL	  <<  3)
#define M_PERFCTL_INTERRUPT_ENABLE	(1UL	  <<  4)
#define M_PERFCTL_EVENT(event)		(((event) & 0x3ff)  << 5)
#define M_PERFCTL_VPEID(vpe)		((vpe)	  << 16)
#define M_PERFCTL_MT_EN(filter)		((filter) << 20)
#define	   M_TC_EN_ALL			M_PERFCTL_MT_EN(0)
#define	   M_TC_EN_VPE			M_PERFCTL_MT_EN(1)
#define	   M_TC_EN_TC			M_PERFCTL_MT_EN(2)
#define M_PERFCTL_TCID(tcid)		((tcid)	  << 22)
#define M_PERFCTL_WIDE			(1UL	  << 30)
#define M_PERFCTL_MORE			(1UL	  << 31)

#define M_COUNTER_OVERFLOW		(1UL	  << 31)

/* Netlogic XLR specific, count events in all threads in a core */
#define M_PERFCTL_COUNT_ALL_THREADS	(1UL	  << 13)

static int (*save_perf_irq)(void);

/*
 * XLR has only one set of counters per core. Designate the
 * first hardware thread in the core for setup and init.
 * Skip CPUs with non-zero hardware thread id (4 hwt per core)
 */
#if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
#define oprofile_skip_cpu(c)	((cpu_logical_map(c) & 0x3) != 0)
#else
#define oprofile_skip_cpu(c)	0
#endif

#ifdef CONFIG_MIPS_MT_SMP
static int cpu_has_mipsmt_pertccounters;
#define WHAT		(M_TC_EN_VPE | \
			 M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
#define vpe_id()	(cpu_has_mipsmt_pertccounters ? \
			0 : cpu_data[smp_processor_id()].vpe_id)

/*
 * The number of bits to shift to convert between counters per core and
 * counters per VPE.  There is no reasonable interface atm to obtain the
 * number of VPEs used by Linux and in the 34K this number is fixed to two
 * anyways so we hardcore a few things here for the moment.  The way it's
 * done here will ensure that oprofile VSMP kernel will run right on a lesser
 * core like a 24K also or with maxcpus=1.
 */
static inline unsigned int vpe_shift(void)
{
	if (num_possible_cpus() > 1)
		return 1;

	return 0;
}

#else

#define WHAT		0
#define vpe_id()	0

static inline unsigned int vpe_shift(void)
{
	return 0;
}

#endif

static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
{
	return counters >> vpe_shift();
}

static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
{
	return counters << vpe_shift();
}

#define __define_perf_accessors(r, n, np)				\
									\
static inline unsigned int r_c0_ ## r ## n(void)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		return read_c0_ ## r ## n();				\
	case 1:								\
		return read_c0_ ## r ## np();				\
	default:							\
		BUG();							\
	}								\
	return 0;							\
}									\
									\
static inline void w_c0_ ## r ## n(unsigned int value)			\
{									\
	unsigned int cpu = vpe_id();					\
									\
	switch (cpu) {							\
	case 0:								\
		write_c0_ ## r ## n(value);				\
		return;							\
	case 1:								\
		write_c0_ ## r ## np(value);				\
		return;							\
	default:							\
		BUG();							\
	}								\
	return;								\
}									\

__define_perf_accessors(perfcntr, 0, 2)
__define_perf_accessors(perfcntr, 1, 3)
__define_perf_accessors(perfcntr, 2, 0)
__define_perf_accessors(perfcntr, 3, 1)

__define_perf_accessors(perfctrl, 0, 2)
__define_perf_accessors(perfctrl, 1, 3)
__define_perf_accessors(perfctrl, 2, 0)
__define_perf_accessors(perfctrl, 3, 1)

struct op_mips_model op_model_mipsxx_ops;

static struct mipsxx_register_config {
	unsigned int control[4];
	unsigned int counter[4];
} reg;

/* Compute all of the registers in preparation for enabling profiling.	*/

static void mipsxx_reg_setup(struct op_counter_config *ctr)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	int i;

	/* Compute the performance counter control word.  */
	for (i = 0; i < counters; i++) {
		reg.control[i] = 0;
		reg.counter[i] = 0;

		if (!ctr[i].enabled)
			continue;

		reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
				 M_PERFCTL_INTERRUPT_ENABLE;
		if (ctr[i].kernel)
			reg.control[i] |= M_PERFCTL_KERNEL;
		if (ctr[i].user)
			reg.control[i] |= M_PERFCTL_USER;
		if (ctr[i].exl)
			reg.control[i] |= M_PERFCTL_EXL;
		if (boot_cpu_type() == CPU_XLR)
			reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS;
		reg.counter[i] = 0x80000000 - ctr[i].count;
	}
}

/* Program all of the registers in preparation for enabling profiling.	*/

static void mipsxx_cpu_setup(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	if (oprofile_skip_cpu(smp_processor_id()))
		return;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(reg.counter[3]);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(reg.counter[2]);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(reg.counter[1]);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(reg.counter[0]);
	}
}

/* Start all counters on current CPU */
static void mipsxx_cpu_start(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	if (oprofile_skip_cpu(smp_processor_id()))
		return;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(WHAT | reg.control[3]);
	case 3:
		w_c0_perfctrl2(WHAT | reg.control[2]);
	case 2:
		w_c0_perfctrl1(WHAT | reg.control[1]);
	case 1:
		w_c0_perfctrl0(WHAT | reg.control[0]);
	}
}

/* Stop all counters on current CPU */
static void mipsxx_cpu_stop(void *args)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;

	if (oprofile_skip_cpu(smp_processor_id()))
		return;

	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
	case 3:
		w_c0_perfctrl2(0);
	case 2:
		w_c0_perfctrl1(0);
	case 1:
		w_c0_perfctrl0(0);
	}
}

static int mipsxx_perfcount_handler(void)
{
	unsigned int counters = op_model_mipsxx_ops.num_counters;
	unsigned int control;
	unsigned int counter;
	int handled = IRQ_NONE;

	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
		return handled;

	switch (counters) {
#define HANDLE_COUNTER(n)						\
	case n + 1:							\
		control = r_c0_perfctrl ## n();				\
		counter = r_c0_perfcntr ## n();				\
		if ((control & M_PERFCTL_INTERRUPT_ENABLE) &&		\
		    (counter & M_COUNTER_OVERFLOW)) {			\
			oprofile_add_sample(get_irq_regs(), n);		\
			w_c0_perfcntr ## n(reg.counter[n]);		\
			handled = IRQ_HANDLED;				\
		}
	HANDLE_COUNTER(3)
	HANDLE_COUNTER(2)
	HANDLE_COUNTER(1)
	HANDLE_COUNTER(0)
	}

	return handled;
}

#define M_CONFIG1_PC	(1 << 4)

static inline int __n_counters(void)
{
	if (!(read_c0_config1() & M_CONFIG1_PC))
		return 0;
	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
		return 1;
	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
		return 2;
	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
		return 3;

	return 4;
}

static inline int n_counters(void)
{
	int counters;

	switch (current_cpu_type()) {
	case CPU_R10000:
		counters = 2;
		break;

	case CPU_R12000:
	case CPU_R14000:
		counters = 4;
		break;

	default:
		counters = __n_counters();
	}

	return counters;
}

static void reset_counters(void *arg)
{
	int counters = (int)(long)arg;
	switch (counters) {
	case 4:
		w_c0_perfctrl3(0);
		w_c0_perfcntr3(0);
	case 3:
		w_c0_perfctrl2(0);
		w_c0_perfcntr2(0);
	case 2:
		w_c0_perfctrl1(0);
		w_c0_perfcntr1(0);
	case 1:
		w_c0_perfctrl0(0);
		w_c0_perfcntr0(0);
	}
}

static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
{
	return mipsxx_perfcount_handler();
}

static int __init mipsxx_init(void)
{
	int counters;

	counters = n_counters();
	if (counters == 0) {
		printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
		return -ENODEV;
	}

#ifdef CONFIG_MIPS_MT_SMP
	cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
	if (!cpu_has_mipsmt_pertccounters)
		counters = counters_total_to_per_cpu(counters);
#endif
	on_each_cpu(reset_counters, (void *)(long)counters, 1);

	op_model_mipsxx_ops.num_counters = counters;
	switch (current_cpu_type()) {
	case CPU_M14KC:
		op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
		break;

	case CPU_M14KEC:
		op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
		break;

	case CPU_20KC:
		op_model_mipsxx_ops.cpu_type = "mips/20K";
		break;

	case CPU_24K:
		op_model_mipsxx_ops.cpu_type = "mips/24K";
		break;

	case CPU_25KF:
		op_model_mipsxx_ops.cpu_type = "mips/25K";
		break;

	case CPU_1004K:
	case CPU_34K:
		op_model_mipsxx_ops.cpu_type = "mips/34K";
		break;

	case CPU_1074K:
	case CPU_74K:
		op_model_mipsxx_ops.cpu_type = "mips/74K";
		break;

	case CPU_INTERAPTIV:
		op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
		break;

	case CPU_PROAPTIV:
		op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
		break;

	case CPU_P5600:
		op_model_mipsxx_ops.cpu_type = "mips/P5600";
		break;

	case CPU_5KC:
		op_model_mipsxx_ops.cpu_type = "mips/5K";
		break;

	case CPU_R10000:
		if ((current_cpu_data.processor_id & 0xff) == 0x20)
			op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
		else
			op_model_mipsxx_ops.cpu_type = "mips/r10000";
		break;

	case CPU_R12000:
	case CPU_R14000:
		op_model_mipsxx_ops.cpu_type = "mips/r12000";
		break;

	case CPU_SB1:
	case CPU_SB1A:
		op_model_mipsxx_ops.cpu_type = "mips/sb1";
		break;

	case CPU_LOONGSON1:
		op_model_mipsxx_ops.cpu_type = "mips/loongson1";
		break;

	case CPU_XLR:
		op_model_mipsxx_ops.cpu_type = "mips/xlr";
		break;

	default:
		printk(KERN_ERR "Profiling unsupported for this CPU\n");

		return -ENODEV;
	}

	save_perf_irq = perf_irq;
	perf_irq = mipsxx_perfcount_handler;

	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
		return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
			0, "Perfcounter", save_perf_irq);

	return 0;
}

static void mipsxx_exit(void)
{
	int counters = op_model_mipsxx_ops.num_counters;

	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
		free_irq(cp0_perfcount_irq, save_perf_irq);

	counters = counters_per_cpu_to_total(counters);
	on_each_cpu(reset_counters, (void *)(long)counters, 1);

	perf_irq = save_perf_irq;
}

struct op_mips_model op_model_mipsxx_ops = {
	.reg_setup	= mipsxx_reg_setup,
	.cpu_setup	= mipsxx_cpu_setup,
	.init		= mipsxx_init,
	.exit		= mipsxx_exit,
	.cpu_start	= mipsxx_cpu_start,
	.cpu_stop	= mipsxx_cpu_stop,
};
Commit	Line	Data
54176736 RB	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
937a8015	6	* Copyright (C) 2004, 05, 06 by Ralf Baechle
54176736 RB	7	* Copyright (C) 2005 by MIPS Technologies, Inc.
54176736 RB	8	*/
5e2862eb	9	#include <linux/cpumask.h>
54176736 RB	10	#include <linux/oprofile.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/smp.h>
937a8015	13	#include <asm/irq_regs.h>
54176736 RB	14
	15	#include "op_impl.h"
	16
70342287 RB	17	#define M_PERFCTL_EXL (1UL << 0)
	18	#define M_PERFCTL_KERNEL (1UL << 1)
	19	#define M_PERFCTL_SUPERVISOR (1UL << 2)
	20	#define M_PERFCTL_USER (1UL << 3)
	21	#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4)
39a51109	22	#define M_PERFCTL_EVENT(event) (((event) & 0x3ff) << 5)
70342287	23	#define M_PERFCTL_VPEID(vpe) ((vpe) << 16)
92c7b62f	24	#define M_PERFCTL_MT_EN(filter) ((filter) << 20)
70342287 RB	25	#define M_TC_EN_ALL M_PERFCTL_MT_EN(0)
	26	#define M_TC_EN_VPE M_PERFCTL_MT_EN(1)
	27	#define M_TC_EN_TC M_PERFCTL_MT_EN(2)
	28	#define M_PERFCTL_TCID(tcid) ((tcid) << 22)
	29	#define M_PERFCTL_WIDE (1UL << 30)
	30	#define M_PERFCTL_MORE (1UL << 31)
92c7b62f	31
70342287	32	#define M_COUNTER_OVERFLOW (1UL << 31)
92c7b62f	33
c783390a	34	/* Netlogic XLR specific, count events in all threads in a core */
70342287	35	#define M_PERFCTL_COUNT_ALL_THREADS (1UL << 13)
c783390a	36
46684734 DV	37	static int (*save_perf_irq)(void);
46684734 DV	38
c783390a MB	39	/*
	40	* XLR has only one set of counters per core. Designate the
	41	* first hardware thread in the core for setup and init.
	42	* Skip CPUs with non-zero hardware thread id (4 hwt per core)
	43	*/
83a18415	44	#if defined(CONFIG_CPU_XLR) && defined(CONFIG_SMP)
c783390a MB	45	#define oprofile_skip_cpu(c) ((cpu_logical_map(c) & 0x3) != 0)
	46	#else
	47	#define oprofile_skip_cpu(c) 0
	48	#endif
	49
92c7b62f	50	#ifdef CONFIG_MIPS_MT_SMP
39b8d525 RB	51	static int cpu_has_mipsmt_pertccounters;
	52	#define WHAT (M_TC_EN_VPE \| \
	53	M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
	54	#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
	55	0 : cpu_data[smp_processor_id()].vpe_id)
5e2862eb RB	56
	57	/*
	58	* The number of bits to shift to convert between counters per core and
	59	* counters per VPE. There is no reasonable interface atm to obtain the
	60	* number of VPEs used by Linux and in the 34K this number is fixed to two
	61	* anyways so we hardcore a few things here for the moment. The way it's
	62	* done here will ensure that oprofile VSMP kernel will run right on a lesser
	63	* core like a 24K also or with maxcpus=1.
	64	*/
	65	static inline unsigned int vpe_shift(void)
	66	{
	67	if (num_possible_cpus() > 1)
	68	return 1;
	69
	70	return 0;
	71	}
	72
92c7b62f	73	#else
5e2862eb	74
be609f35	75	#define WHAT 0
6f4c5bde	76	#define vpe_id() 0
5e2862eb RB	77
	78	static inline unsigned int vpe_shift(void)
	79	{
	80	return 0;
	81	}
	82
92c7b62f	83	#endif
54176736	84
5e2862eb RB	85	static inline unsigned int counters_total_to_per_cpu(unsigned int counters)
	86	{
	87	return counters >> vpe_shift();
	88	}
	89
	90	static inline unsigned int counters_per_cpu_to_total(unsigned int counters)
	91	{
	92	return counters << vpe_shift();
	93	}
	94
92c7b62f RB	95	#define __define_perf_accessors(r, n, np) \
	96	\
	97	static inline unsigned int r_c0_ ## r ## n(void) \
	98	{ \
be609f35	99	unsigned int cpu = vpe_id(); \
92c7b62f RB	100	\
	101	switch (cpu) { \
	102	case 0: \
	103	return read_c0_ ## r ## n(); \
	104	case 1: \
	105	return read_c0_ ## r ## np(); \
	106	default: \
	107	BUG(); \
	108	} \
30f244ae	109	return 0; \
92c7b62f RB	110	} \
	111	\
	112	static inline void w_c0_ ## r ## n(unsigned int value) \
	113	{ \
be609f35	114	unsigned int cpu = vpe_id(); \
92c7b62f RB	115	\
	116	switch (cpu) { \
	117	case 0: \
	118	write_c0_ ## r ## n(value); \
	119	return; \
	120	case 1: \
	121	write_c0_ ## r ## np(value); \
	122	return; \
	123	default: \
	124	BUG(); \
	125	} \
30f244ae	126	return; \
92c7b62f RB	127	} \
	128
	129	__define_perf_accessors(perfcntr, 0, 2)
	130	__define_perf_accessors(perfcntr, 1, 3)
795a2258 CD	131	__define_perf_accessors(perfcntr, 2, 0)
795a2258 CD	132	__define_perf_accessors(perfcntr, 3, 1)
92c7b62f RB	133
	134	__define_perf_accessors(perfctrl, 0, 2)
	135	__define_perf_accessors(perfctrl, 1, 3)
795a2258 CD	136	__define_perf_accessors(perfctrl, 2, 0)
795a2258 CD	137	__define_perf_accessors(perfctrl, 3, 1)
54176736	138
1acf1ca7	139	struct op_mips_model op_model_mipsxx_ops;
54176736 RB	140
	141	static struct mipsxx_register_config {
	142	unsigned int control[4];
	143	unsigned int counter[4];
	144	} reg;
	145
70342287	146	/* Compute all of the registers in preparation for enabling profiling. */
54176736 RB	147
	148	static void mipsxx_reg_setup(struct op_counter_config *ctr)
	149	{
1acf1ca7	150	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	151	int i;
	152
	153	/* Compute the performance counter control word. */
54176736 RB	154	for (i = 0; i < counters; i++) {
	155	reg.control[i] = 0;
	156	reg.counter[i] = 0;
	157
	158	if (!ctr[i].enabled)
	159	continue;
	160
	161	reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) \|
70342287	162	M_PERFCTL_INTERRUPT_ENABLE;
54176736 RB	163	if (ctr[i].kernel)
	164	reg.control[i] \|= M_PERFCTL_KERNEL;
	165	if (ctr[i].user)
	166	reg.control[i] \|= M_PERFCTL_USER;
	167	if (ctr[i].exl)
	168	reg.control[i] \|= M_PERFCTL_EXL;
cf5b2d23	169	if (boot_cpu_type() == CPU_XLR)
c783390a	170	reg.control[i] \|= M_PERFCTL_COUNT_ALL_THREADS;
54176736 RB	171	reg.counter[i] = 0x80000000 - ctr[i].count;
	172	}
	173	}
	174
70342287	175	/* Program all of the registers in preparation for enabling profiling. */
54176736	176
49a89efb	177	static void mipsxx_cpu_setup(void *args)
54176736	178	{
1acf1ca7	179	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736	180
c783390a MB	181	if (oprofile_skip_cpu(smp_processor_id()))
	182	return;
	183
54176736 RB	184	switch (counters) {
54176736 RB	185	case 4:
92c7b62f RB	186	w_c0_perfctrl3(0);
92c7b62f RB	187	w_c0_perfcntr3(reg.counter[3]);
54176736	188	case 3:
92c7b62f RB	189	w_c0_perfctrl2(0);
92c7b62f RB	190	w_c0_perfcntr2(reg.counter[2]);
54176736	191	case 2:
92c7b62f RB	192	w_c0_perfctrl1(0);
92c7b62f RB	193	w_c0_perfcntr1(reg.counter[1]);
54176736	194	case 1:
92c7b62f RB	195	w_c0_perfctrl0(0);
92c7b62f RB	196	w_c0_perfcntr0(reg.counter[0]);
54176736 RB	197	}
	198	}
	199
	200	/* Start all counters on current CPU */
	201	static void mipsxx_cpu_start(void *args)
	202	{
1acf1ca7	203	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736	204
c783390a MB	205	if (oprofile_skip_cpu(smp_processor_id()))
	206	return;
	207
54176736 RB	208	switch (counters) {
54176736 RB	209	case 4:
92c7b62f	210	w_c0_perfctrl3(WHAT \| reg.control[3]);
54176736	211	case 3:
92c7b62f	212	w_c0_perfctrl2(WHAT \| reg.control[2]);
54176736	213	case 2:
92c7b62f	214	w_c0_perfctrl1(WHAT \| reg.control[1]);
54176736	215	case 1:
92c7b62f	216	w_c0_perfctrl0(WHAT \| reg.control[0]);
54176736 RB	217	}
	218	}
	219
	220	/* Stop all counters on current CPU */
	221	static void mipsxx_cpu_stop(void *args)
	222	{
1acf1ca7	223	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736	224
c783390a MB	225	if (oprofile_skip_cpu(smp_processor_id()))
	226	return;
	227
54176736 RB	228	switch (counters) {
54176736 RB	229	case 4:
92c7b62f	230	w_c0_perfctrl3(0);
54176736	231	case 3:
92c7b62f	232	w_c0_perfctrl2(0);
54176736	233	case 2:
92c7b62f	234	w_c0_perfctrl1(0);
54176736	235	case 1:
92c7b62f	236	w_c0_perfctrl0(0);
54176736 RB	237	}
	238	}
	239
937a8015	240	static int mipsxx_perfcount_handler(void)
54176736	241	{
1acf1ca7	242	unsigned int counters = op_model_mipsxx_ops.num_counters;
54176736 RB	243	unsigned int control;
54176736 RB	244	unsigned int counter;
ffe9ee47 CD	245	int handled = IRQ_NONE;
	246
	247	if (cpu_has_mips_r2 && !(read_c0_cause() & (1 << 26)))
	248	return handled;
54176736 RB	249
	250	switch (counters) {
	251	#define HANDLE_COUNTER(n) \
	252	case n + 1: \
92c7b62f RB	253	control = r_c0_perfctrl ## n(); \
92c7b62f RB	254	counter = r_c0_perfcntr ## n(); \
54176736 RB	255	if ((control & M_PERFCTL_INTERRUPT_ENABLE) && \
54176736 RB	256	(counter & M_COUNTER_OVERFLOW)) { \
937a8015	257	oprofile_add_sample(get_irq_regs(), n); \
92c7b62f	258	w_c0_perfcntr ## n(reg.counter[n]); \
ffe9ee47	259	handled = IRQ_HANDLED; \
54176736 RB	260	}
	261	HANDLE_COUNTER(3)
	262	HANDLE_COUNTER(2)
	263	HANDLE_COUNTER(1)
	264	HANDLE_COUNTER(0)
	265	}
ba339c03 RB	266
ba339c03 RB	267	return handled;
54176736 RB	268	}
	269
	270	#define M_CONFIG1_PC (1 << 4)
	271
92c7b62f	272	static inline int __n_counters(void)
54176736 RB	273	{
	274	if (!(read_c0_config1() & M_CONFIG1_PC))
	275	return 0;
39b8d525	276	if (!(read_c0_perfctrl0() & M_PERFCTL_MORE))
54176736	277	return 1;
39b8d525	278	if (!(read_c0_perfctrl1() & M_PERFCTL_MORE))
54176736	279	return 2;
39b8d525	280	if (!(read_c0_perfctrl2() & M_PERFCTL_MORE))
54176736 RB	281	return 3;
	282
	283	return 4;
	284	}
	285
92c7b62f RB	286	static inline int n_counters(void)
92c7b62f RB	287	{
714cfe78 RB	288	int counters;
714cfe78 RB	289
10cc3529	290	switch (current_cpu_type()) {
714cfe78 RB	291	case CPU_R10000:
714cfe78 RB	292	counters = 2;
148171b2	293	break;
714cfe78 RB	294
	295	case CPU_R12000:
	296	case CPU_R14000:
	297	counters = 4;
148171b2	298	break;
714cfe78 RB	299
	300	default:
	301	counters = __n_counters();
	302	}
92c7b62f	303
92c7b62f RB	304	return counters;
	305	}
	306
39b8d525	307	static void reset_counters(void *arg)
54176736	308	{
005ca9a3	309	int counters = (int)(long)arg;
54176736 RB	310	switch (counters) {
54176736 RB	311	case 4:
92c7b62f RB	312	w_c0_perfctrl3(0);
92c7b62f RB	313	w_c0_perfcntr3(0);
54176736	314	case 3:
92c7b62f RB	315	w_c0_perfctrl2(0);
92c7b62f RB	316	w_c0_perfcntr2(0);
54176736	317	case 2:
92c7b62f RB	318	w_c0_perfctrl1(0);
92c7b62f RB	319	w_c0_perfcntr1(0);
54176736	320	case 1:
92c7b62f RB	321	w_c0_perfctrl0(0);
92c7b62f RB	322	w_c0_perfcntr0(0);
54176736 RB	323	}
	324	}
	325
3572a2c3 FF	326	static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
	327	{
	328	return mipsxx_perfcount_handler();
	329	}
	330
54176736 RB	331	static int __init mipsxx_init(void)
	332	{
	333	int counters;
	334
	335	counters = n_counters();
9efeae9a RB	336	if (counters == 0) {
9efeae9a RB	337	printk(KERN_ERR "Oprofile: CPU has no performance counters\n");
54176736	338	return -ENODEV;
9efeae9a	339	}
54176736	340
39b8d525 RB	341	#ifdef CONFIG_MIPS_MT_SMP
	342	cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
	343	if (!cpu_has_mipsmt_pertccounters)
	344	counters = counters_total_to_per_cpu(counters);
	345	#endif
f6f88e9b	346	on_each_cpu(reset_counters, (void *)(long)counters, 1);
795a2258	347
1acf1ca7	348	op_model_mipsxx_ops.num_counters = counters;
10cc3529	349	switch (current_cpu_type()) {
113c62d9 SH	350	case CPU_M14KC:
	351	op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
	352	break;
	353
f8fa4811 SH	354	case CPU_M14KEC:
	355	op_model_mipsxx_ops.cpu_type = "mips/M14KEc";
	356	break;
	357
2065988e	358	case CPU_20KC:
1acf1ca7	359	op_model_mipsxx_ops.cpu_type = "mips/20K";
2065988e RB	360	break;
2065988e RB	361
54176736	362	case CPU_24K:
1acf1ca7	363	op_model_mipsxx_ops.cpu_type = "mips/24K";
54176736 RB	364	break;
54176736 RB	365
2065988e	366	case CPU_25KF:
1acf1ca7	367	op_model_mipsxx_ops.cpu_type = "mips/25K";
2065988e RB	368	break;
2065988e RB	369
39b8d525	370	case CPU_1004K:
fcfd980c	371	case CPU_34K:
1acf1ca7	372	op_model_mipsxx_ops.cpu_type = "mips/34K";
fcfd980c	373	break;
c620953c	374
442e14a2	375	case CPU_1074K:
c620953c	376	case CPU_74K:
1acf1ca7	377	op_model_mipsxx_ops.cpu_type = "mips/74K";
c620953c	378	break;
fcfd980c	379
26ab96df LY	380	case CPU_INTERAPTIV:
	381	op_model_mipsxx_ops.cpu_type = "mips/interAptiv";
	382	break;
	383
708ac4b8 LY	384	case CPU_PROAPTIV:
	385	op_model_mipsxx_ops.cpu_type = "mips/proAptiv";
	386	break;
	387
8c7f6ba3 JH	388	case CPU_P5600:
	389	op_model_mipsxx_ops.cpu_type = "mips/P5600";
	390	break;
	391
2065988e	392	case CPU_5KC:
1acf1ca7	393	op_model_mipsxx_ops.cpu_type = "mips/5K";
2065988e RB	394	break;
2065988e RB	395
714cfe78 RB	396	case CPU_R10000:
	397	if ((current_cpu_data.processor_id & 0xff) == 0x20)
	398	op_model_mipsxx_ops.cpu_type = "mips/r10000-v2.x";
	399	else
	400	op_model_mipsxx_ops.cpu_type = "mips/r10000";
	401	break;
	402
	403	case CPU_R12000:
	404	case CPU_R14000:
	405	op_model_mipsxx_ops.cpu_type = "mips/r12000";
	406	break;
	407
c03bc121 MM	408	case CPU_SB1:
c03bc121 MM	409	case CPU_SB1A:
1acf1ca7	410	op_model_mipsxx_ops.cpu_type = "mips/sb1";
c03bc121 MM	411	break;
c03bc121 MM	412
2fa36399 KC	413	case CPU_LOONGSON1:
	414	op_model_mipsxx_ops.cpu_type = "mips/loongson1";
	415	break;
	416
c783390a MB	417	case CPU_XLR:
	418	op_model_mipsxx_ops.cpu_type = "mips/xlr";
	419	break;
	420
54176736 RB	421	default:
	422	printk(KERN_ERR "Profiling unsupported for this CPU\n");
	423
	424	return -ENODEV;
	425	}
	426
46684734	427	save_perf_irq = perf_irq;
54176736 RB	428	perf_irq = mipsxx_perfcount_handler;
54176736 RB	429
3572a2c3 FF	430	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
	431	return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
	432	0, "Perfcounter", save_perf_irq);
	433
54176736 RB	434	return 0;
	435	}
	436
	437	static void mipsxx_exit(void)
	438	{
795a2258	439	int counters = op_model_mipsxx_ops.num_counters;
5e2862eb	440
3572a2c3 FF	441	if ((cp0_perfcount_irq >= 0) && (cp0_compare_irq != cp0_perfcount_irq))
	442	free_irq(cp0_perfcount_irq, save_perf_irq);
	443
5e2862eb	444	counters = counters_per_cpu_to_total(counters);
f6f88e9b	445	on_each_cpu(reset_counters, (void *)(long)counters, 1);
54176736	446
46684734	447	perf_irq = save_perf_irq;
54176736 RB	448	}
54176736 RB	449
1acf1ca7	450	struct op_mips_model op_model_mipsxx_ops = {
54176736 RB	451	.reg_setup = mipsxx_reg_setup,
	452	.cpu_setup = mipsxx_cpu_setup,
	453	.init = mipsxx_init,
	454	.exit = mipsxx_exit,
	455	.cpu_start = mipsxx_cpu_start,
	456	.cpu_stop = mipsxx_cpu_stop,
	457	};