[linux-block.git] / arch / mips / netlogic / xlp / usb-init.c

/*
 * Copyright (c) 2003-2012 Broadcom Corporation
 * All Rights Reserved
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the Broadcom
 * license below:
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/dma-mapping.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/platform_device.h>

#include <asm/netlogic/haldefs.h>
#include <asm/netlogic/xlp-hal/iomap.h>
#include <asm/netlogic/xlp-hal/xlp.h>

/*
 * USB glue logic registers, used only during initialization
 */
#define USB_CTL_0			0x01
#define USB_PHY_0			0x0A
#define USB_PHY_RESET			0x01
#define USB_PHY_PORT_RESET_0		0x10
#define USB_PHY_PORT_RESET_1		0x20
#define USB_CONTROLLER_RESET		0x01
#define USB_INT_STATUS			0x0E
#define USB_INT_EN			0x0F
#define USB_PHY_INTERRUPT_EN		0x01
#define USB_OHCI_INTERRUPT_EN		0x02
#define USB_OHCI_INTERRUPT1_EN		0x04
#define USB_OHCI_INTERRUPT2_EN		0x08
#define USB_CTRL_INTERRUPT_EN		0x10

#define nlm_read_usb_reg(b, r)			nlm_read_reg(b, r)
#define nlm_write_usb_reg(b, r, v)		nlm_write_reg(b, r, v)
#define nlm_get_usb_pcibase(node, inst)		\
	nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
#define nlm_get_usb_regbase(node, inst)		\
	(nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)

static void nlm_usb_intr_en(int node, int port)
{
	uint32_t val;
	uint64_t port_addr;

	port_addr = nlm_get_usb_regbase(node, port);
	val = nlm_read_usb_reg(port_addr, USB_INT_EN);
	val = USB_CTRL_INTERRUPT_EN  | USB_OHCI_INTERRUPT_EN |
		USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN	|
		USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
	nlm_write_usb_reg(port_addr, USB_INT_EN, val);
}

static void nlm_usb_hw_reset(int node, int port)
{
	uint64_t port_addr;
	uint32_t val;

	/* reset USB phy */
	port_addr = nlm_get_usb_regbase(node, port);
	val = nlm_read_usb_reg(port_addr, USB_PHY_0);
	val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1);
	nlm_write_usb_reg(port_addr, USB_PHY_0, val);

	mdelay(100);
	val = nlm_read_usb_reg(port_addr, USB_CTL_0);
	val &= ~(USB_CONTROLLER_RESET);
	val |= 0x4;
	nlm_write_usb_reg(port_addr, USB_CTL_0, val);
}

static int __init nlm_platform_usb_init(void)
{
	pr_info("Initializing USB Interface\n");
	nlm_usb_hw_reset(0, 0);
	nlm_usb_hw_reset(0, 3);

	/* Enable PHY interrupts */
	nlm_usb_intr_en(0, 0);
	nlm_usb_intr_en(0, 3);

	return 0;
}

arch_initcall(nlm_platform_usb_init);

static u64 xlp_usb_dmamask = ~(u32)0;

/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */
static void nlm_usb_fixup_final(struct pci_dev *dev)
{
	dev->dev.dma_mask		= &xlp_usb_dmamask;
	dev->dev.coherent_dma_mask	= DMA_BIT_MASK(32);
	switch (dev->devfn) {
	case 0x10:
		dev->irq = PIC_EHCI_0_IRQ;
		break;
	case 0x11:
		dev->irq = PIC_OHCI_0_IRQ;
		break;
	case 0x12:
		dev->irq = PIC_OHCI_1_IRQ;
		break;
	case 0x13:
		dev->irq = PIC_EHCI_1_IRQ;
		break;
	case 0x14:
		dev->irq = PIC_OHCI_2_IRQ;
		break;
	case 0x15:
		dev->irq = PIC_OHCI_3_IRQ;
		break;
	}
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI,
		nlm_usb_fixup_final);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI,
		nlm_usb_fixup_final);
Commit	Line	Data
1004165f GR	1	/*
	2	* Copyright (c) 2003-2012 Broadcom Corporation
	3	* All Rights Reserved
	4	*
	5	* This software is available to you under a choice of one of two
	6	* licenses. You may choose to be licensed under the terms of the GNU
	7	* General Public License (GPL) Version 2, available from the file
	8	* COPYING in the main directory of this source tree, or the Broadcom
	9	* license below:
	10	*
	11	* Redistribution and use in source and binary forms, with or without
	12	* modification, are permitted provided that the following conditions
	13	* are met:
	14	*
	15	* 1. Redistributions of source code must retain the above copyright
	16	* notice, this list of conditions and the following disclaimer.
	17	* 2. Redistributions in binary form must reproduce the above copyright
	18	* notice, this list of conditions and the following disclaimer in
	19	* the documentation and/or other materials provided with the
	20	* distribution.
	21	*
	22	* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
	23	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	24	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	25	* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
	27	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	28	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
	29	* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
	30	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
	31	* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
	32	* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	33	*/
	34
	35	#include <linux/dma-mapping.h>
	36	#include <linux/kernel.h>
	37	#include <linux/delay.h>
	38	#include <linux/init.h>
	39	#include <linux/pci.h>
	40	#include <linux/platform_device.h>
	41
	42	#include <asm/netlogic/haldefs.h>
	43	#include <asm/netlogic/xlp-hal/iomap.h>
	44	#include <asm/netlogic/xlp-hal/xlp.h>
c80dd3b6 J	45
	46	/*
	47	* USB glue logic registers, used only during initialization
	48	*/
	49	#define USB_CTL_0 0x01
	50	#define USB_PHY_0 0x0A
	51	#define USB_PHY_RESET 0x01
	52	#define USB_PHY_PORT_RESET_0 0x10
	53	#define USB_PHY_PORT_RESET_1 0x20
	54	#define USB_CONTROLLER_RESET 0x01
	55	#define USB_INT_STATUS 0x0E
	56	#define USB_INT_EN 0x0F
	57	#define USB_PHY_INTERRUPT_EN 0x01
	58	#define USB_OHCI_INTERRUPT_EN 0x02
	59	#define USB_OHCI_INTERRUPT1_EN 0x04
	60	#define USB_OHCI_INTERRUPT2_EN 0x08
	61	#define USB_CTRL_INTERRUPT_EN 0x10
	62
	63	#define nlm_read_usb_reg(b, r) nlm_read_reg(b, r)
	64	#define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v)
	65	#define nlm_get_usb_pcibase(node, inst) \
	66	nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
	67	#define nlm_get_usb_regbase(node, inst) \
	68	(nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
1004165f GR	69
	70	static void nlm_usb_intr_en(int node, int port)
	71	{
	72	uint32_t val;
	73	uint64_t port_addr;
	74
	75	port_addr = nlm_get_usb_regbase(node, port);
	76	val = nlm_read_usb_reg(port_addr, USB_INT_EN);
	77	val = USB_CTRL_INTERRUPT_EN \| USB_OHCI_INTERRUPT_EN \|
70342287	78	USB_OHCI_INTERRUPT1_EN \| USB_CTRL_INTERRUPT_EN \|
1004165f GR	79	USB_OHCI_INTERRUPT_EN \| USB_OHCI_INTERRUPT2_EN;
	80	nlm_write_usb_reg(port_addr, USB_INT_EN, val);
	81	}
	82
	83	static void nlm_usb_hw_reset(int node, int port)
	84	{
	85	uint64_t port_addr;
	86	uint32_t val;
	87
	88	/* reset USB phy */
	89	port_addr = nlm_get_usb_regbase(node, port);
	90	val = nlm_read_usb_reg(port_addr, USB_PHY_0);
	91	val &= ~(USB_PHY_RESET \| USB_PHY_PORT_RESET_0 \| USB_PHY_PORT_RESET_1);
	92	nlm_write_usb_reg(port_addr, USB_PHY_0, val);
	93
	94	mdelay(100);
	95	val = nlm_read_usb_reg(port_addr, USB_CTL_0);
	96	val &= ~(USB_CONTROLLER_RESET);
	97	val \|= 0x4;
	98	nlm_write_usb_reg(port_addr, USB_CTL_0, val);
	99	}
	100
	101	static int __init nlm_platform_usb_init(void)
	102	{
	103	pr_info("Initializing USB Interface\n");
	104	nlm_usb_hw_reset(0, 0);
	105	nlm_usb_hw_reset(0, 3);
	106
	107	/* Enable PHY interrupts */
	108	nlm_usb_intr_en(0, 0);
	109	nlm_usb_intr_en(0, 3);
	110
	111	return 0;
	112	}
	113
	114	arch_initcall(nlm_platform_usb_init);
	115
	116	static u64 xlp_usb_dmamask = ~(u32)0;
	117
	118	/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */
	119	static void nlm_usb_fixup_final(struct pci_dev *dev)
	120	{
	121	dev->dev.dma_mask = &xlp_usb_dmamask;
35ac7840	122	dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1004165f GR	123	switch (dev->devfn) {
1004165f GR	124	case 0x10:
c80dd3b6 J	125	dev->irq = PIC_EHCI_0_IRQ;
c80dd3b6 J	126	break;
1004165f	127	case 0x11:
c80dd3b6 J	128	dev->irq = PIC_OHCI_0_IRQ;
c80dd3b6 J	129	break;
1004165f	130	case 0x12:
c80dd3b6 J	131	dev->irq = PIC_OHCI_1_IRQ;
c80dd3b6 J	132	break;
1004165f	133	case 0x13:
c80dd3b6 J	134	dev->irq = PIC_EHCI_1_IRQ;
c80dd3b6 J	135	break;
1004165f	136	case 0x14:
c80dd3b6 J	137	dev->irq = PIC_OHCI_2_IRQ;
c80dd3b6 J	138	break;
1004165f	139	case 0x15:
c80dd3b6 J	140	dev->irq = PIC_OHCI_3_IRQ;
c80dd3b6 J	141	break;
1004165f GR	142	}
	143	}
	144	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI,
	145	nlm_usb_fixup_final);
	146	DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI,
	147	nlm_usb_fixup_final);