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c6610de3 MC |
1 | /* |
2 | * Just-In-Time compiler for BPF filters on MIPS | |
3 | * | |
4 | * Copyright (c) 2014 Imagination Technologies Ltd. | |
5 | * Author: Markos Chandras <markos.chandras@imgtec.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; version 2 of the License. | |
10 | */ | |
11 | ||
12 | #include <linux/bitops.h> | |
13 | #include <linux/compiler.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/filter.h> | |
16 | #include <linux/if_vlan.h> | |
17 | #include <linux/kconfig.h> | |
18 | #include <linux/moduleloader.h> | |
19 | #include <linux/netdevice.h> | |
20 | #include <linux/string.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/types.h> | |
23 | #include <asm/bitops.h> | |
24 | #include <asm/cacheflush.h> | |
25 | #include <asm/cpu-features.h> | |
26 | #include <asm/uasm.h> | |
27 | ||
28 | #include "bpf_jit.h" | |
29 | ||
30 | /* ABI | |
31 | * | |
32 | * s0 1st scratch register | |
33 | * s1 2nd scratch register | |
34 | * s2 offset register | |
35 | * s3 BPF register A | |
36 | * s4 BPF register X | |
37 | * s5 *skb | |
38 | * s6 *scratch memory | |
39 | * | |
40 | * On entry (*bpf_func)(*skb, *filter) | |
41 | * a0 = MIPS_R_A0 = skb; | |
42 | * a1 = MIPS_R_A1 = filter; | |
43 | * | |
44 | * Stack | |
45 | * ... | |
46 | * M[15] | |
47 | * M[14] | |
48 | * M[13] | |
49 | * ... | |
50 | * M[0] <-- r_M | |
51 | * saved reg k-1 | |
52 | * saved reg k-2 | |
53 | * ... | |
54 | * saved reg 0 <-- r_sp | |
55 | * <no argument area> | |
56 | * | |
57 | * Packet layout | |
58 | * | |
59 | * <--------------------- len ------------------------> | |
60 | * <--skb-len(r_skb_hl)-->< ----- skb->data_len ------> | |
61 | * ---------------------------------------------------- | |
62 | * | skb->data | | |
63 | * ---------------------------------------------------- | |
64 | */ | |
65 | ||
66 | #define RSIZE (sizeof(unsigned long)) | |
67 | #define ptr typeof(unsigned long) | |
68 | ||
69 | /* ABI specific return values */ | |
70 | #ifdef CONFIG_32BIT /* O32 */ | |
71 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
72 | #define r_err MIPS_R_V1 | |
73 | #define r_val MIPS_R_V0 | |
74 | #else /* CONFIG_CPU_LITTLE_ENDIAN */ | |
75 | #define r_err MIPS_R_V0 | |
76 | #define r_val MIPS_R_V1 | |
77 | #endif | |
78 | #else /* N64 */ | |
79 | #define r_err MIPS_R_V0 | |
80 | #define r_val MIPS_R_V0 | |
81 | #endif | |
82 | ||
83 | #define r_ret MIPS_R_V0 | |
84 | ||
85 | /* | |
86 | * Use 2 scratch registers to avoid pipeline interlocks. | |
87 | * There is no overhead during epilogue and prologue since | |
88 | * any of the $s0-$s6 registers will only be preserved if | |
89 | * they are going to actually be used. | |
90 | */ | |
91 | #define r_s0 MIPS_R_S0 /* scratch reg 1 */ | |
92 | #define r_s1 MIPS_R_S1 /* scratch reg 2 */ | |
93 | #define r_off MIPS_R_S2 | |
94 | #define r_A MIPS_R_S3 | |
95 | #define r_X MIPS_R_S4 | |
96 | #define r_skb MIPS_R_S5 | |
97 | #define r_M MIPS_R_S6 | |
98 | #define r_tmp_imm MIPS_R_T6 /* No need to preserve this */ | |
99 | #define r_tmp MIPS_R_T7 /* No need to preserve this */ | |
100 | #define r_zero MIPS_R_ZERO | |
101 | #define r_sp MIPS_R_SP | |
102 | #define r_ra MIPS_R_RA | |
103 | ||
104 | #define SCRATCH_OFF(k) (4 * (k)) | |
105 | ||
106 | /* JIT flags */ | |
107 | #define SEEN_CALL (1 << BPF_MEMWORDS) | |
108 | #define SEEN_SREG_SFT (BPF_MEMWORDS + 1) | |
109 | #define SEEN_SREG_BASE (1 << SEEN_SREG_SFT) | |
110 | #define SEEN_SREG(x) (SEEN_SREG_BASE << (x)) | |
111 | #define SEEN_S0 SEEN_SREG(0) | |
112 | #define SEEN_S1 SEEN_SREG(1) | |
113 | #define SEEN_OFF SEEN_SREG(2) | |
114 | #define SEEN_A SEEN_SREG(3) | |
115 | #define SEEN_X SEEN_SREG(4) | |
116 | #define SEEN_SKB SEEN_SREG(5) | |
117 | #define SEEN_MEM SEEN_SREG(6) | |
118 | ||
119 | /* Arguments used by JIT */ | |
120 | #define ARGS_USED_BY_JIT 2 /* only applicable to 64-bit */ | |
121 | ||
122 | #define FLAG_NEED_X_RESET (1 << 0) | |
123 | ||
124 | #define SBIT(x) (1 << (x)) /* Signed version of BIT() */ | |
125 | ||
126 | /** | |
127 | * struct jit_ctx - JIT context | |
128 | * @skf: The sk_filter | |
129 | * @prologue_bytes: Number of bytes for prologue | |
130 | * @idx: Instruction index | |
131 | * @flags: JIT flags | |
132 | * @offsets: Instruction offsets | |
133 | * @target: Memory location for the compiled filter | |
134 | */ | |
135 | struct jit_ctx { | |
136 | const struct sk_filter *skf; | |
137 | unsigned int prologue_bytes; | |
138 | u32 idx; | |
139 | u32 flags; | |
140 | u32 *offsets; | |
141 | u32 *target; | |
142 | }; | |
143 | ||
144 | ||
145 | static inline int optimize_div(u32 *k) | |
146 | { | |
147 | /* power of 2 divides can be implemented with right shift */ | |
148 | if (!(*k & (*k-1))) { | |
149 | *k = ilog2(*k); | |
150 | return 1; | |
151 | } | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
156 | /* Simply emit the instruction if the JIT memory space has been allocated */ | |
157 | #define emit_instr(ctx, func, ...) \ | |
158 | do { \ | |
159 | if ((ctx)->target != NULL) { \ | |
160 | u32 *p = &(ctx)->target[ctx->idx]; \ | |
161 | uasm_i_##func(&p, ##__VA_ARGS__); \ | |
162 | } \ | |
163 | (ctx)->idx++; \ | |
164 | } while (0) | |
165 | ||
166 | /* Determine if immediate is within the 16-bit signed range */ | |
167 | static inline bool is_range16(s32 imm) | |
168 | { | |
169 | if (imm >= SBIT(15) || imm < -SBIT(15)) | |
170 | return true; | |
171 | return false; | |
172 | } | |
173 | ||
174 | static inline void emit_addu(unsigned int dst, unsigned int src1, | |
175 | unsigned int src2, struct jit_ctx *ctx) | |
176 | { | |
177 | emit_instr(ctx, addu, dst, src1, src2); | |
178 | } | |
179 | ||
180 | static inline void emit_nop(struct jit_ctx *ctx) | |
181 | { | |
182 | emit_instr(ctx, nop); | |
183 | } | |
184 | ||
185 | /* Load a u32 immediate to a register */ | |
186 | static inline void emit_load_imm(unsigned int dst, u32 imm, struct jit_ctx *ctx) | |
187 | { | |
188 | if (ctx->target != NULL) { | |
189 | /* addiu can only handle s16 */ | |
190 | if (is_range16(imm)) { | |
191 | u32 *p = &ctx->target[ctx->idx]; | |
192 | uasm_i_lui(&p, r_tmp_imm, (s32)imm >> 16); | |
193 | p = &ctx->target[ctx->idx + 1]; | |
194 | uasm_i_ori(&p, dst, r_tmp_imm, imm & 0xffff); | |
195 | } else { | |
196 | u32 *p = &ctx->target[ctx->idx]; | |
197 | uasm_i_addiu(&p, dst, r_zero, imm); | |
198 | } | |
199 | } | |
200 | ctx->idx++; | |
201 | ||
202 | if (is_range16(imm)) | |
203 | ctx->idx++; | |
204 | } | |
205 | ||
206 | static inline void emit_or(unsigned int dst, unsigned int src1, | |
207 | unsigned int src2, struct jit_ctx *ctx) | |
208 | { | |
209 | emit_instr(ctx, or, dst, src1, src2); | |
210 | } | |
211 | ||
212 | static inline void emit_ori(unsigned int dst, unsigned src, u32 imm, | |
213 | struct jit_ctx *ctx) | |
214 | { | |
215 | if (imm >= BIT(16)) { | |
216 | emit_load_imm(r_tmp, imm, ctx); | |
217 | emit_or(dst, src, r_tmp, ctx); | |
218 | } else { | |
219 | emit_instr(ctx, ori, dst, src, imm); | |
220 | } | |
221 | } | |
222 | ||
223 | ||
224 | static inline void emit_daddu(unsigned int dst, unsigned int src1, | |
225 | unsigned int src2, struct jit_ctx *ctx) | |
226 | { | |
227 | emit_instr(ctx, daddu, dst, src1, src2); | |
228 | } | |
229 | ||
230 | static inline void emit_daddiu(unsigned int dst, unsigned int src, | |
231 | int imm, struct jit_ctx *ctx) | |
232 | { | |
233 | /* | |
234 | * Only used for stack, so the imm is relatively small | |
235 | * and it fits in 15-bits | |
236 | */ | |
237 | emit_instr(ctx, daddiu, dst, src, imm); | |
238 | } | |
239 | ||
240 | static inline void emit_addiu(unsigned int dst, unsigned int src, | |
241 | u32 imm, struct jit_ctx *ctx) | |
242 | { | |
243 | if (is_range16(imm)) { | |
244 | emit_load_imm(r_tmp, imm, ctx); | |
245 | emit_addu(dst, r_tmp, src, ctx); | |
246 | } else { | |
247 | emit_instr(ctx, addiu, dst, src, imm); | |
248 | } | |
249 | } | |
250 | ||
251 | static inline void emit_and(unsigned int dst, unsigned int src1, | |
252 | unsigned int src2, struct jit_ctx *ctx) | |
253 | { | |
254 | emit_instr(ctx, and, dst, src1, src2); | |
255 | } | |
256 | ||
257 | static inline void emit_andi(unsigned int dst, unsigned int src, | |
258 | u32 imm, struct jit_ctx *ctx) | |
259 | { | |
260 | /* If imm does not fit in u16 then load it to register */ | |
261 | if (imm >= BIT(16)) { | |
262 | emit_load_imm(r_tmp, imm, ctx); | |
263 | emit_and(dst, src, r_tmp, ctx); | |
264 | } else { | |
265 | emit_instr(ctx, andi, dst, src, imm); | |
266 | } | |
267 | } | |
268 | ||
269 | static inline void emit_xor(unsigned int dst, unsigned int src1, | |
270 | unsigned int src2, struct jit_ctx *ctx) | |
271 | { | |
272 | emit_instr(ctx, xor, dst, src1, src2); | |
273 | } | |
274 | ||
275 | static inline void emit_xori(ptr dst, ptr src, u32 imm, struct jit_ctx *ctx) | |
276 | { | |
277 | /* If imm does not fit in u16 then load it to register */ | |
278 | if (imm >= BIT(16)) { | |
279 | emit_load_imm(r_tmp, imm, ctx); | |
280 | emit_xor(dst, src, r_tmp, ctx); | |
281 | } else { | |
282 | emit_instr(ctx, xori, dst, src, imm); | |
283 | } | |
284 | } | |
285 | ||
286 | static inline void emit_stack_offset(int offset, struct jit_ctx *ctx) | |
287 | { | |
288 | if (config_enabled(CONFIG_64BIT)) | |
289 | emit_instr(ctx, daddiu, r_sp, r_sp, offset); | |
290 | else | |
291 | emit_instr(ctx, addiu, r_sp, r_sp, offset); | |
292 | ||
293 | } | |
294 | ||
295 | static inline void emit_subu(unsigned int dst, unsigned int src1, | |
296 | unsigned int src2, struct jit_ctx *ctx) | |
297 | { | |
298 | emit_instr(ctx, subu, dst, src1, src2); | |
299 | } | |
300 | ||
301 | static inline void emit_neg(unsigned int reg, struct jit_ctx *ctx) | |
302 | { | |
303 | emit_subu(reg, r_zero, reg, ctx); | |
304 | } | |
305 | ||
306 | static inline void emit_sllv(unsigned int dst, unsigned int src, | |
307 | unsigned int sa, struct jit_ctx *ctx) | |
308 | { | |
309 | emit_instr(ctx, sllv, dst, src, sa); | |
310 | } | |
311 | ||
312 | static inline void emit_sll(unsigned int dst, unsigned int src, | |
313 | unsigned int sa, struct jit_ctx *ctx) | |
314 | { | |
315 | /* sa is 5-bits long */ | |
316 | BUG_ON(sa >= BIT(5)); | |
317 | emit_instr(ctx, sll, dst, src, sa); | |
318 | } | |
319 | ||
320 | static inline void emit_srlv(unsigned int dst, unsigned int src, | |
321 | unsigned int sa, struct jit_ctx *ctx) | |
322 | { | |
323 | emit_instr(ctx, srlv, dst, src, sa); | |
324 | } | |
325 | ||
326 | static inline void emit_srl(unsigned int dst, unsigned int src, | |
327 | unsigned int sa, struct jit_ctx *ctx) | |
328 | { | |
329 | /* sa is 5-bits long */ | |
330 | BUG_ON(sa >= BIT(5)); | |
331 | emit_instr(ctx, srl, dst, src, sa); | |
332 | } | |
333 | ||
334 | static inline void emit_sltu(unsigned int dst, unsigned int src1, | |
335 | unsigned int src2, struct jit_ctx *ctx) | |
336 | { | |
337 | emit_instr(ctx, sltu, dst, src1, src2); | |
338 | } | |
339 | ||
340 | static inline void emit_sltiu(unsigned dst, unsigned int src, | |
341 | unsigned int imm, struct jit_ctx *ctx) | |
342 | { | |
343 | /* 16 bit immediate */ | |
344 | if (is_range16((s32)imm)) { | |
345 | emit_load_imm(r_tmp, imm, ctx); | |
346 | emit_sltu(dst, src, r_tmp, ctx); | |
347 | } else { | |
348 | emit_instr(ctx, sltiu, dst, src, imm); | |
349 | } | |
350 | ||
351 | } | |
352 | ||
353 | /* Store register on the stack */ | |
354 | static inline void emit_store_stack_reg(ptr reg, ptr base, | |
355 | unsigned int offset, | |
356 | struct jit_ctx *ctx) | |
357 | { | |
358 | if (config_enabled(CONFIG_64BIT)) | |
359 | emit_instr(ctx, sd, reg, offset, base); | |
360 | else | |
361 | emit_instr(ctx, sw, reg, offset, base); | |
362 | } | |
363 | ||
364 | static inline void emit_store(ptr reg, ptr base, unsigned int offset, | |
365 | struct jit_ctx *ctx) | |
366 | { | |
367 | emit_instr(ctx, sw, reg, offset, base); | |
368 | } | |
369 | ||
370 | static inline void emit_load_stack_reg(ptr reg, ptr base, | |
371 | unsigned int offset, | |
372 | struct jit_ctx *ctx) | |
373 | { | |
374 | if (config_enabled(CONFIG_64BIT)) | |
375 | emit_instr(ctx, ld, reg, offset, base); | |
376 | else | |
377 | emit_instr(ctx, lw, reg, offset, base); | |
378 | } | |
379 | ||
380 | static inline void emit_load(unsigned int reg, unsigned int base, | |
381 | unsigned int offset, struct jit_ctx *ctx) | |
382 | { | |
383 | emit_instr(ctx, lw, reg, offset, base); | |
384 | } | |
385 | ||
386 | static inline void emit_load_byte(unsigned int reg, unsigned int base, | |
387 | unsigned int offset, struct jit_ctx *ctx) | |
388 | { | |
389 | emit_instr(ctx, lb, reg, offset, base); | |
390 | } | |
391 | ||
392 | static inline void emit_half_load(unsigned int reg, unsigned int base, | |
393 | unsigned int offset, struct jit_ctx *ctx) | |
394 | { | |
395 | emit_instr(ctx, lh, reg, offset, base); | |
396 | } | |
397 | ||
398 | static inline void emit_mul(unsigned int dst, unsigned int src1, | |
399 | unsigned int src2, struct jit_ctx *ctx) | |
400 | { | |
401 | emit_instr(ctx, mul, dst, src1, src2); | |
402 | } | |
403 | ||
404 | static inline void emit_div(unsigned int dst, unsigned int src, | |
405 | struct jit_ctx *ctx) | |
406 | { | |
407 | if (ctx->target != NULL) { | |
408 | u32 *p = &ctx->target[ctx->idx]; | |
409 | uasm_i_divu(&p, dst, src); | |
410 | p = &ctx->target[ctx->idx + 1]; | |
411 | uasm_i_mfhi(&p, dst); | |
412 | } | |
413 | ctx->idx += 2; /* 2 insts */ | |
414 | } | |
415 | ||
416 | static inline void emit_mod(unsigned int dst, unsigned int src, | |
417 | struct jit_ctx *ctx) | |
418 | { | |
419 | if (ctx->target != NULL) { | |
420 | u32 *p = &ctx->target[ctx->idx]; | |
421 | uasm_i_divu(&p, dst, src); | |
422 | p = &ctx->target[ctx->idx + 1]; | |
423 | uasm_i_mflo(&p, dst); | |
424 | } | |
425 | ctx->idx += 2; /* 2 insts */ | |
426 | } | |
427 | ||
428 | static inline void emit_dsll(unsigned int dst, unsigned int src, | |
429 | unsigned int sa, struct jit_ctx *ctx) | |
430 | { | |
431 | emit_instr(ctx, dsll, dst, src, sa); | |
432 | } | |
433 | ||
434 | static inline void emit_dsrl32(unsigned int dst, unsigned int src, | |
435 | unsigned int sa, struct jit_ctx *ctx) | |
436 | { | |
437 | emit_instr(ctx, dsrl32, dst, src, sa); | |
438 | } | |
439 | ||
440 | static inline void emit_wsbh(unsigned int dst, unsigned int src, | |
441 | struct jit_ctx *ctx) | |
442 | { | |
443 | emit_instr(ctx, wsbh, dst, src); | |
444 | } | |
445 | ||
446 | /* load a function pointer to register */ | |
447 | static inline void emit_load_func(unsigned int reg, ptr imm, | |
448 | struct jit_ctx *ctx) | |
449 | { | |
450 | if (config_enabled(CONFIG_64BIT)) { | |
451 | /* At this point imm is always 64-bit */ | |
452 | emit_load_imm(r_tmp, (u64)imm >> 32, ctx); | |
453 | emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */ | |
454 | emit_ori(r_tmp, r_tmp_imm, (imm >> 16) & 0xffff, ctx); | |
455 | emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */ | |
456 | emit_ori(reg, r_tmp_imm, imm & 0xffff, ctx); | |
457 | } else { | |
458 | emit_load_imm(reg, imm, ctx); | |
459 | } | |
460 | } | |
461 | ||
462 | /* Move to real MIPS register */ | |
463 | static inline void emit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx) | |
464 | { | |
465 | if (config_enabled(CONFIG_64BIT)) | |
466 | emit_daddu(dst, src, r_zero, ctx); | |
467 | else | |
468 | emit_addu(dst, src, r_zero, ctx); | |
469 | } | |
470 | ||
471 | /* Move to JIT (32-bit) register */ | |
472 | static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx) | |
473 | { | |
474 | emit_addu(dst, src, r_zero, ctx); | |
475 | } | |
476 | ||
477 | /* Compute the immediate value for PC-relative branches. */ | |
478 | static inline u32 b_imm(unsigned int tgt, struct jit_ctx *ctx) | |
479 | { | |
480 | if (ctx->target == NULL) | |
481 | return 0; | |
482 | ||
483 | /* | |
484 | * We want a pc-relative branch. We only do forward branches | |
485 | * so tgt is always after pc. tgt is the instruction offset | |
486 | * we want to jump to. | |
487 | ||
488 | * Branch on MIPS: | |
489 | * I: target_offset <- sign_extend(offset) | |
490 | * I+1: PC += target_offset (delay slot) | |
491 | * | |
492 | * ctx->idx currently points to the branch instruction | |
493 | * but the offset is added to the delay slot so we need | |
494 | * to subtract 4. | |
495 | */ | |
496 | return ctx->offsets[tgt] - | |
497 | (ctx->idx * 4 - ctx->prologue_bytes) - 4; | |
498 | } | |
499 | ||
500 | static inline void emit_bcond(int cond, unsigned int reg1, unsigned int reg2, | |
501 | unsigned int imm, struct jit_ctx *ctx) | |
502 | { | |
503 | if (ctx->target != NULL) { | |
504 | u32 *p = &ctx->target[ctx->idx]; | |
505 | ||
506 | switch (cond) { | |
507 | case MIPS_COND_EQ: | |
508 | uasm_i_beq(&p, reg1, reg2, imm); | |
509 | break; | |
510 | case MIPS_COND_NE: | |
511 | uasm_i_bne(&p, reg1, reg2, imm); | |
512 | break; | |
513 | case MIPS_COND_ALL: | |
514 | uasm_i_b(&p, imm); | |
515 | break; | |
516 | default: | |
517 | pr_warn("%s: Unhandled branch conditional: %d\n", | |
518 | __func__, cond); | |
519 | } | |
520 | } | |
521 | ctx->idx++; | |
522 | } | |
523 | ||
524 | static inline void emit_b(unsigned int imm, struct jit_ctx *ctx) | |
525 | { | |
526 | emit_bcond(MIPS_COND_ALL, r_zero, r_zero, imm, ctx); | |
527 | } | |
528 | ||
529 | static inline void emit_jalr(unsigned int link, unsigned int reg, | |
530 | struct jit_ctx *ctx) | |
531 | { | |
532 | emit_instr(ctx, jalr, link, reg); | |
533 | } | |
534 | ||
535 | static inline void emit_jr(unsigned int reg, struct jit_ctx *ctx) | |
536 | { | |
537 | emit_instr(ctx, jr, reg); | |
538 | } | |
539 | ||
540 | static inline u16 align_sp(unsigned int num) | |
541 | { | |
542 | /* Double word alignment for 32-bit, quadword for 64-bit */ | |
543 | unsigned int align = config_enabled(CONFIG_64BIT) ? 16 : 8; | |
544 | num = (num + (align - 1)) & -align; | |
545 | return num; | |
546 | } | |
547 | ||
548 | static inline void update_on_xread(struct jit_ctx *ctx) | |
549 | { | |
550 | if (!(ctx->flags & SEEN_X)) | |
551 | ctx->flags |= FLAG_NEED_X_RESET; | |
552 | ||
553 | ctx->flags |= SEEN_X; | |
554 | } | |
555 | ||
556 | static bool is_load_to_a(u16 inst) | |
557 | { | |
558 | switch (inst) { | |
a83d081e DB |
559 | case BPF_LD | BPF_W | BPF_LEN: |
560 | case BPF_LD | BPF_W | BPF_ABS: | |
561 | case BPF_LD | BPF_H | BPF_ABS: | |
562 | case BPF_LD | BPF_B | BPF_ABS: | |
c6610de3 MC |
563 | return true; |
564 | default: | |
565 | return false; | |
566 | } | |
567 | } | |
568 | ||
569 | static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset) | |
570 | { | |
571 | int i = 0, real_off = 0; | |
572 | u32 sflags, tmp_flags; | |
573 | ||
574 | /* Adjust the stack pointer */ | |
575 | emit_stack_offset(-align_sp(offset), ctx); | |
576 | ||
577 | if (ctx->flags & SEEN_CALL) { | |
578 | /* Argument save area */ | |
579 | if (config_enabled(CONFIG_64BIT)) | |
580 | /* Bottom of current frame */ | |
581 | real_off = align_sp(offset) - RSIZE; | |
582 | else | |
583 | /* Top of previous frame */ | |
584 | real_off = align_sp(offset) + RSIZE; | |
585 | emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx); | |
586 | emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx); | |
587 | ||
588 | real_off = 0; | |
589 | } | |
590 | ||
591 | tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT; | |
592 | /* sflags is essentially a bitmap */ | |
593 | while (tmp_flags) { | |
594 | if ((sflags >> i) & 0x1) { | |
595 | emit_store_stack_reg(MIPS_R_S0 + i, r_sp, real_off, | |
596 | ctx); | |
597 | real_off += RSIZE; | |
598 | } | |
599 | i++; | |
600 | tmp_flags >>= 1; | |
601 | } | |
602 | ||
603 | /* save return address */ | |
604 | if (ctx->flags & SEEN_CALL) { | |
605 | emit_store_stack_reg(r_ra, r_sp, real_off, ctx); | |
606 | real_off += RSIZE; | |
607 | } | |
608 | ||
609 | /* Setup r_M leaving the alignment gap if necessary */ | |
610 | if (ctx->flags & SEEN_MEM) { | |
611 | if (real_off % (RSIZE * 2)) | |
612 | real_off += RSIZE; | |
613 | emit_addiu(r_M, r_sp, real_off, ctx); | |
614 | } | |
615 | } | |
616 | ||
617 | static void restore_bpf_jit_regs(struct jit_ctx *ctx, | |
618 | unsigned int offset) | |
619 | { | |
620 | int i, real_off = 0; | |
621 | u32 sflags, tmp_flags; | |
622 | ||
623 | if (ctx->flags & SEEN_CALL) { | |
624 | if (config_enabled(CONFIG_64BIT)) | |
625 | /* Bottom of current frame */ | |
626 | real_off = align_sp(offset) - RSIZE; | |
627 | else | |
628 | /* Top of previous frame */ | |
629 | real_off = align_sp(offset) + RSIZE; | |
630 | emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx); | |
631 | emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx); | |
632 | ||
633 | real_off = 0; | |
634 | } | |
635 | ||
636 | tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT; | |
637 | /* sflags is a bitmap */ | |
638 | i = 0; | |
639 | while (tmp_flags) { | |
640 | if ((sflags >> i) & 0x1) { | |
641 | emit_load_stack_reg(MIPS_R_S0 + i, r_sp, real_off, | |
642 | ctx); | |
643 | real_off += RSIZE; | |
644 | } | |
645 | i++; | |
646 | tmp_flags >>= 1; | |
647 | } | |
648 | ||
649 | /* restore return address */ | |
650 | if (ctx->flags & SEEN_CALL) | |
651 | emit_load_stack_reg(r_ra, r_sp, real_off, ctx); | |
652 | ||
653 | /* Restore the sp and discard the scrach memory */ | |
654 | emit_stack_offset(align_sp(offset), ctx); | |
655 | } | |
656 | ||
657 | static unsigned int get_stack_depth(struct jit_ctx *ctx) | |
658 | { | |
659 | int sp_off = 0; | |
660 | ||
661 | ||
662 | /* How may s* regs do we need to preserved? */ | |
663 | sp_off += hweight32(ctx->flags >> SEEN_SREG_SFT) * RSIZE; | |
664 | ||
665 | if (ctx->flags & SEEN_MEM) | |
666 | sp_off += 4 * BPF_MEMWORDS; /* BPF_MEMWORDS are 32-bit */ | |
667 | ||
668 | if (ctx->flags & SEEN_CALL) | |
669 | /* | |
670 | * The JIT code make calls to external functions using 2 | |
671 | * arguments. Therefore, for o32 we don't need to allocate | |
672 | * space because we don't care if the argumetns are lost | |
673 | * across calls. We do need however to preserve incoming | |
674 | * arguments but the space is already allocated for us by | |
675 | * the caller. On the other hand, for n64, we need to allocate | |
676 | * this space ourselves. We need to preserve $ra as well. | |
677 | */ | |
678 | sp_off += config_enabled(CONFIG_64BIT) ? | |
679 | (ARGS_USED_BY_JIT + 1) * RSIZE : RSIZE; | |
680 | ||
681 | /* | |
682 | * Subtract the bytes for the last registers since we only care about | |
683 | * the location on the stack pointer. | |
684 | */ | |
685 | return sp_off - RSIZE; | |
686 | } | |
687 | ||
688 | static void build_prologue(struct jit_ctx *ctx) | |
689 | { | |
690 | u16 first_inst = ctx->skf->insns[0].code; | |
691 | int sp_off; | |
692 | ||
693 | /* Calculate the total offset for the stack pointer */ | |
694 | sp_off = get_stack_depth(ctx); | |
695 | save_bpf_jit_regs(ctx, sp_off); | |
696 | ||
697 | if (ctx->flags & SEEN_SKB) | |
698 | emit_reg_move(r_skb, MIPS_R_A0, ctx); | |
699 | ||
700 | if (ctx->flags & FLAG_NEED_X_RESET) | |
701 | emit_jit_reg_move(r_X, r_zero, ctx); | |
702 | ||
703 | /* Do not leak kernel data to userspace */ | |
a83d081e | 704 | if ((first_inst != (BPF_RET | BPF_K)) && !(is_load_to_a(first_inst))) |
c6610de3 MC |
705 | emit_jit_reg_move(r_A, r_zero, ctx); |
706 | } | |
707 | ||
708 | static void build_epilogue(struct jit_ctx *ctx) | |
709 | { | |
710 | unsigned int sp_off; | |
711 | ||
712 | /* Calculate the total offset for the stack pointer */ | |
713 | ||
714 | sp_off = get_stack_depth(ctx); | |
715 | restore_bpf_jit_regs(ctx, sp_off); | |
716 | ||
717 | /* Return */ | |
718 | emit_jr(r_ra, ctx); | |
719 | emit_nop(ctx); | |
720 | } | |
721 | ||
722 | static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset) | |
723 | { | |
724 | u8 ret; | |
725 | int err; | |
726 | ||
727 | err = skb_copy_bits(skb, offset, &ret, 1); | |
728 | ||
729 | return (u64)err << 32 | ret; | |
730 | } | |
731 | ||
732 | static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset) | |
733 | { | |
734 | u16 ret; | |
735 | int err; | |
736 | ||
737 | err = skb_copy_bits(skb, offset, &ret, 2); | |
738 | ||
739 | return (u64)err << 32 | ntohs(ret); | |
740 | } | |
741 | ||
742 | static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset) | |
743 | { | |
744 | u32 ret; | |
745 | int err; | |
746 | ||
747 | err = skb_copy_bits(skb, offset, &ret, 4); | |
748 | ||
749 | return (u64)err << 32 | ntohl(ret); | |
750 | } | |
751 | ||
752 | #define PKT_TYPE_MAX 7 | |
753 | static int pkt_type_offset(void) | |
754 | { | |
755 | struct sk_buff skb_probe = { | |
756 | .pkt_type = ~0, | |
757 | }; | |
758 | char *ct = (char *)&skb_probe; | |
759 | unsigned int off; | |
760 | ||
761 | for (off = 0; off < sizeof(struct sk_buff); off++) { | |
762 | if (ct[off] == PKT_TYPE_MAX) | |
763 | return off; | |
764 | } | |
765 | pr_err_once("Please fix pkt_type_offset(), as pkt_type couldn't be found\n"); | |
766 | return -1; | |
767 | } | |
768 | ||
769 | static int build_body(struct jit_ctx *ctx) | |
770 | { | |
771 | void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w}; | |
772 | const struct sk_filter *prog = ctx->skf; | |
773 | const struct sock_filter *inst; | |
774 | unsigned int i, off, load_order, condt; | |
775 | u32 k, b_off __maybe_unused; | |
776 | ||
777 | for (i = 0; i < prog->len; i++) { | |
a83d081e DB |
778 | u16 code; |
779 | ||
c6610de3 MC |
780 | inst = &(prog->insns[i]); |
781 | pr_debug("%s: code->0x%02x, jt->0x%x, jf->0x%x, k->0x%x\n", | |
782 | __func__, inst->code, inst->jt, inst->jf, inst->k); | |
783 | k = inst->k; | |
a83d081e | 784 | code = bpf_anc_helper(inst); |
c6610de3 MC |
785 | |
786 | if (ctx->target == NULL) | |
787 | ctx->offsets[i] = ctx->idx * 4; | |
788 | ||
a83d081e DB |
789 | switch (code) { |
790 | case BPF_LD | BPF_IMM: | |
c6610de3 MC |
791 | /* A <- k ==> li r_A, k */ |
792 | ctx->flags |= SEEN_A; | |
793 | emit_load_imm(r_A, k, ctx); | |
794 | break; | |
a83d081e | 795 | case BPF_LD | BPF_W | BPF_LEN: |
c6610de3 MC |
796 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4); |
797 | /* A <- len ==> lw r_A, offset(skb) */ | |
798 | ctx->flags |= SEEN_SKB | SEEN_A; | |
799 | off = offsetof(struct sk_buff, len); | |
800 | emit_load(r_A, r_skb, off, ctx); | |
801 | break; | |
a83d081e | 802 | case BPF_LD | BPF_MEM: |
c6610de3 MC |
803 | /* A <- M[k] ==> lw r_A, offset(M) */ |
804 | ctx->flags |= SEEN_MEM | SEEN_A; | |
805 | emit_load(r_A, r_M, SCRATCH_OFF(k), ctx); | |
806 | break; | |
a83d081e | 807 | case BPF_LD | BPF_W | BPF_ABS: |
c6610de3 MC |
808 | /* A <- P[k:4] */ |
809 | load_order = 2; | |
810 | goto load; | |
a83d081e | 811 | case BPF_LD | BPF_H | BPF_ABS: |
c6610de3 MC |
812 | /* A <- P[k:2] */ |
813 | load_order = 1; | |
814 | goto load; | |
a83d081e | 815 | case BPF_LD | BPF_B | BPF_ABS: |
c6610de3 MC |
816 | /* A <- P[k:1] */ |
817 | load_order = 0; | |
818 | load: | |
819 | emit_load_imm(r_off, k, ctx); | |
820 | load_common: | |
821 | ctx->flags |= SEEN_CALL | SEEN_OFF | SEEN_S0 | | |
822 | SEEN_SKB | SEEN_A; | |
823 | ||
824 | emit_load_func(r_s0, (ptr)load_func[load_order], | |
825 | ctx); | |
826 | emit_reg_move(MIPS_R_A0, r_skb, ctx); | |
827 | emit_jalr(MIPS_R_RA, r_s0, ctx); | |
828 | /* Load second argument to delay slot */ | |
829 | emit_reg_move(MIPS_R_A1, r_off, ctx); | |
830 | /* Check the error value */ | |
831 | if (config_enabled(CONFIG_64BIT)) { | |
832 | /* Get error code from the top 32-bits */ | |
833 | emit_dsrl32(r_s0, r_val, 0, ctx); | |
834 | /* Branch to 3 instructions ahead */ | |
835 | emit_bcond(MIPS_COND_NE, r_s0, r_zero, 3 << 2, | |
836 | ctx); | |
837 | } else { | |
838 | /* Branch to 3 instructions ahead */ | |
839 | emit_bcond(MIPS_COND_NE, r_err, r_zero, 3 << 2, | |
840 | ctx); | |
841 | } | |
842 | emit_nop(ctx); | |
843 | /* We are good */ | |
844 | emit_b(b_imm(i + 1, ctx), ctx); | |
845 | emit_jit_reg_move(r_A, r_val, ctx); | |
846 | /* Return with error */ | |
847 | emit_b(b_imm(prog->len, ctx), ctx); | |
848 | emit_reg_move(r_ret, r_zero, ctx); | |
849 | break; | |
a83d081e | 850 | case BPF_LD | BPF_W | BPF_IND: |
c6610de3 MC |
851 | /* A <- P[X + k:4] */ |
852 | load_order = 2; | |
853 | goto load_ind; | |
a83d081e | 854 | case BPF_LD | BPF_H | BPF_IND: |
c6610de3 MC |
855 | /* A <- P[X + k:2] */ |
856 | load_order = 1; | |
857 | goto load_ind; | |
a83d081e | 858 | case BPF_LD | BPF_B | BPF_IND: |
c6610de3 MC |
859 | /* A <- P[X + k:1] */ |
860 | load_order = 0; | |
861 | load_ind: | |
862 | update_on_xread(ctx); | |
863 | ctx->flags |= SEEN_OFF | SEEN_X; | |
864 | emit_addiu(r_off, r_X, k, ctx); | |
865 | goto load_common; | |
a83d081e | 866 | case BPF_LDX | BPF_IMM: |
c6610de3 MC |
867 | /* X <- k */ |
868 | ctx->flags |= SEEN_X; | |
869 | emit_load_imm(r_X, k, ctx); | |
870 | break; | |
a83d081e | 871 | case BPF_LDX | BPF_MEM: |
c6610de3 MC |
872 | /* X <- M[k] */ |
873 | ctx->flags |= SEEN_X | SEEN_MEM; | |
874 | emit_load(r_X, r_M, SCRATCH_OFF(k), ctx); | |
875 | break; | |
a83d081e | 876 | case BPF_LDX | BPF_W | BPF_LEN: |
c6610de3 MC |
877 | /* X <- len */ |
878 | ctx->flags |= SEEN_X | SEEN_SKB; | |
879 | off = offsetof(struct sk_buff, len); | |
880 | emit_load(r_X, r_skb, off, ctx); | |
881 | break; | |
a83d081e | 882 | case BPF_LDX | BPF_B | BPF_MSH: |
c6610de3 MC |
883 | /* X <- 4 * (P[k:1] & 0xf) */ |
884 | ctx->flags |= SEEN_X | SEEN_CALL | SEEN_S0 | SEEN_SKB; | |
885 | /* Load offset to a1 */ | |
886 | emit_load_func(r_s0, (ptr)jit_get_skb_b, ctx); | |
887 | /* | |
888 | * This may emit two instructions so it may not fit | |
889 | * in the delay slot. So use a0 in the delay slot. | |
890 | */ | |
891 | emit_load_imm(MIPS_R_A1, k, ctx); | |
892 | emit_jalr(MIPS_R_RA, r_s0, ctx); | |
893 | emit_reg_move(MIPS_R_A0, r_skb, ctx); /* delay slot */ | |
894 | /* Check the error value */ | |
895 | if (config_enabled(CONFIG_64BIT)) { | |
896 | /* Top 32-bits of $v0 on 64-bit */ | |
897 | emit_dsrl32(r_s0, r_val, 0, ctx); | |
898 | emit_bcond(MIPS_COND_NE, r_s0, r_zero, | |
899 | 3 << 2, ctx); | |
900 | } else { | |
901 | emit_bcond(MIPS_COND_NE, r_err, r_zero, | |
902 | 3 << 2, ctx); | |
903 | } | |
904 | /* No need for delay slot */ | |
905 | /* We are good */ | |
906 | /* X <- P[1:K] & 0xf */ | |
907 | emit_andi(r_X, r_val, 0xf, ctx); | |
908 | /* X << 2 */ | |
909 | emit_b(b_imm(i + 1, ctx), ctx); | |
910 | emit_sll(r_X, r_X, 2, ctx); /* delay slot */ | |
911 | /* Return with error */ | |
912 | emit_b(b_imm(prog->len, ctx), ctx); | |
913 | emit_load_imm(r_ret, 0, ctx); /* delay slot */ | |
914 | break; | |
a83d081e | 915 | case BPF_ST: |
c6610de3 MC |
916 | /* M[k] <- A */ |
917 | ctx->flags |= SEEN_MEM | SEEN_A; | |
918 | emit_store(r_A, r_M, SCRATCH_OFF(k), ctx); | |
919 | break; | |
a83d081e | 920 | case BPF_STX: |
c6610de3 MC |
921 | /* M[k] <- X */ |
922 | ctx->flags |= SEEN_MEM | SEEN_X; | |
923 | emit_store(r_X, r_M, SCRATCH_OFF(k), ctx); | |
924 | break; | |
a83d081e | 925 | case BPF_ALU | BPF_ADD | BPF_K: |
c6610de3 MC |
926 | /* A += K */ |
927 | ctx->flags |= SEEN_A; | |
928 | emit_addiu(r_A, r_A, k, ctx); | |
929 | break; | |
a83d081e | 930 | case BPF_ALU | BPF_ADD | BPF_X: |
c6610de3 MC |
931 | /* A += X */ |
932 | ctx->flags |= SEEN_A | SEEN_X; | |
933 | emit_addu(r_A, r_A, r_X, ctx); | |
934 | break; | |
a83d081e | 935 | case BPF_ALU | BPF_SUB | BPF_K: |
c6610de3 MC |
936 | /* A -= K */ |
937 | ctx->flags |= SEEN_A; | |
938 | emit_addiu(r_A, r_A, -k, ctx); | |
939 | break; | |
a83d081e | 940 | case BPF_ALU | BPF_SUB | BPF_X: |
c6610de3 MC |
941 | /* A -= X */ |
942 | ctx->flags |= SEEN_A | SEEN_X; | |
943 | emit_subu(r_A, r_A, r_X, ctx); | |
944 | break; | |
a83d081e | 945 | case BPF_ALU | BPF_MUL | BPF_K: |
c6610de3 MC |
946 | /* A *= K */ |
947 | /* Load K to scratch register before MUL */ | |
948 | ctx->flags |= SEEN_A | SEEN_S0; | |
949 | emit_load_imm(r_s0, k, ctx); | |
950 | emit_mul(r_A, r_A, r_s0, ctx); | |
951 | break; | |
a83d081e | 952 | case BPF_ALU | BPF_MUL | BPF_X: |
c6610de3 MC |
953 | /* A *= X */ |
954 | update_on_xread(ctx); | |
955 | ctx->flags |= SEEN_A | SEEN_X; | |
956 | emit_mul(r_A, r_A, r_X, ctx); | |
957 | break; | |
a83d081e | 958 | case BPF_ALU | BPF_DIV | BPF_K: |
c6610de3 MC |
959 | /* A /= k */ |
960 | if (k == 1) | |
961 | break; | |
962 | if (optimize_div(&k)) { | |
963 | ctx->flags |= SEEN_A; | |
964 | emit_srl(r_A, r_A, k, ctx); | |
965 | break; | |
966 | } | |
967 | ctx->flags |= SEEN_A | SEEN_S0; | |
968 | emit_load_imm(r_s0, k, ctx); | |
969 | emit_div(r_A, r_s0, ctx); | |
970 | break; | |
a83d081e | 971 | case BPF_ALU | BPF_MOD | BPF_K: |
c6610de3 MC |
972 | /* A %= k */ |
973 | if (k == 1 || optimize_div(&k)) { | |
974 | ctx->flags |= SEEN_A; | |
975 | emit_jit_reg_move(r_A, r_zero, ctx); | |
976 | } else { | |
977 | ctx->flags |= SEEN_A | SEEN_S0; | |
978 | emit_load_imm(r_s0, k, ctx); | |
979 | emit_mod(r_A, r_s0, ctx); | |
980 | } | |
981 | break; | |
a83d081e | 982 | case BPF_ALU | BPF_DIV | BPF_X: |
c6610de3 MC |
983 | /* A /= X */ |
984 | update_on_xread(ctx); | |
985 | ctx->flags |= SEEN_X | SEEN_A; | |
986 | /* Check if r_X is zero */ | |
987 | emit_bcond(MIPS_COND_EQ, r_X, r_zero, | |
988 | b_imm(prog->len, ctx), ctx); | |
989 | emit_load_imm(r_val, 0, ctx); /* delay slot */ | |
990 | emit_div(r_A, r_X, ctx); | |
991 | break; | |
a83d081e | 992 | case BPF_ALU | BPF_MOD | BPF_X: |
c6610de3 MC |
993 | /* A %= X */ |
994 | update_on_xread(ctx); | |
995 | ctx->flags |= SEEN_X | SEEN_A; | |
996 | /* Check if r_X is zero */ | |
997 | emit_bcond(MIPS_COND_EQ, r_X, r_zero, | |
998 | b_imm(prog->len, ctx), ctx); | |
999 | emit_load_imm(r_val, 0, ctx); /* delay slot */ | |
1000 | emit_mod(r_A, r_X, ctx); | |
1001 | break; | |
a83d081e | 1002 | case BPF_ALU | BPF_OR | BPF_K: |
c6610de3 MC |
1003 | /* A |= K */ |
1004 | ctx->flags |= SEEN_A; | |
1005 | emit_ori(r_A, r_A, k, ctx); | |
1006 | break; | |
a83d081e | 1007 | case BPF_ALU | BPF_OR | BPF_X: |
c6610de3 MC |
1008 | /* A |= X */ |
1009 | update_on_xread(ctx); | |
1010 | ctx->flags |= SEEN_A; | |
1011 | emit_ori(r_A, r_A, r_X, ctx); | |
1012 | break; | |
a83d081e | 1013 | case BPF_ALU | BPF_XOR | BPF_K: |
c6610de3 MC |
1014 | /* A ^= k */ |
1015 | ctx->flags |= SEEN_A; | |
1016 | emit_xori(r_A, r_A, k, ctx); | |
1017 | break; | |
a83d081e DB |
1018 | case BPF_ANC | SKF_AD_ALU_XOR_X: |
1019 | case BPF_ALU | BPF_XOR | BPF_X: | |
c6610de3 MC |
1020 | /* A ^= X */ |
1021 | update_on_xread(ctx); | |
1022 | ctx->flags |= SEEN_A; | |
1023 | emit_xor(r_A, r_A, r_X, ctx); | |
1024 | break; | |
a83d081e | 1025 | case BPF_ALU | BPF_AND | BPF_K: |
c6610de3 MC |
1026 | /* A &= K */ |
1027 | ctx->flags |= SEEN_A; | |
1028 | emit_andi(r_A, r_A, k, ctx); | |
1029 | break; | |
a83d081e | 1030 | case BPF_ALU | BPF_AND | BPF_X: |
c6610de3 MC |
1031 | /* A &= X */ |
1032 | update_on_xread(ctx); | |
1033 | ctx->flags |= SEEN_A | SEEN_X; | |
1034 | emit_and(r_A, r_A, r_X, ctx); | |
1035 | break; | |
a83d081e | 1036 | case BPF_ALU | BPF_LSH | BPF_K: |
c6610de3 MC |
1037 | /* A <<= K */ |
1038 | ctx->flags |= SEEN_A; | |
1039 | emit_sll(r_A, r_A, k, ctx); | |
1040 | break; | |
a83d081e | 1041 | case BPF_ALU | BPF_LSH | BPF_X: |
c6610de3 MC |
1042 | /* A <<= X */ |
1043 | ctx->flags |= SEEN_A | SEEN_X; | |
1044 | update_on_xread(ctx); | |
1045 | emit_sllv(r_A, r_A, r_X, ctx); | |
1046 | break; | |
a83d081e | 1047 | case BPF_ALU | BPF_RSH | BPF_K: |
c6610de3 MC |
1048 | /* A >>= K */ |
1049 | ctx->flags |= SEEN_A; | |
1050 | emit_srl(r_A, r_A, k, ctx); | |
1051 | break; | |
a83d081e | 1052 | case BPF_ALU | BPF_RSH | BPF_X: |
c6610de3 MC |
1053 | ctx->flags |= SEEN_A | SEEN_X; |
1054 | update_on_xread(ctx); | |
1055 | emit_srlv(r_A, r_A, r_X, ctx); | |
1056 | break; | |
a83d081e | 1057 | case BPF_ALU | BPF_NEG: |
c6610de3 MC |
1058 | /* A = -A */ |
1059 | ctx->flags |= SEEN_A; | |
1060 | emit_neg(r_A, ctx); | |
1061 | break; | |
a83d081e | 1062 | case BPF_JMP | BPF_JA: |
c6610de3 MC |
1063 | /* pc += K */ |
1064 | emit_b(b_imm(i + k + 1, ctx), ctx); | |
1065 | emit_nop(ctx); | |
1066 | break; | |
a83d081e | 1067 | case BPF_JMP | BPF_JEQ | BPF_K: |
c6610de3 MC |
1068 | /* pc += ( A == K ) ? pc->jt : pc->jf */ |
1069 | condt = MIPS_COND_EQ | MIPS_COND_K; | |
1070 | goto jmp_cmp; | |
a83d081e | 1071 | case BPF_JMP | BPF_JEQ | BPF_X: |
c6610de3 MC |
1072 | ctx->flags |= SEEN_X; |
1073 | /* pc += ( A == X ) ? pc->jt : pc->jf */ | |
1074 | condt = MIPS_COND_EQ | MIPS_COND_X; | |
1075 | goto jmp_cmp; | |
a83d081e | 1076 | case BPF_JMP | BPF_JGE | BPF_K: |
c6610de3 MC |
1077 | /* pc += ( A >= K ) ? pc->jt : pc->jf */ |
1078 | condt = MIPS_COND_GE | MIPS_COND_K; | |
1079 | goto jmp_cmp; | |
a83d081e | 1080 | case BPF_JMP | BPF_JGE | BPF_X: |
c6610de3 MC |
1081 | ctx->flags |= SEEN_X; |
1082 | /* pc += ( A >= X ) ? pc->jt : pc->jf */ | |
1083 | condt = MIPS_COND_GE | MIPS_COND_X; | |
1084 | goto jmp_cmp; | |
a83d081e | 1085 | case BPF_JMP | BPF_JGT | BPF_K: |
c6610de3 MC |
1086 | /* pc += ( A > K ) ? pc->jt : pc->jf */ |
1087 | condt = MIPS_COND_GT | MIPS_COND_K; | |
1088 | goto jmp_cmp; | |
a83d081e | 1089 | case BPF_JMP | BPF_JGT | BPF_X: |
c6610de3 MC |
1090 | ctx->flags |= SEEN_X; |
1091 | /* pc += ( A > X ) ? pc->jt : pc->jf */ | |
1092 | condt = MIPS_COND_GT | MIPS_COND_X; | |
1093 | jmp_cmp: | |
1094 | /* Greater or Equal */ | |
1095 | if ((condt & MIPS_COND_GE) || | |
1096 | (condt & MIPS_COND_GT)) { | |
1097 | if (condt & MIPS_COND_K) { /* K */ | |
1098 | ctx->flags |= SEEN_S0 | SEEN_A; | |
1099 | emit_sltiu(r_s0, r_A, k, ctx); | |
1100 | } else { /* X */ | |
1101 | ctx->flags |= SEEN_S0 | SEEN_A | | |
1102 | SEEN_X; | |
1103 | emit_sltu(r_s0, r_A, r_X, ctx); | |
1104 | } | |
1105 | /* A < (K|X) ? r_scrach = 1 */ | |
1106 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1107 | emit_bcond(MIPS_COND_GT, r_s0, r_zero, b_off, | |
1108 | ctx); | |
1109 | emit_nop(ctx); | |
1110 | /* A > (K|X) ? scratch = 0 */ | |
1111 | if (condt & MIPS_COND_GT) { | |
1112 | /* Checking for equality */ | |
1113 | ctx->flags |= SEEN_S0 | SEEN_A | SEEN_X; | |
1114 | if (condt & MIPS_COND_K) | |
1115 | emit_load_imm(r_s0, k, ctx); | |
1116 | else | |
1117 | emit_jit_reg_move(r_s0, r_X, | |
1118 | ctx); | |
1119 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1120 | emit_bcond(MIPS_COND_EQ, r_A, r_s0, | |
1121 | b_off, ctx); | |
1122 | emit_nop(ctx); | |
1123 | /* Finally, A > K|X */ | |
1124 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1125 | emit_b(b_off, ctx); | |
1126 | emit_nop(ctx); | |
1127 | } else { | |
1128 | /* A >= (K|X) so jump */ | |
1129 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1130 | emit_b(b_off, ctx); | |
1131 | emit_nop(ctx); | |
1132 | } | |
1133 | } else { | |
1134 | /* A == K|X */ | |
1135 | if (condt & MIPS_COND_K) { /* K */ | |
1136 | ctx->flags |= SEEN_S0 | SEEN_A; | |
1137 | emit_load_imm(r_s0, k, ctx); | |
1138 | /* jump true */ | |
1139 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1140 | emit_bcond(MIPS_COND_EQ, r_A, r_s0, | |
1141 | b_off, ctx); | |
1142 | emit_nop(ctx); | |
1143 | /* jump false */ | |
1144 | b_off = b_imm(i + inst->jf + 1, | |
1145 | ctx); | |
1146 | emit_bcond(MIPS_COND_NE, r_A, r_s0, | |
1147 | b_off, ctx); | |
1148 | emit_nop(ctx); | |
1149 | } else { /* X */ | |
1150 | /* jump true */ | |
1151 | ctx->flags |= SEEN_A | SEEN_X; | |
1152 | b_off = b_imm(i + inst->jt + 1, | |
1153 | ctx); | |
1154 | emit_bcond(MIPS_COND_EQ, r_A, r_X, | |
1155 | b_off, ctx); | |
1156 | emit_nop(ctx); | |
1157 | /* jump false */ | |
1158 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1159 | emit_bcond(MIPS_COND_NE, r_A, r_X, | |
1160 | b_off, ctx); | |
1161 | emit_nop(ctx); | |
1162 | } | |
1163 | } | |
1164 | break; | |
a83d081e | 1165 | case BPF_JMP | BPF_JSET | BPF_K: |
c6610de3 MC |
1166 | ctx->flags |= SEEN_S0 | SEEN_S1 | SEEN_A; |
1167 | /* pc += (A & K) ? pc -> jt : pc -> jf */ | |
1168 | emit_load_imm(r_s1, k, ctx); | |
1169 | emit_and(r_s0, r_A, r_s1, ctx); | |
1170 | /* jump true */ | |
1171 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1172 | emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx); | |
1173 | emit_nop(ctx); | |
1174 | /* jump false */ | |
1175 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1176 | emit_b(b_off, ctx); | |
1177 | emit_nop(ctx); | |
1178 | break; | |
a83d081e | 1179 | case BPF_JMP | BPF_JSET | BPF_X: |
c6610de3 MC |
1180 | ctx->flags |= SEEN_S0 | SEEN_X | SEEN_A; |
1181 | /* pc += (A & X) ? pc -> jt : pc -> jf */ | |
1182 | emit_and(r_s0, r_A, r_X, ctx); | |
1183 | /* jump true */ | |
1184 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1185 | emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx); | |
1186 | emit_nop(ctx); | |
1187 | /* jump false */ | |
1188 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1189 | emit_b(b_off, ctx); | |
1190 | emit_nop(ctx); | |
1191 | break; | |
a83d081e | 1192 | case BPF_RET | BPF_A: |
c6610de3 MC |
1193 | ctx->flags |= SEEN_A; |
1194 | if (i != prog->len - 1) | |
1195 | /* | |
1196 | * If this is not the last instruction | |
1197 | * then jump to the epilogue | |
1198 | */ | |
1199 | emit_b(b_imm(prog->len, ctx), ctx); | |
1200 | emit_reg_move(r_ret, r_A, ctx); /* delay slot */ | |
1201 | break; | |
a83d081e | 1202 | case BPF_RET | BPF_K: |
c6610de3 MC |
1203 | /* |
1204 | * It can emit two instructions so it does not fit on | |
1205 | * the delay slot. | |
1206 | */ | |
1207 | emit_load_imm(r_ret, k, ctx); | |
1208 | if (i != prog->len - 1) { | |
1209 | /* | |
1210 | * If this is not the last instruction | |
1211 | * then jump to the epilogue | |
1212 | */ | |
1213 | emit_b(b_imm(prog->len, ctx), ctx); | |
1214 | emit_nop(ctx); | |
1215 | } | |
1216 | break; | |
a83d081e | 1217 | case BPF_MISC | BPF_TAX: |
c6610de3 MC |
1218 | /* X = A */ |
1219 | ctx->flags |= SEEN_X | SEEN_A; | |
1220 | emit_jit_reg_move(r_X, r_A, ctx); | |
1221 | break; | |
a83d081e | 1222 | case BPF_MISC | BPF_TXA: |
c6610de3 MC |
1223 | /* A = X */ |
1224 | ctx->flags |= SEEN_A | SEEN_X; | |
1225 | update_on_xread(ctx); | |
1226 | emit_jit_reg_move(r_A, r_X, ctx); | |
1227 | break; | |
1228 | /* AUX */ | |
a83d081e | 1229 | case BPF_ANC | SKF_AD_PROTOCOL: |
c6610de3 MC |
1230 | /* A = ntohs(skb->protocol */ |
1231 | ctx->flags |= SEEN_SKB | SEEN_OFF | SEEN_A; | |
1232 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, | |
1233 | protocol) != 2); | |
1234 | off = offsetof(struct sk_buff, protocol); | |
1235 | emit_half_load(r_A, r_skb, off, ctx); | |
1236 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
1237 | /* This needs little endian fixup */ | |
b4f16c93 RB |
1238 | if (cpu_has_mips_r2) { |
1239 | /* R2 and later have the wsbh instruction */ | |
1240 | emit_wsbh(r_A, r_A, ctx); | |
1241 | } else { | |
c6610de3 MC |
1242 | /* Get first byte */ |
1243 | emit_andi(r_tmp_imm, r_A, 0xff, ctx); | |
1244 | /* Shift it */ | |
1245 | emit_sll(r_tmp, r_tmp_imm, 8, ctx); | |
1246 | /* Get second byte */ | |
1247 | emit_srl(r_tmp_imm, r_A, 8, ctx); | |
1248 | emit_andi(r_tmp_imm, r_tmp_imm, 0xff, ctx); | |
1249 | /* Put everyting together in r_A */ | |
1250 | emit_or(r_A, r_tmp, r_tmp_imm, ctx); | |
c6610de3 MC |
1251 | } |
1252 | #endif | |
1253 | break; | |
a83d081e | 1254 | case BPF_ANC | SKF_AD_CPU: |
c6610de3 MC |
1255 | ctx->flags |= SEEN_A | SEEN_OFF; |
1256 | /* A = current_thread_info()->cpu */ | |
1257 | BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info, | |
1258 | cpu) != 4); | |
1259 | off = offsetof(struct thread_info, cpu); | |
1260 | /* $28/gp points to the thread_info struct */ | |
1261 | emit_load(r_A, 28, off, ctx); | |
1262 | break; | |
a83d081e | 1263 | case BPF_ANC | SKF_AD_IFINDEX: |
c6610de3 MC |
1264 | /* A = skb->dev->ifindex */ |
1265 | ctx->flags |= SEEN_SKB | SEEN_A | SEEN_S0; | |
1266 | off = offsetof(struct sk_buff, dev); | |
1267 | emit_load(r_s0, r_skb, off, ctx); | |
1268 | /* error (0) in the delay slot */ | |
1269 | emit_bcond(MIPS_COND_EQ, r_s0, r_zero, | |
1270 | b_imm(prog->len, ctx), ctx); | |
1271 | emit_reg_move(r_ret, r_zero, ctx); | |
1272 | BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, | |
1273 | ifindex) != 4); | |
1274 | off = offsetof(struct net_device, ifindex); | |
1275 | emit_load(r_A, r_s0, off, ctx); | |
1276 | break; | |
a83d081e | 1277 | case BPF_ANC | SKF_AD_MARK: |
c6610de3 MC |
1278 | ctx->flags |= SEEN_SKB | SEEN_A; |
1279 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4); | |
1280 | off = offsetof(struct sk_buff, mark); | |
1281 | emit_load(r_A, r_skb, off, ctx); | |
1282 | break; | |
a83d081e | 1283 | case BPF_ANC | SKF_AD_RXHASH: |
c6610de3 MC |
1284 | ctx->flags |= SEEN_SKB | SEEN_A; |
1285 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4); | |
1286 | off = offsetof(struct sk_buff, hash); | |
1287 | emit_load(r_A, r_skb, off, ctx); | |
1288 | break; | |
a83d081e DB |
1289 | case BPF_ANC | SKF_AD_VLAN_TAG: |
1290 | case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT: | |
c6610de3 MC |
1291 | ctx->flags |= SEEN_SKB | SEEN_S0 | SEEN_A; |
1292 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, | |
1293 | vlan_tci) != 2); | |
1294 | off = offsetof(struct sk_buff, vlan_tci); | |
1295 | emit_half_load(r_s0, r_skb, off, ctx); | |
a83d081e | 1296 | if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) |
c6610de3 MC |
1297 | emit_and(r_A, r_s0, VLAN_VID_MASK, ctx); |
1298 | else | |
1299 | emit_and(r_A, r_s0, VLAN_TAG_PRESENT, ctx); | |
1300 | break; | |
a83d081e | 1301 | case BPF_ANC | SKF_AD_PKTTYPE: |
c6610de3 MC |
1302 | off = pkt_type_offset(); |
1303 | ||
1304 | if (off < 0) | |
1305 | return -1; | |
1306 | emit_load_byte(r_tmp, r_skb, off, ctx); | |
1307 | /* Keep only the last 3 bits */ | |
1308 | emit_andi(r_A, r_tmp, PKT_TYPE_MAX, ctx); | |
1309 | break; | |
a83d081e | 1310 | case BPF_ANC | SKF_AD_QUEUE: |
c6610de3 MC |
1311 | ctx->flags |= SEEN_SKB | SEEN_A; |
1312 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, | |
1313 | queue_mapping) != 2); | |
1314 | BUILD_BUG_ON(offsetof(struct sk_buff, | |
1315 | queue_mapping) > 0xff); | |
1316 | off = offsetof(struct sk_buff, queue_mapping); | |
1317 | emit_half_load(r_A, r_skb, off, ctx); | |
1318 | break; | |
1319 | default: | |
1320 | pr_warn("%s: Unhandled opcode: 0x%02x\n", __FILE__, | |
1321 | inst->code); | |
1322 | return -1; | |
1323 | } | |
1324 | } | |
1325 | ||
1326 | /* compute offsets only during the first pass */ | |
1327 | if (ctx->target == NULL) | |
1328 | ctx->offsets[i] = ctx->idx * 4; | |
1329 | ||
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | int bpf_jit_enable __read_mostly; | |
1334 | ||
1335 | void bpf_jit_compile(struct sk_filter *fp) | |
1336 | { | |
1337 | struct jit_ctx ctx; | |
1338 | unsigned int alloc_size, tmp_idx; | |
1339 | ||
1340 | if (!bpf_jit_enable) | |
1341 | return; | |
1342 | ||
1343 | memset(&ctx, 0, sizeof(ctx)); | |
1344 | ||
1345 | ctx.offsets = kcalloc(fp->len, sizeof(*ctx.offsets), GFP_KERNEL); | |
1346 | if (ctx.offsets == NULL) | |
1347 | return; | |
1348 | ||
1349 | ctx.skf = fp; | |
1350 | ||
1351 | if (build_body(&ctx)) | |
1352 | goto out; | |
1353 | ||
1354 | tmp_idx = ctx.idx; | |
1355 | build_prologue(&ctx); | |
1356 | ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4; | |
1357 | /* just to complete the ctx.idx count */ | |
1358 | build_epilogue(&ctx); | |
1359 | ||
1360 | alloc_size = 4 * ctx.idx; | |
1361 | ctx.target = module_alloc(alloc_size); | |
1362 | if (ctx.target == NULL) | |
1363 | goto out; | |
1364 | ||
1365 | /* Clean it */ | |
1366 | memset(ctx.target, 0, alloc_size); | |
1367 | ||
1368 | ctx.idx = 0; | |
1369 | ||
1370 | /* Generate the actual JIT code */ | |
1371 | build_prologue(&ctx); | |
1372 | build_body(&ctx); | |
1373 | build_epilogue(&ctx); | |
1374 | ||
1375 | /* Update the icache */ | |
1376 | flush_icache_range((ptr)ctx.target, (ptr)(ctx.target + ctx.idx)); | |
1377 | ||
1378 | if (bpf_jit_enable > 1) | |
1379 | /* Dump JIT code */ | |
1380 | bpf_jit_dump(fp->len, alloc_size, 2, ctx.target); | |
1381 | ||
1382 | fp->bpf_func = (void *)ctx.target; | |
1383 | fp->jited = 1; | |
1384 | ||
1385 | out: | |
1386 | kfree(ctx.offsets); | |
1387 | } | |
1388 | ||
1389 | void bpf_jit_free(struct sk_filter *fp) | |
1390 | { | |
1391 | if (fp->jited) | |
1392 | module_free(NULL, fp->bpf_func); | |
1393 | kfree(fp); | |
1394 | } |