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c6610de3 MC |
1 | /* |
2 | * Just-In-Time compiler for BPF filters on MIPS | |
3 | * | |
4 | * Copyright (c) 2014 Imagination Technologies Ltd. | |
5 | * Author: Markos Chandras <markos.chandras@imgtec.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; version 2 of the License. | |
10 | */ | |
11 | ||
12 | #include <linux/bitops.h> | |
13 | #include <linux/compiler.h> | |
14 | #include <linux/errno.h> | |
15 | #include <linux/filter.h> | |
16 | #include <linux/if_vlan.h> | |
17 | #include <linux/kconfig.h> | |
18 | #include <linux/moduleloader.h> | |
19 | #include <linux/netdevice.h> | |
20 | #include <linux/string.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/types.h> | |
23 | #include <asm/bitops.h> | |
24 | #include <asm/cacheflush.h> | |
25 | #include <asm/cpu-features.h> | |
26 | #include <asm/uasm.h> | |
27 | ||
28 | #include "bpf_jit.h" | |
29 | ||
30 | /* ABI | |
31 | * | |
32 | * s0 1st scratch register | |
33 | * s1 2nd scratch register | |
34 | * s2 offset register | |
35 | * s3 BPF register A | |
36 | * s4 BPF register X | |
37 | * s5 *skb | |
38 | * s6 *scratch memory | |
39 | * | |
40 | * On entry (*bpf_func)(*skb, *filter) | |
41 | * a0 = MIPS_R_A0 = skb; | |
42 | * a1 = MIPS_R_A1 = filter; | |
43 | * | |
44 | * Stack | |
45 | * ... | |
46 | * M[15] | |
47 | * M[14] | |
48 | * M[13] | |
49 | * ... | |
50 | * M[0] <-- r_M | |
51 | * saved reg k-1 | |
52 | * saved reg k-2 | |
53 | * ... | |
54 | * saved reg 0 <-- r_sp | |
55 | * <no argument area> | |
56 | * | |
57 | * Packet layout | |
58 | * | |
59 | * <--------------------- len ------------------------> | |
60 | * <--skb-len(r_skb_hl)-->< ----- skb->data_len ------> | |
61 | * ---------------------------------------------------- | |
62 | * | skb->data | | |
63 | * ---------------------------------------------------- | |
64 | */ | |
65 | ||
66 | #define RSIZE (sizeof(unsigned long)) | |
67 | #define ptr typeof(unsigned long) | |
68 | ||
69 | /* ABI specific return values */ | |
70 | #ifdef CONFIG_32BIT /* O32 */ | |
71 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
72 | #define r_err MIPS_R_V1 | |
73 | #define r_val MIPS_R_V0 | |
74 | #else /* CONFIG_CPU_LITTLE_ENDIAN */ | |
75 | #define r_err MIPS_R_V0 | |
76 | #define r_val MIPS_R_V1 | |
77 | #endif | |
78 | #else /* N64 */ | |
79 | #define r_err MIPS_R_V0 | |
80 | #define r_val MIPS_R_V0 | |
81 | #endif | |
82 | ||
83 | #define r_ret MIPS_R_V0 | |
84 | ||
85 | /* | |
86 | * Use 2 scratch registers to avoid pipeline interlocks. | |
87 | * There is no overhead during epilogue and prologue since | |
88 | * any of the $s0-$s6 registers will only be preserved if | |
89 | * they are going to actually be used. | |
90 | */ | |
91 | #define r_s0 MIPS_R_S0 /* scratch reg 1 */ | |
92 | #define r_s1 MIPS_R_S1 /* scratch reg 2 */ | |
93 | #define r_off MIPS_R_S2 | |
94 | #define r_A MIPS_R_S3 | |
95 | #define r_X MIPS_R_S4 | |
96 | #define r_skb MIPS_R_S5 | |
97 | #define r_M MIPS_R_S6 | |
98 | #define r_tmp_imm MIPS_R_T6 /* No need to preserve this */ | |
99 | #define r_tmp MIPS_R_T7 /* No need to preserve this */ | |
100 | #define r_zero MIPS_R_ZERO | |
101 | #define r_sp MIPS_R_SP | |
102 | #define r_ra MIPS_R_RA | |
103 | ||
104 | #define SCRATCH_OFF(k) (4 * (k)) | |
105 | ||
106 | /* JIT flags */ | |
107 | #define SEEN_CALL (1 << BPF_MEMWORDS) | |
108 | #define SEEN_SREG_SFT (BPF_MEMWORDS + 1) | |
109 | #define SEEN_SREG_BASE (1 << SEEN_SREG_SFT) | |
110 | #define SEEN_SREG(x) (SEEN_SREG_BASE << (x)) | |
111 | #define SEEN_S0 SEEN_SREG(0) | |
112 | #define SEEN_S1 SEEN_SREG(1) | |
113 | #define SEEN_OFF SEEN_SREG(2) | |
114 | #define SEEN_A SEEN_SREG(3) | |
115 | #define SEEN_X SEEN_SREG(4) | |
116 | #define SEEN_SKB SEEN_SREG(5) | |
117 | #define SEEN_MEM SEEN_SREG(6) | |
118 | ||
119 | /* Arguments used by JIT */ | |
120 | #define ARGS_USED_BY_JIT 2 /* only applicable to 64-bit */ | |
121 | ||
122 | #define FLAG_NEED_X_RESET (1 << 0) | |
123 | ||
124 | #define SBIT(x) (1 << (x)) /* Signed version of BIT() */ | |
125 | ||
126 | /** | |
127 | * struct jit_ctx - JIT context | |
128 | * @skf: The sk_filter | |
129 | * @prologue_bytes: Number of bytes for prologue | |
130 | * @idx: Instruction index | |
131 | * @flags: JIT flags | |
132 | * @offsets: Instruction offsets | |
133 | * @target: Memory location for the compiled filter | |
134 | */ | |
135 | struct jit_ctx { | |
136 | const struct sk_filter *skf; | |
137 | unsigned int prologue_bytes; | |
138 | u32 idx; | |
139 | u32 flags; | |
140 | u32 *offsets; | |
141 | u32 *target; | |
142 | }; | |
143 | ||
144 | ||
145 | static inline int optimize_div(u32 *k) | |
146 | { | |
147 | /* power of 2 divides can be implemented with right shift */ | |
148 | if (!(*k & (*k-1))) { | |
149 | *k = ilog2(*k); | |
150 | return 1; | |
151 | } | |
152 | ||
153 | return 0; | |
154 | } | |
155 | ||
156 | /* Simply emit the instruction if the JIT memory space has been allocated */ | |
157 | #define emit_instr(ctx, func, ...) \ | |
158 | do { \ | |
159 | if ((ctx)->target != NULL) { \ | |
160 | u32 *p = &(ctx)->target[ctx->idx]; \ | |
161 | uasm_i_##func(&p, ##__VA_ARGS__); \ | |
162 | } \ | |
163 | (ctx)->idx++; \ | |
164 | } while (0) | |
165 | ||
166 | /* Determine if immediate is within the 16-bit signed range */ | |
167 | static inline bool is_range16(s32 imm) | |
168 | { | |
169 | if (imm >= SBIT(15) || imm < -SBIT(15)) | |
170 | return true; | |
171 | return false; | |
172 | } | |
173 | ||
174 | static inline void emit_addu(unsigned int dst, unsigned int src1, | |
175 | unsigned int src2, struct jit_ctx *ctx) | |
176 | { | |
177 | emit_instr(ctx, addu, dst, src1, src2); | |
178 | } | |
179 | ||
180 | static inline void emit_nop(struct jit_ctx *ctx) | |
181 | { | |
182 | emit_instr(ctx, nop); | |
183 | } | |
184 | ||
185 | /* Load a u32 immediate to a register */ | |
186 | static inline void emit_load_imm(unsigned int dst, u32 imm, struct jit_ctx *ctx) | |
187 | { | |
188 | if (ctx->target != NULL) { | |
189 | /* addiu can only handle s16 */ | |
190 | if (is_range16(imm)) { | |
191 | u32 *p = &ctx->target[ctx->idx]; | |
192 | uasm_i_lui(&p, r_tmp_imm, (s32)imm >> 16); | |
193 | p = &ctx->target[ctx->idx + 1]; | |
194 | uasm_i_ori(&p, dst, r_tmp_imm, imm & 0xffff); | |
195 | } else { | |
196 | u32 *p = &ctx->target[ctx->idx]; | |
197 | uasm_i_addiu(&p, dst, r_zero, imm); | |
198 | } | |
199 | } | |
200 | ctx->idx++; | |
201 | ||
202 | if (is_range16(imm)) | |
203 | ctx->idx++; | |
204 | } | |
205 | ||
206 | static inline void emit_or(unsigned int dst, unsigned int src1, | |
207 | unsigned int src2, struct jit_ctx *ctx) | |
208 | { | |
209 | emit_instr(ctx, or, dst, src1, src2); | |
210 | } | |
211 | ||
212 | static inline void emit_ori(unsigned int dst, unsigned src, u32 imm, | |
213 | struct jit_ctx *ctx) | |
214 | { | |
215 | if (imm >= BIT(16)) { | |
216 | emit_load_imm(r_tmp, imm, ctx); | |
217 | emit_or(dst, src, r_tmp, ctx); | |
218 | } else { | |
219 | emit_instr(ctx, ori, dst, src, imm); | |
220 | } | |
221 | } | |
222 | ||
223 | ||
224 | static inline void emit_daddu(unsigned int dst, unsigned int src1, | |
225 | unsigned int src2, struct jit_ctx *ctx) | |
226 | { | |
227 | emit_instr(ctx, daddu, dst, src1, src2); | |
228 | } | |
229 | ||
230 | static inline void emit_daddiu(unsigned int dst, unsigned int src, | |
231 | int imm, struct jit_ctx *ctx) | |
232 | { | |
233 | /* | |
234 | * Only used for stack, so the imm is relatively small | |
235 | * and it fits in 15-bits | |
236 | */ | |
237 | emit_instr(ctx, daddiu, dst, src, imm); | |
238 | } | |
239 | ||
240 | static inline void emit_addiu(unsigned int dst, unsigned int src, | |
241 | u32 imm, struct jit_ctx *ctx) | |
242 | { | |
243 | if (is_range16(imm)) { | |
244 | emit_load_imm(r_tmp, imm, ctx); | |
245 | emit_addu(dst, r_tmp, src, ctx); | |
246 | } else { | |
247 | emit_instr(ctx, addiu, dst, src, imm); | |
248 | } | |
249 | } | |
250 | ||
251 | static inline void emit_and(unsigned int dst, unsigned int src1, | |
252 | unsigned int src2, struct jit_ctx *ctx) | |
253 | { | |
254 | emit_instr(ctx, and, dst, src1, src2); | |
255 | } | |
256 | ||
257 | static inline void emit_andi(unsigned int dst, unsigned int src, | |
258 | u32 imm, struct jit_ctx *ctx) | |
259 | { | |
260 | /* If imm does not fit in u16 then load it to register */ | |
261 | if (imm >= BIT(16)) { | |
262 | emit_load_imm(r_tmp, imm, ctx); | |
263 | emit_and(dst, src, r_tmp, ctx); | |
264 | } else { | |
265 | emit_instr(ctx, andi, dst, src, imm); | |
266 | } | |
267 | } | |
268 | ||
269 | static inline void emit_xor(unsigned int dst, unsigned int src1, | |
270 | unsigned int src2, struct jit_ctx *ctx) | |
271 | { | |
272 | emit_instr(ctx, xor, dst, src1, src2); | |
273 | } | |
274 | ||
275 | static inline void emit_xori(ptr dst, ptr src, u32 imm, struct jit_ctx *ctx) | |
276 | { | |
277 | /* If imm does not fit in u16 then load it to register */ | |
278 | if (imm >= BIT(16)) { | |
279 | emit_load_imm(r_tmp, imm, ctx); | |
280 | emit_xor(dst, src, r_tmp, ctx); | |
281 | } else { | |
282 | emit_instr(ctx, xori, dst, src, imm); | |
283 | } | |
284 | } | |
285 | ||
286 | static inline void emit_stack_offset(int offset, struct jit_ctx *ctx) | |
287 | { | |
288 | if (config_enabled(CONFIG_64BIT)) | |
289 | emit_instr(ctx, daddiu, r_sp, r_sp, offset); | |
290 | else | |
291 | emit_instr(ctx, addiu, r_sp, r_sp, offset); | |
292 | ||
293 | } | |
294 | ||
295 | static inline void emit_subu(unsigned int dst, unsigned int src1, | |
296 | unsigned int src2, struct jit_ctx *ctx) | |
297 | { | |
298 | emit_instr(ctx, subu, dst, src1, src2); | |
299 | } | |
300 | ||
301 | static inline void emit_neg(unsigned int reg, struct jit_ctx *ctx) | |
302 | { | |
303 | emit_subu(reg, r_zero, reg, ctx); | |
304 | } | |
305 | ||
306 | static inline void emit_sllv(unsigned int dst, unsigned int src, | |
307 | unsigned int sa, struct jit_ctx *ctx) | |
308 | { | |
309 | emit_instr(ctx, sllv, dst, src, sa); | |
310 | } | |
311 | ||
312 | static inline void emit_sll(unsigned int dst, unsigned int src, | |
313 | unsigned int sa, struct jit_ctx *ctx) | |
314 | { | |
315 | /* sa is 5-bits long */ | |
316 | BUG_ON(sa >= BIT(5)); | |
317 | emit_instr(ctx, sll, dst, src, sa); | |
318 | } | |
319 | ||
320 | static inline void emit_srlv(unsigned int dst, unsigned int src, | |
321 | unsigned int sa, struct jit_ctx *ctx) | |
322 | { | |
323 | emit_instr(ctx, srlv, dst, src, sa); | |
324 | } | |
325 | ||
326 | static inline void emit_srl(unsigned int dst, unsigned int src, | |
327 | unsigned int sa, struct jit_ctx *ctx) | |
328 | { | |
329 | /* sa is 5-bits long */ | |
330 | BUG_ON(sa >= BIT(5)); | |
331 | emit_instr(ctx, srl, dst, src, sa); | |
332 | } | |
333 | ||
55393ee5 MC |
334 | static inline void emit_slt(unsigned int dst, unsigned int src1, |
335 | unsigned int src2, struct jit_ctx *ctx) | |
336 | { | |
337 | emit_instr(ctx, slt, dst, src1, src2); | |
338 | } | |
339 | ||
c6610de3 MC |
340 | static inline void emit_sltu(unsigned int dst, unsigned int src1, |
341 | unsigned int src2, struct jit_ctx *ctx) | |
342 | { | |
343 | emit_instr(ctx, sltu, dst, src1, src2); | |
344 | } | |
345 | ||
346 | static inline void emit_sltiu(unsigned dst, unsigned int src, | |
347 | unsigned int imm, struct jit_ctx *ctx) | |
348 | { | |
349 | /* 16 bit immediate */ | |
350 | if (is_range16((s32)imm)) { | |
351 | emit_load_imm(r_tmp, imm, ctx); | |
352 | emit_sltu(dst, src, r_tmp, ctx); | |
353 | } else { | |
354 | emit_instr(ctx, sltiu, dst, src, imm); | |
355 | } | |
356 | ||
357 | } | |
358 | ||
359 | /* Store register on the stack */ | |
360 | static inline void emit_store_stack_reg(ptr reg, ptr base, | |
361 | unsigned int offset, | |
362 | struct jit_ctx *ctx) | |
363 | { | |
364 | if (config_enabled(CONFIG_64BIT)) | |
365 | emit_instr(ctx, sd, reg, offset, base); | |
366 | else | |
367 | emit_instr(ctx, sw, reg, offset, base); | |
368 | } | |
369 | ||
370 | static inline void emit_store(ptr reg, ptr base, unsigned int offset, | |
371 | struct jit_ctx *ctx) | |
372 | { | |
373 | emit_instr(ctx, sw, reg, offset, base); | |
374 | } | |
375 | ||
376 | static inline void emit_load_stack_reg(ptr reg, ptr base, | |
377 | unsigned int offset, | |
378 | struct jit_ctx *ctx) | |
379 | { | |
380 | if (config_enabled(CONFIG_64BIT)) | |
381 | emit_instr(ctx, ld, reg, offset, base); | |
382 | else | |
383 | emit_instr(ctx, lw, reg, offset, base); | |
384 | } | |
385 | ||
386 | static inline void emit_load(unsigned int reg, unsigned int base, | |
387 | unsigned int offset, struct jit_ctx *ctx) | |
388 | { | |
389 | emit_instr(ctx, lw, reg, offset, base); | |
390 | } | |
391 | ||
392 | static inline void emit_load_byte(unsigned int reg, unsigned int base, | |
393 | unsigned int offset, struct jit_ctx *ctx) | |
394 | { | |
395 | emit_instr(ctx, lb, reg, offset, base); | |
396 | } | |
397 | ||
398 | static inline void emit_half_load(unsigned int reg, unsigned int base, | |
399 | unsigned int offset, struct jit_ctx *ctx) | |
400 | { | |
401 | emit_instr(ctx, lh, reg, offset, base); | |
402 | } | |
403 | ||
404 | static inline void emit_mul(unsigned int dst, unsigned int src1, | |
405 | unsigned int src2, struct jit_ctx *ctx) | |
406 | { | |
407 | emit_instr(ctx, mul, dst, src1, src2); | |
408 | } | |
409 | ||
410 | static inline void emit_div(unsigned int dst, unsigned int src, | |
411 | struct jit_ctx *ctx) | |
412 | { | |
413 | if (ctx->target != NULL) { | |
414 | u32 *p = &ctx->target[ctx->idx]; | |
415 | uasm_i_divu(&p, dst, src); | |
416 | p = &ctx->target[ctx->idx + 1]; | |
35a8e16a | 417 | uasm_i_mflo(&p, dst); |
c6610de3 MC |
418 | } |
419 | ctx->idx += 2; /* 2 insts */ | |
420 | } | |
421 | ||
422 | static inline void emit_mod(unsigned int dst, unsigned int src, | |
423 | struct jit_ctx *ctx) | |
424 | { | |
425 | if (ctx->target != NULL) { | |
426 | u32 *p = &ctx->target[ctx->idx]; | |
427 | uasm_i_divu(&p, dst, src); | |
428 | p = &ctx->target[ctx->idx + 1]; | |
429 | uasm_i_mflo(&p, dst); | |
430 | } | |
431 | ctx->idx += 2; /* 2 insts */ | |
432 | } | |
433 | ||
434 | static inline void emit_dsll(unsigned int dst, unsigned int src, | |
435 | unsigned int sa, struct jit_ctx *ctx) | |
436 | { | |
437 | emit_instr(ctx, dsll, dst, src, sa); | |
438 | } | |
439 | ||
440 | static inline void emit_dsrl32(unsigned int dst, unsigned int src, | |
441 | unsigned int sa, struct jit_ctx *ctx) | |
442 | { | |
443 | emit_instr(ctx, dsrl32, dst, src, sa); | |
444 | } | |
445 | ||
446 | static inline void emit_wsbh(unsigned int dst, unsigned int src, | |
447 | struct jit_ctx *ctx) | |
448 | { | |
449 | emit_instr(ctx, wsbh, dst, src); | |
450 | } | |
451 | ||
452 | /* load a function pointer to register */ | |
453 | static inline void emit_load_func(unsigned int reg, ptr imm, | |
454 | struct jit_ctx *ctx) | |
455 | { | |
456 | if (config_enabled(CONFIG_64BIT)) { | |
457 | /* At this point imm is always 64-bit */ | |
458 | emit_load_imm(r_tmp, (u64)imm >> 32, ctx); | |
459 | emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */ | |
460 | emit_ori(r_tmp, r_tmp_imm, (imm >> 16) & 0xffff, ctx); | |
461 | emit_dsll(r_tmp_imm, r_tmp, 16, ctx); /* left shift by 16 */ | |
462 | emit_ori(reg, r_tmp_imm, imm & 0xffff, ctx); | |
463 | } else { | |
464 | emit_load_imm(reg, imm, ctx); | |
465 | } | |
466 | } | |
467 | ||
468 | /* Move to real MIPS register */ | |
469 | static inline void emit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx) | |
470 | { | |
471 | if (config_enabled(CONFIG_64BIT)) | |
472 | emit_daddu(dst, src, r_zero, ctx); | |
473 | else | |
474 | emit_addu(dst, src, r_zero, ctx); | |
475 | } | |
476 | ||
477 | /* Move to JIT (32-bit) register */ | |
478 | static inline void emit_jit_reg_move(ptr dst, ptr src, struct jit_ctx *ctx) | |
479 | { | |
480 | emit_addu(dst, src, r_zero, ctx); | |
481 | } | |
482 | ||
483 | /* Compute the immediate value for PC-relative branches. */ | |
484 | static inline u32 b_imm(unsigned int tgt, struct jit_ctx *ctx) | |
485 | { | |
486 | if (ctx->target == NULL) | |
487 | return 0; | |
488 | ||
489 | /* | |
490 | * We want a pc-relative branch. We only do forward branches | |
491 | * so tgt is always after pc. tgt is the instruction offset | |
492 | * we want to jump to. | |
493 | ||
494 | * Branch on MIPS: | |
495 | * I: target_offset <- sign_extend(offset) | |
496 | * I+1: PC += target_offset (delay slot) | |
497 | * | |
498 | * ctx->idx currently points to the branch instruction | |
499 | * but the offset is added to the delay slot so we need | |
500 | * to subtract 4. | |
501 | */ | |
502 | return ctx->offsets[tgt] - | |
503 | (ctx->idx * 4 - ctx->prologue_bytes) - 4; | |
504 | } | |
505 | ||
506 | static inline void emit_bcond(int cond, unsigned int reg1, unsigned int reg2, | |
507 | unsigned int imm, struct jit_ctx *ctx) | |
508 | { | |
509 | if (ctx->target != NULL) { | |
510 | u32 *p = &ctx->target[ctx->idx]; | |
511 | ||
512 | switch (cond) { | |
513 | case MIPS_COND_EQ: | |
514 | uasm_i_beq(&p, reg1, reg2, imm); | |
515 | break; | |
516 | case MIPS_COND_NE: | |
517 | uasm_i_bne(&p, reg1, reg2, imm); | |
518 | break; | |
519 | case MIPS_COND_ALL: | |
520 | uasm_i_b(&p, imm); | |
521 | break; | |
522 | default: | |
523 | pr_warn("%s: Unhandled branch conditional: %d\n", | |
524 | __func__, cond); | |
525 | } | |
526 | } | |
527 | ctx->idx++; | |
528 | } | |
529 | ||
530 | static inline void emit_b(unsigned int imm, struct jit_ctx *ctx) | |
531 | { | |
532 | emit_bcond(MIPS_COND_ALL, r_zero, r_zero, imm, ctx); | |
533 | } | |
534 | ||
535 | static inline void emit_jalr(unsigned int link, unsigned int reg, | |
536 | struct jit_ctx *ctx) | |
537 | { | |
538 | emit_instr(ctx, jalr, link, reg); | |
539 | } | |
540 | ||
541 | static inline void emit_jr(unsigned int reg, struct jit_ctx *ctx) | |
542 | { | |
543 | emit_instr(ctx, jr, reg); | |
544 | } | |
545 | ||
546 | static inline u16 align_sp(unsigned int num) | |
547 | { | |
548 | /* Double word alignment for 32-bit, quadword for 64-bit */ | |
549 | unsigned int align = config_enabled(CONFIG_64BIT) ? 16 : 8; | |
550 | num = (num + (align - 1)) & -align; | |
551 | return num; | |
552 | } | |
553 | ||
554 | static inline void update_on_xread(struct jit_ctx *ctx) | |
555 | { | |
556 | if (!(ctx->flags & SEEN_X)) | |
557 | ctx->flags |= FLAG_NEED_X_RESET; | |
558 | ||
559 | ctx->flags |= SEEN_X; | |
560 | } | |
561 | ||
562 | static bool is_load_to_a(u16 inst) | |
563 | { | |
564 | switch (inst) { | |
a83d081e DB |
565 | case BPF_LD | BPF_W | BPF_LEN: |
566 | case BPF_LD | BPF_W | BPF_ABS: | |
567 | case BPF_LD | BPF_H | BPF_ABS: | |
568 | case BPF_LD | BPF_B | BPF_ABS: | |
c6610de3 MC |
569 | return true; |
570 | default: | |
571 | return false; | |
572 | } | |
573 | } | |
574 | ||
575 | static void save_bpf_jit_regs(struct jit_ctx *ctx, unsigned offset) | |
576 | { | |
577 | int i = 0, real_off = 0; | |
578 | u32 sflags, tmp_flags; | |
579 | ||
580 | /* Adjust the stack pointer */ | |
581 | emit_stack_offset(-align_sp(offset), ctx); | |
582 | ||
583 | if (ctx->flags & SEEN_CALL) { | |
584 | /* Argument save area */ | |
585 | if (config_enabled(CONFIG_64BIT)) | |
586 | /* Bottom of current frame */ | |
587 | real_off = align_sp(offset) - RSIZE; | |
588 | else | |
589 | /* Top of previous frame */ | |
590 | real_off = align_sp(offset) + RSIZE; | |
591 | emit_store_stack_reg(MIPS_R_A0, r_sp, real_off, ctx); | |
592 | emit_store_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx); | |
593 | ||
594 | real_off = 0; | |
595 | } | |
596 | ||
597 | tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT; | |
598 | /* sflags is essentially a bitmap */ | |
599 | while (tmp_flags) { | |
600 | if ((sflags >> i) & 0x1) { | |
601 | emit_store_stack_reg(MIPS_R_S0 + i, r_sp, real_off, | |
602 | ctx); | |
603 | real_off += RSIZE; | |
604 | } | |
605 | i++; | |
606 | tmp_flags >>= 1; | |
607 | } | |
608 | ||
609 | /* save return address */ | |
610 | if (ctx->flags & SEEN_CALL) { | |
611 | emit_store_stack_reg(r_ra, r_sp, real_off, ctx); | |
612 | real_off += RSIZE; | |
613 | } | |
614 | ||
615 | /* Setup r_M leaving the alignment gap if necessary */ | |
616 | if (ctx->flags & SEEN_MEM) { | |
617 | if (real_off % (RSIZE * 2)) | |
618 | real_off += RSIZE; | |
619 | emit_addiu(r_M, r_sp, real_off, ctx); | |
620 | } | |
621 | } | |
622 | ||
623 | static void restore_bpf_jit_regs(struct jit_ctx *ctx, | |
624 | unsigned int offset) | |
625 | { | |
626 | int i, real_off = 0; | |
627 | u32 sflags, tmp_flags; | |
628 | ||
629 | if (ctx->flags & SEEN_CALL) { | |
630 | if (config_enabled(CONFIG_64BIT)) | |
631 | /* Bottom of current frame */ | |
632 | real_off = align_sp(offset) - RSIZE; | |
633 | else | |
634 | /* Top of previous frame */ | |
635 | real_off = align_sp(offset) + RSIZE; | |
636 | emit_load_stack_reg(MIPS_R_A0, r_sp, real_off, ctx); | |
637 | emit_load_stack_reg(MIPS_R_A1, r_sp, real_off + RSIZE, ctx); | |
638 | ||
639 | real_off = 0; | |
640 | } | |
641 | ||
642 | tmp_flags = sflags = ctx->flags >> SEEN_SREG_SFT; | |
643 | /* sflags is a bitmap */ | |
644 | i = 0; | |
645 | while (tmp_flags) { | |
646 | if ((sflags >> i) & 0x1) { | |
647 | emit_load_stack_reg(MIPS_R_S0 + i, r_sp, real_off, | |
648 | ctx); | |
649 | real_off += RSIZE; | |
650 | } | |
651 | i++; | |
652 | tmp_flags >>= 1; | |
653 | } | |
654 | ||
655 | /* restore return address */ | |
656 | if (ctx->flags & SEEN_CALL) | |
657 | emit_load_stack_reg(r_ra, r_sp, real_off, ctx); | |
658 | ||
659 | /* Restore the sp and discard the scrach memory */ | |
660 | emit_stack_offset(align_sp(offset), ctx); | |
661 | } | |
662 | ||
663 | static unsigned int get_stack_depth(struct jit_ctx *ctx) | |
664 | { | |
665 | int sp_off = 0; | |
666 | ||
667 | ||
668 | /* How may s* regs do we need to preserved? */ | |
669 | sp_off += hweight32(ctx->flags >> SEEN_SREG_SFT) * RSIZE; | |
670 | ||
671 | if (ctx->flags & SEEN_MEM) | |
672 | sp_off += 4 * BPF_MEMWORDS; /* BPF_MEMWORDS are 32-bit */ | |
673 | ||
674 | if (ctx->flags & SEEN_CALL) | |
675 | /* | |
676 | * The JIT code make calls to external functions using 2 | |
677 | * arguments. Therefore, for o32 we don't need to allocate | |
678 | * space because we don't care if the argumetns are lost | |
679 | * across calls. We do need however to preserve incoming | |
680 | * arguments but the space is already allocated for us by | |
681 | * the caller. On the other hand, for n64, we need to allocate | |
682 | * this space ourselves. We need to preserve $ra as well. | |
683 | */ | |
684 | sp_off += config_enabled(CONFIG_64BIT) ? | |
685 | (ARGS_USED_BY_JIT + 1) * RSIZE : RSIZE; | |
686 | ||
687 | /* | |
688 | * Subtract the bytes for the last registers since we only care about | |
689 | * the location on the stack pointer. | |
690 | */ | |
691 | return sp_off - RSIZE; | |
692 | } | |
693 | ||
694 | static void build_prologue(struct jit_ctx *ctx) | |
695 | { | |
696 | u16 first_inst = ctx->skf->insns[0].code; | |
697 | int sp_off; | |
698 | ||
699 | /* Calculate the total offset for the stack pointer */ | |
700 | sp_off = get_stack_depth(ctx); | |
701 | save_bpf_jit_regs(ctx, sp_off); | |
702 | ||
703 | if (ctx->flags & SEEN_SKB) | |
704 | emit_reg_move(r_skb, MIPS_R_A0, ctx); | |
705 | ||
706 | if (ctx->flags & FLAG_NEED_X_RESET) | |
707 | emit_jit_reg_move(r_X, r_zero, ctx); | |
708 | ||
709 | /* Do not leak kernel data to userspace */ | |
a83d081e | 710 | if ((first_inst != (BPF_RET | BPF_K)) && !(is_load_to_a(first_inst))) |
c6610de3 MC |
711 | emit_jit_reg_move(r_A, r_zero, ctx); |
712 | } | |
713 | ||
714 | static void build_epilogue(struct jit_ctx *ctx) | |
715 | { | |
716 | unsigned int sp_off; | |
717 | ||
718 | /* Calculate the total offset for the stack pointer */ | |
719 | ||
720 | sp_off = get_stack_depth(ctx); | |
721 | restore_bpf_jit_regs(ctx, sp_off); | |
722 | ||
723 | /* Return */ | |
724 | emit_jr(r_ra, ctx); | |
725 | emit_nop(ctx); | |
726 | } | |
727 | ||
728 | static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset) | |
729 | { | |
730 | u8 ret; | |
731 | int err; | |
732 | ||
733 | err = skb_copy_bits(skb, offset, &ret, 1); | |
734 | ||
735 | return (u64)err << 32 | ret; | |
736 | } | |
737 | ||
738 | static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset) | |
739 | { | |
740 | u16 ret; | |
741 | int err; | |
742 | ||
743 | err = skb_copy_bits(skb, offset, &ret, 2); | |
744 | ||
745 | return (u64)err << 32 | ntohs(ret); | |
746 | } | |
747 | ||
748 | static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset) | |
749 | { | |
750 | u32 ret; | |
751 | int err; | |
752 | ||
753 | err = skb_copy_bits(skb, offset, &ret, 4); | |
754 | ||
755 | return (u64)err << 32 | ntohl(ret); | |
756 | } | |
757 | ||
758 | #define PKT_TYPE_MAX 7 | |
759 | static int pkt_type_offset(void) | |
760 | { | |
761 | struct sk_buff skb_probe = { | |
762 | .pkt_type = ~0, | |
763 | }; | |
764 | char *ct = (char *)&skb_probe; | |
765 | unsigned int off; | |
766 | ||
767 | for (off = 0; off < sizeof(struct sk_buff); off++) { | |
768 | if (ct[off] == PKT_TYPE_MAX) | |
769 | return off; | |
770 | } | |
771 | pr_err_once("Please fix pkt_type_offset(), as pkt_type couldn't be found\n"); | |
772 | return -1; | |
773 | } | |
774 | ||
775 | static int build_body(struct jit_ctx *ctx) | |
776 | { | |
777 | void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w}; | |
778 | const struct sk_filter *prog = ctx->skf; | |
779 | const struct sock_filter *inst; | |
780 | unsigned int i, off, load_order, condt; | |
781 | u32 k, b_off __maybe_unused; | |
782 | ||
783 | for (i = 0; i < prog->len; i++) { | |
a83d081e DB |
784 | u16 code; |
785 | ||
c6610de3 MC |
786 | inst = &(prog->insns[i]); |
787 | pr_debug("%s: code->0x%02x, jt->0x%x, jf->0x%x, k->0x%x\n", | |
788 | __func__, inst->code, inst->jt, inst->jf, inst->k); | |
789 | k = inst->k; | |
a83d081e | 790 | code = bpf_anc_helper(inst); |
c6610de3 MC |
791 | |
792 | if (ctx->target == NULL) | |
793 | ctx->offsets[i] = ctx->idx * 4; | |
794 | ||
a83d081e DB |
795 | switch (code) { |
796 | case BPF_LD | BPF_IMM: | |
c6610de3 MC |
797 | /* A <- k ==> li r_A, k */ |
798 | ctx->flags |= SEEN_A; | |
799 | emit_load_imm(r_A, k, ctx); | |
800 | break; | |
a83d081e | 801 | case BPF_LD | BPF_W | BPF_LEN: |
c6610de3 MC |
802 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4); |
803 | /* A <- len ==> lw r_A, offset(skb) */ | |
804 | ctx->flags |= SEEN_SKB | SEEN_A; | |
805 | off = offsetof(struct sk_buff, len); | |
806 | emit_load(r_A, r_skb, off, ctx); | |
807 | break; | |
a83d081e | 808 | case BPF_LD | BPF_MEM: |
c6610de3 MC |
809 | /* A <- M[k] ==> lw r_A, offset(M) */ |
810 | ctx->flags |= SEEN_MEM | SEEN_A; | |
811 | emit_load(r_A, r_M, SCRATCH_OFF(k), ctx); | |
812 | break; | |
a83d081e | 813 | case BPF_LD | BPF_W | BPF_ABS: |
c6610de3 MC |
814 | /* A <- P[k:4] */ |
815 | load_order = 2; | |
816 | goto load; | |
a83d081e | 817 | case BPF_LD | BPF_H | BPF_ABS: |
c6610de3 MC |
818 | /* A <- P[k:2] */ |
819 | load_order = 1; | |
820 | goto load; | |
a83d081e | 821 | case BPF_LD | BPF_B | BPF_ABS: |
c6610de3 MC |
822 | /* A <- P[k:1] */ |
823 | load_order = 0; | |
824 | load: | |
55393ee5 MC |
825 | /* the interpreter will deal with the negative K */ |
826 | if ((int)k < 0) | |
827 | return -ENOTSUPP; | |
828 | ||
c6610de3 MC |
829 | emit_load_imm(r_off, k, ctx); |
830 | load_common: | |
55393ee5 MC |
831 | /* |
832 | * We may got here from the indirect loads so | |
833 | * return if offset is negative. | |
834 | */ | |
835 | emit_slt(r_s0, r_off, r_zero, ctx); | |
836 | emit_bcond(MIPS_COND_NE, r_s0, r_zero, | |
837 | b_imm(prog->len, ctx), ctx); | |
838 | emit_reg_move(r_ret, r_zero, ctx); | |
839 | ||
c6610de3 MC |
840 | ctx->flags |= SEEN_CALL | SEEN_OFF | SEEN_S0 | |
841 | SEEN_SKB | SEEN_A; | |
842 | ||
843 | emit_load_func(r_s0, (ptr)load_func[load_order], | |
844 | ctx); | |
845 | emit_reg_move(MIPS_R_A0, r_skb, ctx); | |
846 | emit_jalr(MIPS_R_RA, r_s0, ctx); | |
847 | /* Load second argument to delay slot */ | |
848 | emit_reg_move(MIPS_R_A1, r_off, ctx); | |
849 | /* Check the error value */ | |
850 | if (config_enabled(CONFIG_64BIT)) { | |
851 | /* Get error code from the top 32-bits */ | |
852 | emit_dsrl32(r_s0, r_val, 0, ctx); | |
853 | /* Branch to 3 instructions ahead */ | |
854 | emit_bcond(MIPS_COND_NE, r_s0, r_zero, 3 << 2, | |
855 | ctx); | |
856 | } else { | |
857 | /* Branch to 3 instructions ahead */ | |
858 | emit_bcond(MIPS_COND_NE, r_err, r_zero, 3 << 2, | |
859 | ctx); | |
860 | } | |
861 | emit_nop(ctx); | |
862 | /* We are good */ | |
863 | emit_b(b_imm(i + 1, ctx), ctx); | |
864 | emit_jit_reg_move(r_A, r_val, ctx); | |
865 | /* Return with error */ | |
866 | emit_b(b_imm(prog->len, ctx), ctx); | |
867 | emit_reg_move(r_ret, r_zero, ctx); | |
868 | break; | |
a83d081e | 869 | case BPF_LD | BPF_W | BPF_IND: |
c6610de3 MC |
870 | /* A <- P[X + k:4] */ |
871 | load_order = 2; | |
872 | goto load_ind; | |
a83d081e | 873 | case BPF_LD | BPF_H | BPF_IND: |
c6610de3 MC |
874 | /* A <- P[X + k:2] */ |
875 | load_order = 1; | |
876 | goto load_ind; | |
a83d081e | 877 | case BPF_LD | BPF_B | BPF_IND: |
c6610de3 MC |
878 | /* A <- P[X + k:1] */ |
879 | load_order = 0; | |
880 | load_ind: | |
881 | update_on_xread(ctx); | |
882 | ctx->flags |= SEEN_OFF | SEEN_X; | |
883 | emit_addiu(r_off, r_X, k, ctx); | |
884 | goto load_common; | |
a83d081e | 885 | case BPF_LDX | BPF_IMM: |
c6610de3 MC |
886 | /* X <- k */ |
887 | ctx->flags |= SEEN_X; | |
888 | emit_load_imm(r_X, k, ctx); | |
889 | break; | |
a83d081e | 890 | case BPF_LDX | BPF_MEM: |
c6610de3 MC |
891 | /* X <- M[k] */ |
892 | ctx->flags |= SEEN_X | SEEN_MEM; | |
893 | emit_load(r_X, r_M, SCRATCH_OFF(k), ctx); | |
894 | break; | |
a83d081e | 895 | case BPF_LDX | BPF_W | BPF_LEN: |
c6610de3 MC |
896 | /* X <- len */ |
897 | ctx->flags |= SEEN_X | SEEN_SKB; | |
898 | off = offsetof(struct sk_buff, len); | |
899 | emit_load(r_X, r_skb, off, ctx); | |
900 | break; | |
a83d081e | 901 | case BPF_LDX | BPF_B | BPF_MSH: |
55393ee5 MC |
902 | /* the interpreter will deal with the negative K */ |
903 | if ((int)k < 0) | |
904 | return -ENOTSUPP; | |
905 | ||
c6610de3 MC |
906 | /* X <- 4 * (P[k:1] & 0xf) */ |
907 | ctx->flags |= SEEN_X | SEEN_CALL | SEEN_S0 | SEEN_SKB; | |
908 | /* Load offset to a1 */ | |
909 | emit_load_func(r_s0, (ptr)jit_get_skb_b, ctx); | |
910 | /* | |
911 | * This may emit two instructions so it may not fit | |
912 | * in the delay slot. So use a0 in the delay slot. | |
913 | */ | |
914 | emit_load_imm(MIPS_R_A1, k, ctx); | |
915 | emit_jalr(MIPS_R_RA, r_s0, ctx); | |
916 | emit_reg_move(MIPS_R_A0, r_skb, ctx); /* delay slot */ | |
917 | /* Check the error value */ | |
918 | if (config_enabled(CONFIG_64BIT)) { | |
919 | /* Top 32-bits of $v0 on 64-bit */ | |
920 | emit_dsrl32(r_s0, r_val, 0, ctx); | |
921 | emit_bcond(MIPS_COND_NE, r_s0, r_zero, | |
922 | 3 << 2, ctx); | |
923 | } else { | |
924 | emit_bcond(MIPS_COND_NE, r_err, r_zero, | |
925 | 3 << 2, ctx); | |
926 | } | |
927 | /* No need for delay slot */ | |
928 | /* We are good */ | |
929 | /* X <- P[1:K] & 0xf */ | |
930 | emit_andi(r_X, r_val, 0xf, ctx); | |
931 | /* X << 2 */ | |
932 | emit_b(b_imm(i + 1, ctx), ctx); | |
933 | emit_sll(r_X, r_X, 2, ctx); /* delay slot */ | |
934 | /* Return with error */ | |
935 | emit_b(b_imm(prog->len, ctx), ctx); | |
936 | emit_load_imm(r_ret, 0, ctx); /* delay slot */ | |
937 | break; | |
a83d081e | 938 | case BPF_ST: |
c6610de3 MC |
939 | /* M[k] <- A */ |
940 | ctx->flags |= SEEN_MEM | SEEN_A; | |
941 | emit_store(r_A, r_M, SCRATCH_OFF(k), ctx); | |
942 | break; | |
a83d081e | 943 | case BPF_STX: |
c6610de3 MC |
944 | /* M[k] <- X */ |
945 | ctx->flags |= SEEN_MEM | SEEN_X; | |
946 | emit_store(r_X, r_M, SCRATCH_OFF(k), ctx); | |
947 | break; | |
a83d081e | 948 | case BPF_ALU | BPF_ADD | BPF_K: |
c6610de3 MC |
949 | /* A += K */ |
950 | ctx->flags |= SEEN_A; | |
951 | emit_addiu(r_A, r_A, k, ctx); | |
952 | break; | |
a83d081e | 953 | case BPF_ALU | BPF_ADD | BPF_X: |
c6610de3 MC |
954 | /* A += X */ |
955 | ctx->flags |= SEEN_A | SEEN_X; | |
956 | emit_addu(r_A, r_A, r_X, ctx); | |
957 | break; | |
a83d081e | 958 | case BPF_ALU | BPF_SUB | BPF_K: |
c6610de3 MC |
959 | /* A -= K */ |
960 | ctx->flags |= SEEN_A; | |
961 | emit_addiu(r_A, r_A, -k, ctx); | |
962 | break; | |
a83d081e | 963 | case BPF_ALU | BPF_SUB | BPF_X: |
c6610de3 MC |
964 | /* A -= X */ |
965 | ctx->flags |= SEEN_A | SEEN_X; | |
966 | emit_subu(r_A, r_A, r_X, ctx); | |
967 | break; | |
a83d081e | 968 | case BPF_ALU | BPF_MUL | BPF_K: |
c6610de3 MC |
969 | /* A *= K */ |
970 | /* Load K to scratch register before MUL */ | |
971 | ctx->flags |= SEEN_A | SEEN_S0; | |
972 | emit_load_imm(r_s0, k, ctx); | |
973 | emit_mul(r_A, r_A, r_s0, ctx); | |
974 | break; | |
a83d081e | 975 | case BPF_ALU | BPF_MUL | BPF_X: |
c6610de3 MC |
976 | /* A *= X */ |
977 | update_on_xread(ctx); | |
978 | ctx->flags |= SEEN_A | SEEN_X; | |
979 | emit_mul(r_A, r_A, r_X, ctx); | |
980 | break; | |
a83d081e | 981 | case BPF_ALU | BPF_DIV | BPF_K: |
c6610de3 MC |
982 | /* A /= k */ |
983 | if (k == 1) | |
984 | break; | |
985 | if (optimize_div(&k)) { | |
986 | ctx->flags |= SEEN_A; | |
987 | emit_srl(r_A, r_A, k, ctx); | |
988 | break; | |
989 | } | |
990 | ctx->flags |= SEEN_A | SEEN_S0; | |
991 | emit_load_imm(r_s0, k, ctx); | |
992 | emit_div(r_A, r_s0, ctx); | |
993 | break; | |
a83d081e | 994 | case BPF_ALU | BPF_MOD | BPF_K: |
c6610de3 MC |
995 | /* A %= k */ |
996 | if (k == 1 || optimize_div(&k)) { | |
997 | ctx->flags |= SEEN_A; | |
998 | emit_jit_reg_move(r_A, r_zero, ctx); | |
999 | } else { | |
1000 | ctx->flags |= SEEN_A | SEEN_S0; | |
1001 | emit_load_imm(r_s0, k, ctx); | |
1002 | emit_mod(r_A, r_s0, ctx); | |
1003 | } | |
1004 | break; | |
a83d081e | 1005 | case BPF_ALU | BPF_DIV | BPF_X: |
c6610de3 MC |
1006 | /* A /= X */ |
1007 | update_on_xread(ctx); | |
1008 | ctx->flags |= SEEN_X | SEEN_A; | |
1009 | /* Check if r_X is zero */ | |
1010 | emit_bcond(MIPS_COND_EQ, r_X, r_zero, | |
1011 | b_imm(prog->len, ctx), ctx); | |
1012 | emit_load_imm(r_val, 0, ctx); /* delay slot */ | |
1013 | emit_div(r_A, r_X, ctx); | |
1014 | break; | |
a83d081e | 1015 | case BPF_ALU | BPF_MOD | BPF_X: |
c6610de3 MC |
1016 | /* A %= X */ |
1017 | update_on_xread(ctx); | |
1018 | ctx->flags |= SEEN_X | SEEN_A; | |
1019 | /* Check if r_X is zero */ | |
1020 | emit_bcond(MIPS_COND_EQ, r_X, r_zero, | |
1021 | b_imm(prog->len, ctx), ctx); | |
1022 | emit_load_imm(r_val, 0, ctx); /* delay slot */ | |
1023 | emit_mod(r_A, r_X, ctx); | |
1024 | break; | |
a83d081e | 1025 | case BPF_ALU | BPF_OR | BPF_K: |
c6610de3 MC |
1026 | /* A |= K */ |
1027 | ctx->flags |= SEEN_A; | |
1028 | emit_ori(r_A, r_A, k, ctx); | |
1029 | break; | |
a83d081e | 1030 | case BPF_ALU | BPF_OR | BPF_X: |
c6610de3 MC |
1031 | /* A |= X */ |
1032 | update_on_xread(ctx); | |
1033 | ctx->flags |= SEEN_A; | |
1034 | emit_ori(r_A, r_A, r_X, ctx); | |
1035 | break; | |
a83d081e | 1036 | case BPF_ALU | BPF_XOR | BPF_K: |
c6610de3 MC |
1037 | /* A ^= k */ |
1038 | ctx->flags |= SEEN_A; | |
1039 | emit_xori(r_A, r_A, k, ctx); | |
1040 | break; | |
a83d081e DB |
1041 | case BPF_ANC | SKF_AD_ALU_XOR_X: |
1042 | case BPF_ALU | BPF_XOR | BPF_X: | |
c6610de3 MC |
1043 | /* A ^= X */ |
1044 | update_on_xread(ctx); | |
1045 | ctx->flags |= SEEN_A; | |
1046 | emit_xor(r_A, r_A, r_X, ctx); | |
1047 | break; | |
a83d081e | 1048 | case BPF_ALU | BPF_AND | BPF_K: |
c6610de3 MC |
1049 | /* A &= K */ |
1050 | ctx->flags |= SEEN_A; | |
1051 | emit_andi(r_A, r_A, k, ctx); | |
1052 | break; | |
a83d081e | 1053 | case BPF_ALU | BPF_AND | BPF_X: |
c6610de3 MC |
1054 | /* A &= X */ |
1055 | update_on_xread(ctx); | |
1056 | ctx->flags |= SEEN_A | SEEN_X; | |
1057 | emit_and(r_A, r_A, r_X, ctx); | |
1058 | break; | |
a83d081e | 1059 | case BPF_ALU | BPF_LSH | BPF_K: |
c6610de3 MC |
1060 | /* A <<= K */ |
1061 | ctx->flags |= SEEN_A; | |
1062 | emit_sll(r_A, r_A, k, ctx); | |
1063 | break; | |
a83d081e | 1064 | case BPF_ALU | BPF_LSH | BPF_X: |
c6610de3 MC |
1065 | /* A <<= X */ |
1066 | ctx->flags |= SEEN_A | SEEN_X; | |
1067 | update_on_xread(ctx); | |
1068 | emit_sllv(r_A, r_A, r_X, ctx); | |
1069 | break; | |
a83d081e | 1070 | case BPF_ALU | BPF_RSH | BPF_K: |
c6610de3 MC |
1071 | /* A >>= K */ |
1072 | ctx->flags |= SEEN_A; | |
1073 | emit_srl(r_A, r_A, k, ctx); | |
1074 | break; | |
a83d081e | 1075 | case BPF_ALU | BPF_RSH | BPF_X: |
c6610de3 MC |
1076 | ctx->flags |= SEEN_A | SEEN_X; |
1077 | update_on_xread(ctx); | |
1078 | emit_srlv(r_A, r_A, r_X, ctx); | |
1079 | break; | |
a83d081e | 1080 | case BPF_ALU | BPF_NEG: |
c6610de3 MC |
1081 | /* A = -A */ |
1082 | ctx->flags |= SEEN_A; | |
1083 | emit_neg(r_A, ctx); | |
1084 | break; | |
a83d081e | 1085 | case BPF_JMP | BPF_JA: |
c6610de3 MC |
1086 | /* pc += K */ |
1087 | emit_b(b_imm(i + k + 1, ctx), ctx); | |
1088 | emit_nop(ctx); | |
1089 | break; | |
a83d081e | 1090 | case BPF_JMP | BPF_JEQ | BPF_K: |
c6610de3 MC |
1091 | /* pc += ( A == K ) ? pc->jt : pc->jf */ |
1092 | condt = MIPS_COND_EQ | MIPS_COND_K; | |
1093 | goto jmp_cmp; | |
a83d081e | 1094 | case BPF_JMP | BPF_JEQ | BPF_X: |
c6610de3 MC |
1095 | ctx->flags |= SEEN_X; |
1096 | /* pc += ( A == X ) ? pc->jt : pc->jf */ | |
1097 | condt = MIPS_COND_EQ | MIPS_COND_X; | |
1098 | goto jmp_cmp; | |
a83d081e | 1099 | case BPF_JMP | BPF_JGE | BPF_K: |
c6610de3 MC |
1100 | /* pc += ( A >= K ) ? pc->jt : pc->jf */ |
1101 | condt = MIPS_COND_GE | MIPS_COND_K; | |
1102 | goto jmp_cmp; | |
a83d081e | 1103 | case BPF_JMP | BPF_JGE | BPF_X: |
c6610de3 MC |
1104 | ctx->flags |= SEEN_X; |
1105 | /* pc += ( A >= X ) ? pc->jt : pc->jf */ | |
1106 | condt = MIPS_COND_GE | MIPS_COND_X; | |
1107 | goto jmp_cmp; | |
a83d081e | 1108 | case BPF_JMP | BPF_JGT | BPF_K: |
c6610de3 MC |
1109 | /* pc += ( A > K ) ? pc->jt : pc->jf */ |
1110 | condt = MIPS_COND_GT | MIPS_COND_K; | |
1111 | goto jmp_cmp; | |
a83d081e | 1112 | case BPF_JMP | BPF_JGT | BPF_X: |
c6610de3 MC |
1113 | ctx->flags |= SEEN_X; |
1114 | /* pc += ( A > X ) ? pc->jt : pc->jf */ | |
1115 | condt = MIPS_COND_GT | MIPS_COND_X; | |
1116 | jmp_cmp: | |
1117 | /* Greater or Equal */ | |
1118 | if ((condt & MIPS_COND_GE) || | |
1119 | (condt & MIPS_COND_GT)) { | |
1120 | if (condt & MIPS_COND_K) { /* K */ | |
1121 | ctx->flags |= SEEN_S0 | SEEN_A; | |
1122 | emit_sltiu(r_s0, r_A, k, ctx); | |
1123 | } else { /* X */ | |
1124 | ctx->flags |= SEEN_S0 | SEEN_A | | |
1125 | SEEN_X; | |
1126 | emit_sltu(r_s0, r_A, r_X, ctx); | |
1127 | } | |
1128 | /* A < (K|X) ? r_scrach = 1 */ | |
1129 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1130 | emit_bcond(MIPS_COND_GT, r_s0, r_zero, b_off, | |
1131 | ctx); | |
1132 | emit_nop(ctx); | |
1133 | /* A > (K|X) ? scratch = 0 */ | |
1134 | if (condt & MIPS_COND_GT) { | |
1135 | /* Checking for equality */ | |
1136 | ctx->flags |= SEEN_S0 | SEEN_A | SEEN_X; | |
1137 | if (condt & MIPS_COND_K) | |
1138 | emit_load_imm(r_s0, k, ctx); | |
1139 | else | |
1140 | emit_jit_reg_move(r_s0, r_X, | |
1141 | ctx); | |
1142 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1143 | emit_bcond(MIPS_COND_EQ, r_A, r_s0, | |
1144 | b_off, ctx); | |
1145 | emit_nop(ctx); | |
1146 | /* Finally, A > K|X */ | |
1147 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1148 | emit_b(b_off, ctx); | |
1149 | emit_nop(ctx); | |
1150 | } else { | |
1151 | /* A >= (K|X) so jump */ | |
1152 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1153 | emit_b(b_off, ctx); | |
1154 | emit_nop(ctx); | |
1155 | } | |
1156 | } else { | |
1157 | /* A == K|X */ | |
1158 | if (condt & MIPS_COND_K) { /* K */ | |
1159 | ctx->flags |= SEEN_S0 | SEEN_A; | |
1160 | emit_load_imm(r_s0, k, ctx); | |
1161 | /* jump true */ | |
1162 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1163 | emit_bcond(MIPS_COND_EQ, r_A, r_s0, | |
1164 | b_off, ctx); | |
1165 | emit_nop(ctx); | |
1166 | /* jump false */ | |
1167 | b_off = b_imm(i + inst->jf + 1, | |
1168 | ctx); | |
1169 | emit_bcond(MIPS_COND_NE, r_A, r_s0, | |
1170 | b_off, ctx); | |
1171 | emit_nop(ctx); | |
1172 | } else { /* X */ | |
1173 | /* jump true */ | |
1174 | ctx->flags |= SEEN_A | SEEN_X; | |
1175 | b_off = b_imm(i + inst->jt + 1, | |
1176 | ctx); | |
1177 | emit_bcond(MIPS_COND_EQ, r_A, r_X, | |
1178 | b_off, ctx); | |
1179 | emit_nop(ctx); | |
1180 | /* jump false */ | |
1181 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1182 | emit_bcond(MIPS_COND_NE, r_A, r_X, | |
1183 | b_off, ctx); | |
1184 | emit_nop(ctx); | |
1185 | } | |
1186 | } | |
1187 | break; | |
a83d081e | 1188 | case BPF_JMP | BPF_JSET | BPF_K: |
c6610de3 MC |
1189 | ctx->flags |= SEEN_S0 | SEEN_S1 | SEEN_A; |
1190 | /* pc += (A & K) ? pc -> jt : pc -> jf */ | |
1191 | emit_load_imm(r_s1, k, ctx); | |
1192 | emit_and(r_s0, r_A, r_s1, ctx); | |
1193 | /* jump true */ | |
1194 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1195 | emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx); | |
1196 | emit_nop(ctx); | |
1197 | /* jump false */ | |
1198 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1199 | emit_b(b_off, ctx); | |
1200 | emit_nop(ctx); | |
1201 | break; | |
a83d081e | 1202 | case BPF_JMP | BPF_JSET | BPF_X: |
c6610de3 MC |
1203 | ctx->flags |= SEEN_S0 | SEEN_X | SEEN_A; |
1204 | /* pc += (A & X) ? pc -> jt : pc -> jf */ | |
1205 | emit_and(r_s0, r_A, r_X, ctx); | |
1206 | /* jump true */ | |
1207 | b_off = b_imm(i + inst->jt + 1, ctx); | |
1208 | emit_bcond(MIPS_COND_NE, r_s0, r_zero, b_off, ctx); | |
1209 | emit_nop(ctx); | |
1210 | /* jump false */ | |
1211 | b_off = b_imm(i + inst->jf + 1, ctx); | |
1212 | emit_b(b_off, ctx); | |
1213 | emit_nop(ctx); | |
1214 | break; | |
a83d081e | 1215 | case BPF_RET | BPF_A: |
c6610de3 MC |
1216 | ctx->flags |= SEEN_A; |
1217 | if (i != prog->len - 1) | |
1218 | /* | |
1219 | * If this is not the last instruction | |
1220 | * then jump to the epilogue | |
1221 | */ | |
1222 | emit_b(b_imm(prog->len, ctx), ctx); | |
1223 | emit_reg_move(r_ret, r_A, ctx); /* delay slot */ | |
1224 | break; | |
a83d081e | 1225 | case BPF_RET | BPF_K: |
c6610de3 MC |
1226 | /* |
1227 | * It can emit two instructions so it does not fit on | |
1228 | * the delay slot. | |
1229 | */ | |
1230 | emit_load_imm(r_ret, k, ctx); | |
1231 | if (i != prog->len - 1) { | |
1232 | /* | |
1233 | * If this is not the last instruction | |
1234 | * then jump to the epilogue | |
1235 | */ | |
1236 | emit_b(b_imm(prog->len, ctx), ctx); | |
1237 | emit_nop(ctx); | |
1238 | } | |
1239 | break; | |
a83d081e | 1240 | case BPF_MISC | BPF_TAX: |
c6610de3 MC |
1241 | /* X = A */ |
1242 | ctx->flags |= SEEN_X | SEEN_A; | |
1243 | emit_jit_reg_move(r_X, r_A, ctx); | |
1244 | break; | |
a83d081e | 1245 | case BPF_MISC | BPF_TXA: |
c6610de3 MC |
1246 | /* A = X */ |
1247 | ctx->flags |= SEEN_A | SEEN_X; | |
1248 | update_on_xread(ctx); | |
1249 | emit_jit_reg_move(r_A, r_X, ctx); | |
1250 | break; | |
1251 | /* AUX */ | |
a83d081e | 1252 | case BPF_ANC | SKF_AD_PROTOCOL: |
c6610de3 MC |
1253 | /* A = ntohs(skb->protocol */ |
1254 | ctx->flags |= SEEN_SKB | SEEN_OFF | SEEN_A; | |
1255 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, | |
1256 | protocol) != 2); | |
1257 | off = offsetof(struct sk_buff, protocol); | |
1258 | emit_half_load(r_A, r_skb, off, ctx); | |
1259 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
1260 | /* This needs little endian fixup */ | |
b4f16c93 RB |
1261 | if (cpu_has_mips_r2) { |
1262 | /* R2 and later have the wsbh instruction */ | |
1263 | emit_wsbh(r_A, r_A, ctx); | |
1264 | } else { | |
c6610de3 MC |
1265 | /* Get first byte */ |
1266 | emit_andi(r_tmp_imm, r_A, 0xff, ctx); | |
1267 | /* Shift it */ | |
1268 | emit_sll(r_tmp, r_tmp_imm, 8, ctx); | |
1269 | /* Get second byte */ | |
1270 | emit_srl(r_tmp_imm, r_A, 8, ctx); | |
1271 | emit_andi(r_tmp_imm, r_tmp_imm, 0xff, ctx); | |
1272 | /* Put everyting together in r_A */ | |
1273 | emit_or(r_A, r_tmp, r_tmp_imm, ctx); | |
c6610de3 MC |
1274 | } |
1275 | #endif | |
1276 | break; | |
a83d081e | 1277 | case BPF_ANC | SKF_AD_CPU: |
c6610de3 MC |
1278 | ctx->flags |= SEEN_A | SEEN_OFF; |
1279 | /* A = current_thread_info()->cpu */ | |
1280 | BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info, | |
1281 | cpu) != 4); | |
1282 | off = offsetof(struct thread_info, cpu); | |
1283 | /* $28/gp points to the thread_info struct */ | |
1284 | emit_load(r_A, 28, off, ctx); | |
1285 | break; | |
a83d081e | 1286 | case BPF_ANC | SKF_AD_IFINDEX: |
c6610de3 MC |
1287 | /* A = skb->dev->ifindex */ |
1288 | ctx->flags |= SEEN_SKB | SEEN_A | SEEN_S0; | |
1289 | off = offsetof(struct sk_buff, dev); | |
1290 | emit_load(r_s0, r_skb, off, ctx); | |
1291 | /* error (0) in the delay slot */ | |
1292 | emit_bcond(MIPS_COND_EQ, r_s0, r_zero, | |
1293 | b_imm(prog->len, ctx), ctx); | |
1294 | emit_reg_move(r_ret, r_zero, ctx); | |
1295 | BUILD_BUG_ON(FIELD_SIZEOF(struct net_device, | |
1296 | ifindex) != 4); | |
1297 | off = offsetof(struct net_device, ifindex); | |
1298 | emit_load(r_A, r_s0, off, ctx); | |
1299 | break; | |
a83d081e | 1300 | case BPF_ANC | SKF_AD_MARK: |
c6610de3 MC |
1301 | ctx->flags |= SEEN_SKB | SEEN_A; |
1302 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4); | |
1303 | off = offsetof(struct sk_buff, mark); | |
1304 | emit_load(r_A, r_skb, off, ctx); | |
1305 | break; | |
a83d081e | 1306 | case BPF_ANC | SKF_AD_RXHASH: |
c6610de3 MC |
1307 | ctx->flags |= SEEN_SKB | SEEN_A; |
1308 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4); | |
1309 | off = offsetof(struct sk_buff, hash); | |
1310 | emit_load(r_A, r_skb, off, ctx); | |
1311 | break; | |
a83d081e DB |
1312 | case BPF_ANC | SKF_AD_VLAN_TAG: |
1313 | case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT: | |
c6610de3 MC |
1314 | ctx->flags |= SEEN_SKB | SEEN_S0 | SEEN_A; |
1315 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, | |
1316 | vlan_tci) != 2); | |
1317 | off = offsetof(struct sk_buff, vlan_tci); | |
1318 | emit_half_load(r_s0, r_skb, off, ctx); | |
a83d081e | 1319 | if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) |
c6610de3 MC |
1320 | emit_and(r_A, r_s0, VLAN_VID_MASK, ctx); |
1321 | else | |
1322 | emit_and(r_A, r_s0, VLAN_TAG_PRESENT, ctx); | |
1323 | break; | |
a83d081e | 1324 | case BPF_ANC | SKF_AD_PKTTYPE: |
c6610de3 MC |
1325 | off = pkt_type_offset(); |
1326 | ||
1327 | if (off < 0) | |
1328 | return -1; | |
1329 | emit_load_byte(r_tmp, r_skb, off, ctx); | |
1330 | /* Keep only the last 3 bits */ | |
1331 | emit_andi(r_A, r_tmp, PKT_TYPE_MAX, ctx); | |
1332 | break; | |
a83d081e | 1333 | case BPF_ANC | SKF_AD_QUEUE: |
c6610de3 MC |
1334 | ctx->flags |= SEEN_SKB | SEEN_A; |
1335 | BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, | |
1336 | queue_mapping) != 2); | |
1337 | BUILD_BUG_ON(offsetof(struct sk_buff, | |
1338 | queue_mapping) > 0xff); | |
1339 | off = offsetof(struct sk_buff, queue_mapping); | |
1340 | emit_half_load(r_A, r_skb, off, ctx); | |
1341 | break; | |
1342 | default: | |
1343 | pr_warn("%s: Unhandled opcode: 0x%02x\n", __FILE__, | |
1344 | inst->code); | |
1345 | return -1; | |
1346 | } | |
1347 | } | |
1348 | ||
1349 | /* compute offsets only during the first pass */ | |
1350 | if (ctx->target == NULL) | |
1351 | ctx->offsets[i] = ctx->idx * 4; | |
1352 | ||
1353 | return 0; | |
1354 | } | |
1355 | ||
1356 | int bpf_jit_enable __read_mostly; | |
1357 | ||
1358 | void bpf_jit_compile(struct sk_filter *fp) | |
1359 | { | |
1360 | struct jit_ctx ctx; | |
1361 | unsigned int alloc_size, tmp_idx; | |
1362 | ||
1363 | if (!bpf_jit_enable) | |
1364 | return; | |
1365 | ||
1366 | memset(&ctx, 0, sizeof(ctx)); | |
1367 | ||
1368 | ctx.offsets = kcalloc(fp->len, sizeof(*ctx.offsets), GFP_KERNEL); | |
1369 | if (ctx.offsets == NULL) | |
1370 | return; | |
1371 | ||
1372 | ctx.skf = fp; | |
1373 | ||
1374 | if (build_body(&ctx)) | |
1375 | goto out; | |
1376 | ||
1377 | tmp_idx = ctx.idx; | |
1378 | build_prologue(&ctx); | |
1379 | ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4; | |
1380 | /* just to complete the ctx.idx count */ | |
1381 | build_epilogue(&ctx); | |
1382 | ||
1383 | alloc_size = 4 * ctx.idx; | |
1384 | ctx.target = module_alloc(alloc_size); | |
1385 | if (ctx.target == NULL) | |
1386 | goto out; | |
1387 | ||
1388 | /* Clean it */ | |
1389 | memset(ctx.target, 0, alloc_size); | |
1390 | ||
1391 | ctx.idx = 0; | |
1392 | ||
1393 | /* Generate the actual JIT code */ | |
1394 | build_prologue(&ctx); | |
1395 | build_body(&ctx); | |
1396 | build_epilogue(&ctx); | |
1397 | ||
1398 | /* Update the icache */ | |
1399 | flush_icache_range((ptr)ctx.target, (ptr)(ctx.target + ctx.idx)); | |
1400 | ||
1401 | if (bpf_jit_enable > 1) | |
1402 | /* Dump JIT code */ | |
1403 | bpf_jit_dump(fp->len, alloc_size, 2, ctx.target); | |
1404 | ||
1405 | fp->bpf_func = (void *)ctx.target; | |
1406 | fp->jited = 1; | |
1407 | ||
1408 | out: | |
1409 | kfree(ctx.offsets); | |
1410 | } | |
1411 | ||
1412 | void bpf_jit_free(struct sk_filter *fp) | |
1413 | { | |
1414 | if (fp->jited) | |
1415 | module_free(NULL, fp->bpf_func); | |
1416 | kfree(fp); | |
1417 | } |