MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code
[linux-block.git] / arch / mips / mti-sead3 / sead3-time.c
CommitLineData
3070033a
SH
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 */
8#include <linux/init.h>
9
10#include <asm/setup.h>
11#include <asm/time.h>
12#include <asm/irq.h>
13#include <asm/mips-boards/generic.h>
3070033a
SH
14
15unsigned long cpu_khz;
16
17static int mips_cpu_timer_irq;
18static int mips_cpu_perf_irq;
19
20static void mips_timer_dispatch(void)
21{
22 do_IRQ(mips_cpu_timer_irq);
23}
24
25static void mips_perf_dispatch(void)
26{
27 do_IRQ(mips_cpu_perf_irq);
28}
29
30static void __iomem *status_reg = (void __iomem *)0xbf000410;
31
32/*
33 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect.
34 */
35static unsigned int __init estimate_cpu_frequency(void)
36{
37 unsigned int prid = read_c0_prid() & 0xffff00;
38 unsigned int tick = 0;
39 unsigned int freq;
40 unsigned int orig;
41 unsigned long flags;
42
43 local_irq_save(flags);
44
70342287 45 orig = readl(status_reg) & 0x2; /* get original sample */
3070033a
SH
46 /* wait for transition */
47 while ((readl(status_reg) & 0x2) == orig)
48 ;
70342287 49 orig = orig ^ 0x2; /* flip the bit */
3070033a
SH
50
51 write_c0_count(0);
52
53 /* wait 1 second (the sampling clock transitions every 10ms) */
54 while (tick < 100) {
55 /* wait for transition */
56 while ((readl(status_reg) & 0x2) == orig)
57 ;
70342287 58 orig = orig ^ 0x2; /* flip the bit */
3070033a
SH
59 tick++;
60 }
61
62 freq = read_c0_count();
63
64 local_irq_restore(flags);
65
66 mips_hpt_frequency = freq;
67
68 /* Adjust for processor */
69 if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
70 (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
71 freq *= 2;
72
70342287 73 freq += 5000; /* rounding */
3070033a
SH
74 freq -= freq%10000;
75
76 return freq ;
77}
78
79void read_persistent_clock(struct timespec *ts)
80{
81 ts->tv_sec = 0;
82 ts->tv_nsec = 0;
83}
84
85static void __init plat_perf_setup(void)
86{
87 if (cp0_perfcount_irq >= 0) {
88 if (cpu_has_vint)
89 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
90 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
91 }
92}
93
078a55fc 94unsigned int get_c0_compare_int(void)
3070033a
SH
95{
96 if (cpu_has_vint)
97 set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
98 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
99 return mips_cpu_timer_irq;
100}
101
102void __init plat_time_init(void)
103{
104 unsigned int est_freq;
105
106 est_freq = estimate_cpu_frequency();
107
108 pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000),
109 (est_freq % 1000000) * 100 / 1000000);
110
111 cpu_khz = est_freq / 1000;
112
113 mips_scroll_message();
114
115 plat_perf_setup();
116}