Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Carsten Langgaard, carstenl@mips.com | |
3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. | |
52d65cf8 | 4 | * Copyright (C) 2008 Dmitri Vorobiev |
1da177e4 LT |
5 | * |
6 | * This program is free software; you can distribute it and/or modify it | |
7 | * under the terms of the GNU General Public License (Version 2) as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
13 | * for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
18 | */ | |
54bf038e | 19 | #include <linux/cpu.h> |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | #include <linux/sched.h> | |
22 | #include <linux/ioport.h> | |
54bf038e | 23 | #include <linux/irq.h> |
e8823d26 | 24 | #include <linux/of_fdt.h> |
1da177e4 | 25 | #include <linux/pci.h> |
894673ee | 26 | #include <linux/screen_info.h> |
54bf038e | 27 | #include <linux/time.h> |
1da177e4 | 28 | |
b431f09d | 29 | #include <asm/fw/fw.h> |
e81a8c7d | 30 | #include <asm/mach-malta/malta-dtshim.h> |
237036de | 31 | #include <asm/mips-cm.h> |
1da177e4 | 32 | #include <asm/mips-boards/generic.h> |
1da177e4 LT |
33 | #include <asm/mips-boards/malta.h> |
34 | #include <asm/mips-boards/maltaint.h> | |
35 | #include <asm/dma.h> | |
e8823d26 | 36 | #include <asm/prom.h> |
1da177e4 LT |
37 | #include <asm/traps.h> |
38 | #ifdef CONFIG_VT | |
39 | #include <linux/console.h> | |
40 | #endif | |
41 | ||
39b8d525 RB |
42 | extern void malta_be_init(void); |
43 | extern int malta_be_handler(struct pt_regs *regs, int is_fixup); | |
44 | ||
52d65cf8 | 45 | static struct resource standard_io_resources[] = { |
4ca76513 DV |
46 | { |
47 | .name = "dma1", | |
48 | .start = 0x00, | |
49 | .end = 0x1f, | |
50 | .flags = IORESOURCE_BUSY | |
51 | }, | |
52 | { | |
53 | .name = "timer", | |
54 | .start = 0x40, | |
55 | .end = 0x5f, | |
56 | .flags = IORESOURCE_BUSY | |
57 | }, | |
58 | { | |
59 | .name = "keyboard", | |
60 | .start = 0x60, | |
61 | .end = 0x6f, | |
62 | .flags = IORESOURCE_BUSY | |
63 | }, | |
64 | { | |
65 | .name = "dma page reg", | |
66 | .start = 0x80, | |
67 | .end = 0x8f, | |
68 | .flags = IORESOURCE_BUSY | |
69 | }, | |
70 | { | |
71 | .name = "dma2", | |
72 | .start = 0xc0, | |
73 | .end = 0xdf, | |
74 | .flags = IORESOURCE_BUSY | |
75 | }, | |
1da177e4 LT |
76 | }; |
77 | ||
1da177e4 LT |
78 | const char *get_system_type(void) |
79 | { | |
80 | return "MIPS Malta"; | |
81 | } | |
82 | ||
70342287 | 83 | const char display_string[] = " LINUX ON MALTA "; |
79894c7b | 84 | |
1da177e4 | 85 | #ifdef CONFIG_BLK_DEV_FD |
ef7645cf | 86 | static void __init fd_activate(void) |
1da177e4 LT |
87 | { |
88 | /* | |
89 | * Activate Floppy Controller in the SMSC FDC37M817 Super I/O | |
90 | * Controller. | |
91 | * Done by YAMON 2.00 onwards | |
92 | */ | |
93 | /* Entering config state. */ | |
94 | SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG); | |
95 | ||
96 | /* Activate floppy controller. */ | |
97 | SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG); | |
98 | SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG); | |
99 | SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG); | |
100 | SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG); | |
101 | ||
102 | /* Exit config state. */ | |
103 | SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG); | |
104 | } | |
105 | #endif | |
106 | ||
b6d92b4a SH |
107 | static int __init plat_enable_iocoherency(void) |
108 | { | |
109 | int supported = 0; | |
110 | if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { | |
111 | if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { | |
112 | BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; | |
113 | pr_info("Enabled Bonito CPU coherency\n"); | |
114 | supported = 1; | |
115 | } | |
116 | if (strstr(fw_getcmdline(), "iobcuncached")) { | |
117 | BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; | |
118 | BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & | |
119 | ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | | |
120 | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); | |
121 | pr_info("Disabled Bonito IOBC coherency\n"); | |
122 | } else { | |
123 | BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; | |
124 | BONITO_PCIMEMBASECFG |= | |
125 | (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | | |
126 | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); | |
127 | pr_info("Enabled Bonito IOBC coherency\n"); | |
128 | } | |
237036de | 129 | } else if (mips_cm_numiocu() != 0) { |
b6d92b4a SH |
130 | /* Nothing special needs to be done to enable coherency */ |
131 | pr_info("CMP IOCU detected\n"); | |
132 | if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { | |
133 | pr_crit("IOCU OPERATION DISABLED BY SWITCH - DEFAULTING TO SW IO COHERENCY\n"); | |
134 | return 0; | |
135 | } | |
136 | supported = 1; | |
137 | } | |
138 | hw_coherentio = supported; | |
139 | return supported; | |
140 | } | |
141 | ||
142 | static void __init plat_setup_iocoherency(void) | |
143 | { | |
144 | #ifdef CONFIG_DMA_NONCOHERENT | |
145 | /* | |
146 | * Kernel has been configured with software coherency | |
147 | * but we might choose to turn it off and use hardware | |
148 | * coherency instead. | |
149 | */ | |
150 | if (plat_enable_iocoherency()) { | |
151 | if (coherentio == 0) | |
152 | pr_info("Hardware DMA cache coherency disabled\n"); | |
153 | else | |
154 | pr_info("Hardware DMA cache coherency enabled\n"); | |
155 | } else { | |
156 | if (coherentio == 1) | |
157 | pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); | |
158 | else | |
159 | pr_info("Software DMA cache coherency enabled\n"); | |
160 | } | |
161 | #else | |
162 | if (!plat_enable_iocoherency()) | |
163 | panic("Hardware DMA cache coherency not supported!"); | |
164 | #endif | |
165 | } | |
166 | ||
f3a4ce95 DV |
167 | static void __init pci_clock_check(void) |
168 | { | |
169 | unsigned int __iomem *jmpr_p = | |
170 | (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); | |
171 | int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; | |
4a043d79 | 172 | static const int pciclocks[] __initconst = { |
f3a4ce95 DV |
173 | 33, 20, 25, 30, 12, 16, 37, 10 |
174 | }; | |
175 | int pciclock = pciclocks[jmpr]; | |
a9dde288 | 176 | char *optptr, *argptr = fw_getcmdline(); |
f3a4ce95 | 177 | |
a9dde288 RB |
178 | /* |
179 | * If user passed a pci_clock= option, don't tack on another one | |
180 | */ | |
181 | optptr = strstr(argptr, "pci_clock="); | |
182 | if (optptr && (optptr == argptr || optptr[-1] == ' ')) | |
183 | return; | |
184 | ||
185 | if (pciclock != 33) { | |
186 | pr_warn("WARNING: PCI clock is %dMHz, setting pci_clock\n", | |
49bffbdc | 187 | pciclock); |
f3a4ce95 | 188 | argptr += strlen(argptr); |
a9dde288 | 189 | sprintf(argptr, " pci_clock=%d", pciclock); |
f3a4ce95 | 190 | if (pciclock < 20 || pciclock > 66) |
a9dde288 RB |
191 | pr_warn("WARNING: IDE timing calculations will be " |
192 | "incorrect\n"); | |
f3a4ce95 DV |
193 | } |
194 | } | |
f3a4ce95 | 195 | |
a382963e DV |
196 | #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) |
197 | static void __init screen_info_setup(void) | |
198 | { | |
199 | screen_info = (struct screen_info) { | |
200 | .orig_x = 0, | |
201 | .orig_y = 25, | |
202 | .ext_mem_k = 0, | |
203 | .orig_video_page = 0, | |
204 | .orig_video_mode = 0, | |
205 | .orig_video_cols = 80, | |
206 | .unused2 = 0, | |
207 | .orig_video_ega_bx = 0, | |
208 | .unused3 = 0, | |
209 | .orig_video_lines = 25, | |
210 | .orig_video_isVGA = VIDEO_TYPE_VGAC, | |
211 | .orig_video_points = 16 | |
212 | }; | |
213 | } | |
214 | #endif | |
215 | ||
750dc31c DV |
216 | static void __init bonito_quirks_setup(void) |
217 | { | |
218 | char *argptr; | |
219 | ||
b431f09d | 220 | argptr = fw_getcmdline(); |
750dc31c DV |
221 | if (strstr(argptr, "debug")) { |
222 | BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; | |
49bffbdc | 223 | pr_info("Enabled Bonito debug mode\n"); |
750dc31c DV |
224 | } else |
225 | BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; | |
226 | ||
227 | #ifdef CONFIG_DMA_COHERENT | |
228 | if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { | |
229 | BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; | |
49bffbdc | 230 | pr_info("Enabled Bonito CPU coherency\n"); |
750dc31c | 231 | |
b431f09d | 232 | argptr = fw_getcmdline(); |
750dc31c DV |
233 | if (strstr(argptr, "iobcuncached")) { |
234 | BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; | |
235 | BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & | |
236 | ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | | |
237 | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); | |
49bffbdc | 238 | pr_info("Disabled Bonito IOBC coherency\n"); |
750dc31c DV |
239 | } else { |
240 | BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; | |
241 | BONITO_PCIMEMBASECFG |= | |
242 | (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | | |
243 | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); | |
49bffbdc | 244 | pr_info("Enabled Bonito IOBC coherency\n"); |
750dc31c DV |
245 | } |
246 | } else | |
247 | panic("Hardware DMA cache coherency not supported"); | |
248 | #endif | |
249 | } | |
250 | ||
5e7c1c91 MR |
251 | void __init *plat_get_fdt(void) |
252 | { | |
253 | return (void *)__dtb_start; | |
254 | } | |
255 | ||
2925aba4 | 256 | void __init plat_mem_setup(void) |
1da177e4 LT |
257 | { |
258 | unsigned int i; | |
5e7c1c91 | 259 | void *fdt = plat_get_fdt(); |
1da177e4 | 260 | |
e81a8c7d PB |
261 | fdt = malta_dt_shim(fdt); |
262 | __dt_setup_arch(fdt); | |
e8823d26 | 263 | |
97f2645f | 264 | if (IS_ENABLED(CONFIG_EVA)) |
f8b7faf1 MC |
265 | /* EVA has already been configured in mach-malta/kernel-init.h */ |
266 | pr_info("Enhanced Virtual Addressing (EVA) activated\n"); | |
267 | ||
c83cfc9c RB |
268 | mips_pcibios_init(); |
269 | ||
1da177e4 LT |
270 | /* Request I/O space for devices used on the Malta board. */ |
271 | for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++) | |
272 | request_resource(&ioport_resource, standard_io_resources+i); | |
273 | ||
274 | /* | |
275 | * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge. | |
276 | */ | |
277 | enable_dma(4); | |
278 | ||
1da177e4 | 279 | #ifdef CONFIG_DMA_COHERENT |
750dc31c | 280 | if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO) |
1da177e4 | 281 | panic("Hardware DMA cache coherency not supported"); |
1da177e4 LT |
282 | #endif |
283 | ||
750dc31c DV |
284 | if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) |
285 | bonito_quirks_setup(); | |
286 | ||
b6d92b4a SH |
287 | plat_setup_iocoherency(); |
288 | ||
f3a4ce95 | 289 | pci_clock_check(); |
750dc31c | 290 | |
1da177e4 | 291 | #ifdef CONFIG_BLK_DEV_FD |
49a89efb | 292 | fd_activate(); |
1da177e4 | 293 | #endif |
750dc31c | 294 | |
a382963e DV |
295 | #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) |
296 | screen_info_setup(); | |
1da177e4 | 297 | #endif |
39b8d525 RB |
298 | |
299 | board_be_init = malta_be_init; | |
300 | board_be_handler = malta_be_handler; | |
1da177e4 | 301 | } |