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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-block.git] / arch / mips / mti-malta / malta-int.c
CommitLineData
1da177e4
LT		 1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Routines for generic manipulation of the interrupts found on the MIPS
20 * Malta board.
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
23 */
24#include <linux/init.h>
25#include <linux/irq.h>
26#include <linux/sched.h>
631330f5 27#include <linux/smp.h>
1da177e4 28#include <linux/interrupt.h>
54bf038e 29#include <linux/io.h>
1da177e4 30#include <linux/kernel_stat.h>
25b8ac3b 31#include <linux/kernel.h>
1da177e4
LT		 32#include <linux/random.h>
33
39b8d525 34#include <asm/traps.h>
1da177e4 35#include <asm/i8259.h>
e01402b1 36#include <asm/irq_cpu.h>
ba38cdf9 37#include <asm/irq_regs.h>
1da177e4
LT		 38#include <asm/mips-boards/malta.h>
39#include <asm/mips-boards/maltaint.h>
40#include <asm/mips-boards/piix4.h>
41#include <asm/gt64120.h>
42#include <asm/mips-boards/generic.h>
43#include <asm/mips-boards/msc01_pci.h>
e01402b1 44#include <asm/msc01_ic.h>
39b8d525
RB		 45#include <asm/gic.h>
46#include <asm/gcmpregs.h>
47
48int gcmp_present = -1;
49int gic_present;
50static unsigned long _msc01_biu_base;
51static unsigned long _gcmp_base;
52static unsigned int ipi_map[NR_CPUS];
1da177e4 53
a963dc70 54static DEFINE_RAW_SPINLOCK(mips_irq_lock);
1da177e4
LT		 55
56static inline int mips_pcibios_iack(void)
57{
58 int irq;
af825586 59 u32 dummy;
1da177e4
LT		 60
61 /*
62 * Determine highest priority pending interrupt by performing
63 * a PCI Interrupt Acknowledge cycle.
64 */
b72c0526
CD		 65 switch (mips_revision_sconid) {
66 case MIPS_REVISION_SCON_SOCIT:
67 case MIPS_REVISION_SCON_ROCIT:
68 case MIPS_REVISION_SCON_SOCITSC:
69 case MIPS_REVISION_SCON_SOCITSCP:
af825586 70 MSC_READ(MSC01_PCI_IACK, irq);
1da177e4
LT		 71 irq &= 0xff;
72 break;
b72c0526 73 case MIPS_REVISION_SCON_GT64120:
1da177e4
LT		 74 irq = GT_READ(GT_PCI0_IACK_OFS);
75 irq &= 0xff;
76 break;
b72c0526 77 case MIPS_REVISION_SCON_BONITO:
1da177e4
LT		 78 /* The following will generate a PCI IACK cycle on the
79 * Bonito controller. It's a little bit kludgy, but it
80 * was the easiest way to implement it in hardware at
81 * the given time.
82 */
83 BONITO_PCIMAP_CFG = 0x20000;
84
85 /* Flush Bonito register block */
86 dummy = BONITO_PCIMAP_CFG;
87 iob(); /* sync */
88
accfd35a 89 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
1da177e4
LT		 90 iob(); /* sync */
91 irq &= 0xff;
92 BONITO_PCIMAP_CFG = 0;
93 break;
94 default:
8216d348 95 printk(KERN_WARNING "Unknown system controller.\n");
1da177e4
LT		 96 return -1;
97 }
98 return irq;
99}
100
e01402b1 101static inline int get_int(void)
1da177e4
LT		 102{
103 unsigned long flags;
e01402b1 104 int irq;
a963dc70 105 raw_spin_lock_irqsave(&mips_irq_lock, flags);
1da177e4 106
e01402b1 107 irq = mips_pcibios_iack();
1da177e4
LT		 108
109 /*
479a0e3e
RB		 110 * The only way we can decide if an interrupt is spurious
111 * is by checking the 8259 registers. This needs a spinlock
112 * on an SMP system, so leave it up to the generic code...
1da177e4 113 */
1da177e4 114
a963dc70 115 raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
1da177e4 116
e01402b1 117 return irq;
1da177e4
LT		 118}
119
937a8015 120static void malta_hw0_irqdispatch(void)
1da177e4
LT		 121{
122 int irq;
123
e01402b1 124 irq = get_int();
41c594ab 125 if (irq < 0) {
cd80d548
DV		 126 /* interrupt has already been cleared */
127 return;
41c594ab 128 }
1da177e4 129
937a8015 130 do_IRQ(MALTA_INT_BASE + irq);
1da177e4
LT		 131}
132
39b8d525
RB		 133static void malta_ipi_irqdispatch(void)
134{
135 int irq;
136
137 irq = gic_get_int();
138 if (irq < 0)
139 return; /* interrupt has already been cleared */
140
141 do_IRQ(MIPS_GIC_IRQ_BASE + irq);
142}
143
937a8015 144static void corehi_irqdispatch(void)
1da177e4 145{
937a8015 146 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
af825586 147 unsigned int pcimstat, intisr, inten, intpol;
21a151d8 148 unsigned int intrcause, datalo, datahi;
ba38cdf9 149 struct pt_regs *regs = get_irq_regs();
1da177e4 150
8216d348
DV		 151 printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
152 printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
af825586
DV		 153 "Cause : %08lx\nbadVaddr : %08lx\n",
154 regs->cp0_epc, regs->cp0_status,
155 regs->cp0_cause, regs->cp0_badvaddr);
e01402b1
RB		 156
157 /* Read all the registers and then print them as there is a
158 problem with interspersed printk's upsetting the Bonito controller.
159 Do it for the others too.
160 */
161
b72c0526 162 switch (mips_revision_sconid) {
af825586 163 case MIPS_REVISION_SCON_SOCIT:
b72c0526
CD		 164 case MIPS_REVISION_SCON_ROCIT:
165 case MIPS_REVISION_SCON_SOCITSC:
166 case MIPS_REVISION_SCON_SOCITSCP:
af825586
DV		 167 ll_msc_irq();
168 break;
169 case MIPS_REVISION_SCON_GT64120:
170 intrcause = GT_READ(GT_INTRCAUSE_OFS);
171 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
172 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
8216d348
DV		 173 printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
174 printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
175 datahi, datalo);
af825586
DV		 176 break;
177 case MIPS_REVISION_SCON_BONITO:
178 pcibadaddr = BONITO_PCIBADADDR;
179 pcimstat = BONITO_PCIMSTAT;
180 intisr = BONITO_INTISR;
181 inten = BONITO_INTEN;
182 intpol = BONITO_INTPOL;
183 intedge = BONITO_INTEDGE;
184 intsteer = BONITO_INTSTEER;
185 pcicmd = BONITO_PCICMD;
8216d348
DV		 186 printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
187 printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
188 printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
189 printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
190 printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
191 printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
192 printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
193 printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
af825586
DV		 194 break;
195 }
1da177e4 196
af825586 197 die("CoreHi interrupt", regs);
1da177e4
LT		 198}
199
e4ac58af
RB		 200static inline int clz(unsigned long x)
201{
49a89efb 202 __asm__(
e4ac58af
RB		 203 " .set push \n"
204 " .set mips32 \n"
205 " clz %0, %1 \n"
206 " .set pop \n"
207 : "=r" (x)
208 : "r" (x));
209
210 return x;
211}
212
213/*
214 * Version of ffs that only looks at bits 12..15.
215 */
216static inline unsigned int irq_ffs(unsigned int pending)
217{
218#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
219 return -clz(pending) + 31 - CAUSEB_IP;
220#else
221 unsigned int a0 = 7;
222 unsigned int t0;
223
0118c3ca 224 t0 = pending & 0xf000;
e4ac58af
RB		 225 t0 = t0 < 1;
226 t0 = t0 << 2;
227 a0 = a0 - t0;
0118c3ca 228 pending = pending << t0;
e4ac58af 229
0118c3ca 230 t0 = pending & 0xc000;
e4ac58af
RB		 231 t0 = t0 < 1;
232 t0 = t0 << 1;
233 a0 = a0 - t0;
0118c3ca 234 pending = pending << t0;
e4ac58af 235
0118c3ca 236 t0 = pending & 0x8000;
e4ac58af 237 t0 = t0 < 1;
ae9cef0b 238 /* t0 = t0 << 2; */
e4ac58af 239 a0 = a0 - t0;
ae9cef0b 240 /* pending = pending << t0; */
e4ac58af
RB		 241
242 return a0;
243#endif
244}
245
246/*
247 * IRQs on the Malta board look basically (barring software IRQs which we
248 * don't use at all and all external interrupt sources are combined together
249 * on hardware interrupt 0 (MIPS IRQ 2)) like:
250 *
251 * MIPS IRQ Source
252 * -------- ------
253 * 0 Software (ignored)
254 * 1 Software (ignored)
255 * 2 Combined hardware interrupt (hw0)
256 * 3 Hardware (ignored)
257 * 4 Hardware (ignored)
258 * 5 Hardware (ignored)
259 * 6 Hardware (ignored)
260 * 7 R4k timer (what we use)
261 *
262 * We handle the IRQ according to _our_ priority which is:
263 *
264 * Highest ---- R4k Timer
265 * Lowest ---- Combined hardware interrupt
266 *
267 * then we just return, if multiple IRQs are pending then we will just take
268 * another exception, big deal.
269 */
270
937a8015 271asmlinkage void plat_irq_dispatch(void)
e4ac58af
RB		 272{
273 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
274 int irq;
275
276 irq = irq_ffs(pending);
277
278 if (irq == MIPSCPU_INT_I8259A)
937a8015 279 malta_hw0_irqdispatch();
39b8d525
RB		 280 else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
281 malta_ipi_irqdispatch();
48d480b0 282 else if (irq >= 0)
3b1d4ed5 283 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
e4ac58af 284 else
937a8015 285 spurious_interrupt();
e4ac58af
RB		 286}
287
39b8d525
RB		 288#ifdef CONFIG_MIPS_MT_SMP
289
290
291#define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3
292#define GIC_MIPS_CPU_IPI_CALL_IRQ 4
293
294#define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
295#define C_RESCHED C_SW0
296#define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
297#define C_CALL C_SW1
298static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
299
300static void ipi_resched_dispatch(void)
301{
302 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
303}
304
305static void ipi_call_dispatch(void)
306{
307 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
308}
309
310static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
311{
312 return IRQ_HANDLED;
313}
314
315static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
316{
317 smp_call_function_interrupt();
318
319 return IRQ_HANDLED;
320}
321
322static struct irqaction irq_resched = {
323 .handler = ipi_resched_interrupt,
324 .flags = IRQF_DISABLED|IRQF_PERCPU,
325 .name = "IPI_resched"
326};
327
328static struct irqaction irq_call = {
329 .handler = ipi_call_interrupt,
330 .flags = IRQF_DISABLED|IRQF_PERCPU,
331 .name = "IPI_call"
332};
008ee96f 333#endif /* CONFIG_MIPS_MT_SMP */
a214cef9
TA		 334
335static int gic_resched_int_base;
336static int gic_call_int_base;
337#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
338#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
0365070f
TA		 339
340unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
341{
342 return GIC_CALL_INT(cpu);
343}
344
345unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
346{
347 return GIC_RESCHED_INT(cpu);
348}
39b8d525 349
e01402b1
RB		 350static struct irqaction i8259irq = {
351 .handler = no_action,
352 .name = "XT-PIC cascade"
353};
354
355static struct irqaction corehi_irqaction = {
356 .handler = no_action,
357 .name = "CoreHi"
358};
359
b57c1913 360static msc_irqmap_t __initdata msc_irqmap[] = {
e01402b1
RB		 361 {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
362 {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
363};
b57c1913 364static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
e01402b1 365
b57c1913 366static msc_irqmap_t __initdata msc_eicirqmap[] = {
e01402b1
RB		 367 {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
368 {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
369 {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
370 {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
371 {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
372 {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
373 {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
374 {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
375 {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
376 {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
377};
39b8d525 378
b57c1913 379static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
e01402b1 380
39b8d525
RB		 381/*
382 * This GIC specific tabular array defines the association between External
383 * Interrupts and CPUs/Core Interrupts. The nature of the External
384 * Interrupts is also defined here - polarity/trigger.
385 */
7098f748
CD		 386
387#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
a214cef9 388static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
7098f748
CD		 389 { X, X, X, X, 0 },
390 { X, X, X, X, 0 },
391 { X, X, X, X, 0 },
392 { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
393 { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
394 { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
395 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
396 { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
397 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
398 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
399 { X, X, X, X, 0 },
400 { X, X, X, X, 0 },
401 { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
402 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
403 { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
404 { X, X, X, X, 0 },
405 /* The remainder of this table is initialised by fill_ipi_map */
39b8d525
RB		 406};
407
408/*
409 * GCMP needs to be detected before any SMP initialisation
410 */
47b178bb 411int __init gcmp_probe(unsigned long addr, unsigned long size)
39b8d525 412{
05cf2079
JP		 413 if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
414 gcmp_present = 0;
415 return gcmp_present;
416 }
417
39b8d525
RB		 418 if (gcmp_present >= 0)
419 return gcmp_present;
420
421 _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
422 _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
423 gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
424
425 if (gcmp_present)
7098f748 426 pr_debug("GCMP present\n");
39b8d525
RB		 427 return gcmp_present;
428}
429
7098f748
CD		 430/* Return the number of IOCU's present */
431int __init gcmp_niocu(void)
432{
433 return gcmp_present ?
434 (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
435 0;
436}
437
438/* Set GCMP region attributes */
439void __init gcmp_setregion(int region, unsigned long base,
440 unsigned long mask, int type)
441{
442 GCMPGCBn(CMxBASE, region) = base;
443 GCMPGCBn(CMxMASK, region) = mask | type;
444}
445
7afed6a6 446#if defined(CONFIG_MIPS_MT_SMP)
a214cef9
TA		 447static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
448{
449 int intr = baseintr + cpu;
a214cef9
TA		 450 gic_intr_map[intr].cpunum = cpu;
451 gic_intr_map[intr].pin = cpupin;
452 gic_intr_map[intr].polarity = GIC_POL_POS;
453 gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
7098f748 454 gic_intr_map[intr].flags = GIC_FLAG_IPI;
a214cef9
TA		 455 ipi_map[cpu] |= (1 << (cpupin + 2));
456}
457
7afed6a6 458static void __init fill_ipi_map(void)
39b8d525 459{
a214cef9 460 int cpu;
39b8d525 461
a214cef9
TA		 462 for (cpu = 0; cpu < NR_CPUS; cpu++) {
463 fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
464 fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
39b8d525
RB		 465 }
466}
7afed6a6 467#endif
39b8d525 468
7098f748
CD		 469void __init arch_init_ipiirq(int irq, struct irqaction *action)
470{
471 setup_irq(irq, action);
472 set_irq_handler(irq, handle_percpu_irq);
473}
474
1da177e4
LT		 475void __init arch_init_irq(void)
476{
1da177e4 477 init_i8259_irqs();
e01402b1
RB		 478
479 if (!cpu_has_veic)
97dcb82d 480 mips_cpu_irq_init();
e01402b1 481
39b8d525
RB		 482 if (gcmp_present) {
483 GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
484 gic_present = 1;
485 } else {
05cf2079
JP		 486 if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
487 _msc01_biu_base = (unsigned long)
488 ioremap_nocache(MSC01_BIU_REG_BASE,
489 MSC01_BIU_ADDRSPACE_SZ);
490 gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
491 MSC01_SC_CFG_GICPRES_MSK) >>
492 MSC01_SC_CFG_GICPRES_SHF;
493 }
39b8d525
RB		 494 }
495 if (gic_present)
7098f748 496 pr_debug("GIC present\n");
39b8d525 497
af825586
DV		 498 switch (mips_revision_sconid) {
499 case MIPS_REVISION_SCON_SOCIT:
500 case MIPS_REVISION_SCON_ROCIT:
d725cf38 501 if (cpu_has_veic)
f8071496
DV		 502 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
503 MSC01E_INT_BASE, msc_eicirqmap,
504 msc_nr_eicirqs);
d725cf38 505 else
f8071496
DV		 506 init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
507 MSC01C_INT_BASE, msc_irqmap,
508 msc_nr_irqs);
d725cf38
CD		 509 break;
510
af825586
DV		 511 case MIPS_REVISION_SCON_SOCITSC:
512 case MIPS_REVISION_SCON_SOCITSCP:
e01402b1 513 if (cpu_has_veic)
f8071496
DV		 514 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
515 MSC01E_INT_BASE, msc_eicirqmap,
516 msc_nr_eicirqs);
e01402b1 517 else
f8071496
DV		 518 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
519 MSC01C_INT_BASE, msc_irqmap,
520 msc_nr_irqs);
e01402b1
RB		 521 }
522
523 if (cpu_has_veic) {
49a89efb
RB		 524 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
525 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
526 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
527 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
52b3fc04 528 } else if (cpu_has_vint) {
49a89efb
RB		 529 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
530 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
41c594ab 531#ifdef CONFIG_MIPS_MT_SMTC
49a89efb 532 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
41c594ab 533 (0x100 << MIPSCPU_INT_I8259A));
49a89efb 534 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
41c594ab 535 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
c3a005f4
KK		 536 /*
537 * Temporary hack to ensure that the subsidiary device
538 * interrupts coing in via the i8259A, but associated
539 * with low IRQ numbers, will restore the Status.IM
540 * value associated with the i8259A.
541 */
542 {
543 int i;
544
545 for (i = 0; i < 16; i++)
546 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
547 }
41c594ab 548#else /* Not SMTC */
49a89efb 549 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
f8071496
DV		 550 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
551 &corehi_irqaction);
41c594ab 552#endif /* CONFIG_MIPS_MT_SMTC */
52b3fc04 553 } else {
49a89efb 554 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
f8071496
DV		 555 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
556 &corehi_irqaction);
e01402b1 557 }
39b8d525 558
39b8d525
RB		 559 if (gic_present) {
560 /* FIXME */
561 int i;
7098f748 562#if defined(CONFIG_MIPS_MT_SMP)
a214cef9
TA		 563 gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
564 gic_resched_int_base = gic_call_int_base - NR_CPUS;
39b8d525 565 fill_ipi_map();
7098f748
CD		 566#endif
567 gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
568 ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
39b8d525
RB		 569 if (!gcmp_present) {
570 /* Enable the GIC */
571 i = REG(_msc01_biu_base, MSC01_SC_CFG);
572 REG(_msc01_biu_base, MSC01_SC_CFG) =
573 (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
574 pr_debug("GIC Enabled\n");
575 }
7098f748 576#if defined(CONFIG_MIPS_MT_SMP)
39b8d525
RB		 577 /* set up ipi interrupts */
578 if (cpu_has_vint) {
579 set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
580 set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
581 }
582 /* Argh.. this really needs sorting out.. */
583 printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
584 write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
585 printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
586 write_c0_status(0x1100dc00);
587 printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
a214cef9 588 for (i = 0; i < NR_CPUS; i++) {
7098f748
CD		 589 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
590 GIC_RESCHED_INT(i), &irq_resched);
591 arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
592 GIC_CALL_INT(i), &irq_call);
39b8d525 593 }
7098f748 594#endif
39b8d525 595 } else {
7098f748 596#if defined(CONFIG_MIPS_MT_SMP)
39b8d525
RB		 597 /* set up ipi interrupts */
598 if (cpu_has_veic) {
599 set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
600 set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
601 cpu_ipi_resched_irq = MSC01E_INT_SW0;
602 cpu_ipi_call_irq = MSC01E_INT_SW1;
603 } else {
604 if (cpu_has_vint) {
605 set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
606 set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
607 }
608 cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
609 cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
610 }
7098f748
CD		 611 arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
612 arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
39b8d525 613#endif
7098f748 614 }
39b8d525
RB		 615}
616
617void malta_be_init(void)
618{
619 if (gcmp_present) {
620 /* Could change CM error mask register */
621 }
622}
623
624
625static char *tr[8] = {
626 "mem", "gcr", "gic", "mmio",
627 "0x04", "0x05", "0x06", "0x07"
628};
629
630static char *mcmd[32] = {
631 [0x00] = "0x00",
632 [0x01] = "Legacy Write",
633 [0x02] = "Legacy Read",
634 [0x03] = "0x03",
635 [0x04] = "0x04",
636 [0x05] = "0x05",
637 [0x06] = "0x06",
638 [0x07] = "0x07",
639 [0x08] = "Coherent Read Own",
640 [0x09] = "Coherent Read Share",
641 [0x0a] = "Coherent Read Discard",
642 [0x0b] = "Coherent Ready Share Always",
643 [0x0c] = "Coherent Upgrade",
644 [0x0d] = "Coherent Writeback",
645 [0x0e] = "0x0e",
646 [0x0f] = "0x0f",
647 [0x10] = "Coherent Copyback",
648 [0x11] = "Coherent Copyback Invalidate",
649 [0x12] = "Coherent Invalidate",
650 [0x13] = "Coherent Write Invalidate",
651 [0x14] = "Coherent Completion Sync",
652 [0x15] = "0x15",
653 [0x16] = "0x16",
654 [0x17] = "0x17",
655 [0x18] = "0x18",
656 [0x19] = "0x19",
657 [0x1a] = "0x1a",
658 [0x1b] = "0x1b",
659 [0x1c] = "0x1c",
660 [0x1d] = "0x1d",
661 [0x1e] = "0x1e",
662 [0x1f] = "0x1f"
663};
664
665static char *core[8] = {
666 "Invalid/OK", "Invalid/Data",
667 "Shared/OK", "Shared/Data",
668 "Modified/OK", "Modified/Data",
669 "Exclusive/OK", "Exclusive/Data"
670};
671
672static char *causes[32] = {
673 "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
674 "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
675 "0x08", "0x09", "0x0a", "0x0b",
676 "0x0c", "0x0d", "0x0e", "0x0f",
677 "0x10", "0x11", "0x12", "0x13",
678 "0x14", "0x15", "0x16", "INTVN_WR_ERR",
679 "INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
680 "0x1c", "0x1d", "0x1e", "0x1f"
681};
682
683int malta_be_handler(struct pt_regs *regs, int is_fixup)
684{
685 /* This duplicates the handling in do_be which seems wrong */
686 int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
687
688 if (gcmp_present) {
689 unsigned long cm_error = GCMPGCB(GCMEC);
690 unsigned long cm_addr = GCMPGCB(GCMEA);
691 unsigned long cm_other = GCMPGCB(GCMEO);
692 unsigned long cause, ocause;
693 char buf[256];
694
695 cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
696 if (cause != 0) {
697 cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
698 if (cause < 16) {
699 unsigned long cca_bits = (cm_error >> 15) & 7;
700 unsigned long tr_bits = (cm_error >> 12) & 7;
701 unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
702 unsigned long stag_bits = (cm_error >> 3) & 15;
703 unsigned long sport_bits = (cm_error >> 0) & 7;
704
705 snprintf(buf, sizeof(buf),
706 "CCA=%lu TR=%s MCmd=%s STag=%lu "
707 "SPort=%lu\n",
708 cca_bits, tr[tr_bits], mcmd[mcmd_bits],
709 stag_bits, sport_bits);
710 } else {
711 /* glob state & sresp together */
712 unsigned long c3_bits = (cm_error >> 18) & 7;
713 unsigned long c2_bits = (cm_error >> 15) & 7;
714 unsigned long c1_bits = (cm_error >> 12) & 7;
715 unsigned long c0_bits = (cm_error >> 9) & 7;
716 unsigned long sc_bit = (cm_error >> 8) & 1;
717 unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
718 unsigned long sport_bits = (cm_error >> 0) & 7;
719 snprintf(buf, sizeof(buf),
720 "C3=%s C2=%s C1=%s C0=%s SC=%s "
721 "MCmd=%s SPort=%lu\n",
722 core[c3_bits], core[c2_bits],
723 core[c1_bits], core[c0_bits],
724 sc_bit ? "True" : "False",
725 mcmd[mcmd_bits], sport_bits);
726 }
727
728 ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
729 GCMP_GCB_GMEO_ERROR_2ND_SHF;
730
731 printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
732 causes[cause], buf);
733 printk("CM_ADDR =%08lx\n", cm_addr);
734 printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
735
736 /* reprime cause register */
737 GCMPGCB(GCMEC) = 0;
738 }
739 }
740
741 return retval;
1da177e4 742}
Linux 6.x block layer and io_uring tree(s)