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abc597fe SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * A small micro-assembler. It is intentionally kept simple, does only | |
7 | * support a subset of instructions, and does not try to hide pipeline | |
8 | * effects like branch delay slots. | |
9 | * | |
10 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer | |
11 | * Copyright (C) 2005, 2007 Maciej W. Rozycki | |
12 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | |
13 | * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/types.h> | |
abc597fe SH |
18 | |
19 | #include <asm/inst.h> | |
20 | #include <asm/elf.h> | |
21 | #include <asm/bugs.h> | |
22 | #include <asm/uasm.h> | |
23 | ||
24 | #define RS_MASK 0x1f | |
25 | #define RS_SH 21 | |
26 | #define RT_MASK 0x1f | |
27 | #define RT_SH 16 | |
28 | #define SCIMM_MASK 0xfffff | |
29 | #define SCIMM_SH 6 | |
30 | ||
31 | /* This macro sets the non-variable bits of an instruction. */ | |
32 | #define M(a, b, c, d, e, f) \ | |
33 | ((a) << OP_SH \ | |
34 | | (b) << RS_SH \ | |
35 | | (c) << RT_SH \ | |
36 | | (d) << RD_SH \ | |
37 | | (e) << RE_SH \ | |
38 | | (f) << FUNC_SH) | |
39 | ||
a168b8f1 LY |
40 | /* This macro sets the non-variable bits of an R6 instruction. */ |
41 | #define M6(a, b, c, d, e) \ | |
42 | ((a) << OP_SH \ | |
43 | | (b) << RS_SH \ | |
44 | | (c) << RT_SH \ | |
45 | | (d) << SIMM9_SH \ | |
46 | | (e) << FUNC_SH) | |
47 | ||
abc597fe SH |
48 | #include "uasm.c" |
49 | ||
00e06297 | 50 | static const struct insn insn_table[insn_invalid] = { |
ce807d5f DD |
51 | [insn_addiu] = {M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
52 | [insn_addu] = {M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD}, | |
53 | [insn_and] = {M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD}, | |
54 | [insn_andi] = {M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, | |
55 | [insn_bbit0] = {M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
56 | [insn_bbit1] = {M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
57 | [insn_beq] = {M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
58 | [insn_beql] = {M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
59 | [insn_bgez] = {M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM}, | |
60 | [insn_bgezl] = {M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM}, | |
dc190129 DD |
61 | [insn_bgtz] = {M(bgtz_op, 0, 0, 0, 0, 0), RS | BIMM}, |
62 | [insn_blez] = {M(blez_op, 0, 0, 0, 0, 0), RS | BIMM}, | |
ce807d5f DD |
63 | [insn_bltz] = {M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM}, |
64 | [insn_bltzl] = {M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM}, | |
65 | [insn_bne] = {M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM}, | |
dc190129 | 66 | [insn_break] = {M(spec_op, 0, 0, 0, 0, break_op), SCIMM}, |
a168b8f1 | 67 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f | 68 | [insn_cache] = {M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
a168b8f1 | 69 | #else |
ce807d5f | 70 | [insn_cache] = {M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9}, |
a168b8f1 | 71 | #endif |
ce807d5f DD |
72 | [insn_cfc1] = {M(cop1_op, cfc_op, 0, 0, 0, 0), RT | RD}, |
73 | [insn_cfcmsa] = {M(msa_op, 0, msa_cfc_op, 0, 0, msa_elm_op), RD | RE}, | |
74 | [insn_ctc1] = {M(cop1_op, ctc_op, 0, 0, 0, 0), RT | RD}, | |
75 | [insn_ctcmsa] = {M(msa_op, 0, msa_ctc_op, 0, 0, msa_elm_op), RD | RE}, | |
76 | [insn_daddiu] = {M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
77 | [insn_daddu] = {M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD}, | |
dc190129 | 78 | [insn_ddivu] = {M(spec_op, 0, 0, 0, 0, ddivu_op), RS | RT}, |
0d1d17b9 HN |
79 | [insn_ddivu_r6] = {M(spec_op, 0, 0, 0, ddivu_ddivu6_op, ddivu_op), |
80 | RS | RT | RD}, | |
ce807d5f DD |
81 | [insn_di] = {M(cop0_op, mfmc0_op, 0, 12, 0, 0), RT}, |
82 | [insn_dins] = {M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE}, | |
83 | [insn_dinsm] = {M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE}, | |
dc190129 | 84 | [insn_dinsu] = {M(spec3_op, 0, 0, 0, 0, dinsu_op), RS | RT | RD | RE}, |
ce807d5f | 85 | [insn_divu] = {M(spec_op, 0, 0, 0, 0, divu_op), RS | RT}, |
0d1d17b9 HN |
86 | [insn_divu_r6] = {M(spec_op, 0, 0, 0, divu_divu6_op, divu_op), |
87 | RS | RT | RD}, | |
ce807d5f | 88 | [insn_dmfc0] = {M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET}, |
0d1d17b9 HN |
89 | [insn_dmodu] = {M(spec_op, 0, 0, 0, ddivu_dmodu_op, ddivu_op), |
90 | RS | RT | RD}, | |
ce807d5f | 91 | [insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET}, |
dc190129 | 92 | [insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT}, |
0d1d17b9 HN |
93 | [insn_dmulu] = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op), |
94 | RS | RT | RD}, | |
ce807d5f DD |
95 | [insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE}, |
96 | [insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE}, | |
dc190129 DD |
97 | [insn_dsbh] = {M(spec3_op, 0, 0, 0, dsbh_op, dbshfl_op), RT | RD}, |
98 | [insn_dshd] = {M(spec3_op, 0, 0, 0, dshd_op, dbshfl_op), RT | RD}, | |
ce807d5f DD |
99 | [insn_dsll] = {M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE}, |
100 | [insn_dsll32] = {M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE}, | |
dc190129 | 101 | [insn_dsllv] = {M(spec_op, 0, 0, 0, 0, dsllv_op), RS | RT | RD}, |
ce807d5f | 102 | [insn_dsra] = {M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE}, |
dc190129 DD |
103 | [insn_dsra32] = {M(spec_op, 0, 0, 0, 0, dsra32_op), RT | RD | RE}, |
104 | [insn_dsrav] = {M(spec_op, 0, 0, 0, 0, dsrav_op), RS | RT | RD}, | |
ce807d5f DD |
105 | [insn_dsrl] = {M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE}, |
106 | [insn_dsrl32] = {M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE}, | |
dc190129 | 107 | [insn_dsrlv] = {M(spec_op, 0, 0, 0, 0, dsrlv_op), RS | RT | RD}, |
ce807d5f DD |
108 | [insn_dsubu] = {M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD}, |
109 | [insn_eret] = {M(cop0_op, cop_op, 0, 0, 0, eret_op), 0}, | |
110 | [insn_ext] = {M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE}, | |
111 | [insn_ins] = {M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE}, | |
112 | [insn_j] = {M(j_op, 0, 0, 0, 0, 0), JIMM}, | |
113 | [insn_jal] = {M(jal_op, 0, 0, 0, 0, 0), JIMM}, | |
114 | [insn_jalr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD}, | |
a168b8f1 | 115 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f | 116 | [insn_jr] = {M(spec_op, 0, 0, 0, 0, jr_op), RS}, |
a168b8f1 | 117 | #else |
ce807d5f | 118 | [insn_jr] = {M(spec_op, 0, 0, 0, 0, jalr_op), RS}, |
a168b8f1 | 119 | #endif |
ce807d5f | 120 | [insn_lb] = {M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
dc190129 | 121 | [insn_lbu] = {M(lbu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
ce807d5f DD |
122 | [insn_ld] = {M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
123 | [insn_lddir] = {M(lwc2_op, 0, 0, 0, lddir_op, mult_op), RS | RT | RD}, | |
124 | [insn_ldpte] = {M(lwc2_op, 0, 0, 0, ldpte_op, mult_op), RS | RD}, | |
125 | [insn_ldx] = {M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD}, | |
126 | [insn_lh] = {M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
127 | [insn_lhu] = {M(lhu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
a168b8f1 | 128 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f DD |
129 | [insn_ll] = {M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
130 | [insn_lld] = {M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
a168b8f1 | 131 | #else |
ce807d5f DD |
132 | [insn_ll] = {M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9}, |
133 | [insn_lld] = {M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9}, | |
a168b8f1 | 134 | #endif |
ce807d5f DD |
135 | [insn_lui] = {M(lui_op, 0, 0, 0, 0, 0), RT | SIMM}, |
136 | [insn_lw] = {M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
dc190129 | 137 | [insn_lwu] = {M(lwu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
ce807d5f DD |
138 | [insn_lwx] = {M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD}, |
139 | [insn_mfc0] = {M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, | |
140 | [insn_mfhc0] = {M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET}, | |
141 | [insn_mfhi] = {M(spec_op, 0, 0, 0, 0, mfhi_op), RD}, | |
142 | [insn_mflo] = {M(spec_op, 0, 0, 0, 0, mflo_op), RD}, | |
0d1d17b9 HN |
143 | [insn_modu] = {M(spec_op, 0, 0, 0, divu_modu_op, divu_op), |
144 | RS | RT | RD}, | |
dc190129 DD |
145 | [insn_movn] = {M(spec_op, 0, 0, 0, 0, movn_op), RS | RT | RD}, |
146 | [insn_movz] = {M(spec_op, 0, 0, 0, 0, movz_op), RS | RT | RD}, | |
ce807d5f DD |
147 | [insn_mtc0] = {M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, |
148 | [insn_mthc0] = {M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET}, | |
149 | [insn_mthi] = {M(spec_op, 0, 0, 0, 0, mthi_op), RS}, | |
150 | [insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS}, | |
0d1d17b9 HN |
151 | [insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op), |
152 | RS | RT | RD}, | |
6f63405c | 153 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f | 154 | [insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, |
6f63405c | 155 | #else |
ce807d5f | 156 | [insn_mul] = {M(spec_op, 0, 0, 0, mult_mul_op, mult_op), RS | RT | RD}, |
6f63405c | 157 | #endif |
dc190129 DD |
158 | [insn_multu] = {M(spec_op, 0, 0, 0, 0, multu_op), RS | RT}, |
159 | [insn_nor] = {M(spec_op, 0, 0, 0, 0, nor_op), RS | RT | RD}, | |
ce807d5f DD |
160 | [insn_or] = {M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD}, |
161 | [insn_ori] = {M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, | |
a168b8f1 | 162 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f | 163 | [insn_pref] = {M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
a168b8f1 | 164 | #else |
ce807d5f | 165 | [insn_pref] = {M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9}, |
a168b8f1 | 166 | #endif |
ce807d5f DD |
167 | [insn_rfe] = {M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0}, |
168 | [insn_rotr] = {M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE}, | |
dc190129 | 169 | [insn_sb] = {M(sb_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
a168b8f1 | 170 | #ifndef CONFIG_CPU_MIPSR6 |
ce807d5f DD |
171 | [insn_sc] = {M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
172 | [insn_scd] = {M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
a168b8f1 | 173 | #else |
ce807d5f DD |
174 | [insn_sc] = {M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9}, |
175 | [insn_scd] = {M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9}, | |
a168b8f1 | 176 | #endif |
ce807d5f | 177 | [insn_sd] = {M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
0d1d17b9 HN |
178 | [insn_seleqz] = {M(spec_op, 0, 0, 0, 0, seleqz_op), RS | RT | RD}, |
179 | [insn_selnez] = {M(spec_op, 0, 0, 0, 0, selnez_op), RS | RT | RD}, | |
dc190129 | 180 | [insn_sh] = {M(sh_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
ce807d5f DD |
181 | [insn_sll] = {M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE}, |
182 | [insn_sllv] = {M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD}, | |
183 | [insn_slt] = {M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD}, | |
dc190129 | 184 | [insn_slti] = {M(slti_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
ce807d5f DD |
185 | [insn_sltiu] = {M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, |
186 | [insn_sltu] = {M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD}, | |
187 | [insn_sra] = {M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE}, | |
ee94b90c | 188 | [insn_srav] = {M(spec_op, 0, 0, 0, 0, srav_op), RS | RT | RD}, |
ce807d5f DD |
189 | [insn_srl] = {M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE}, |
190 | [insn_srlv] = {M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD}, | |
191 | [insn_subu] = {M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD}, | |
192 | [insn_sw] = {M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM}, | |
193 | [insn_sync] = {M(spec_op, 0, 0, 0, 0, sync_op), RE}, | |
194 | [insn_syscall] = {M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, | |
195 | [insn_tlbp] = {M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0}, | |
196 | [insn_tlbr] = {M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0}, | |
197 | [insn_tlbwi] = {M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0}, | |
198 | [insn_tlbwr] = {M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0}, | |
199 | [insn_wait] = {M(cop0_op, cop_op, 0, 0, 0, wait_op), SCIMM}, | |
200 | [insn_wsbh] = {M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD}, | |
201 | [insn_xor] = {M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD}, | |
202 | [insn_xori] = {M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM}, | |
203 | [insn_yield] = {M(spec3_op, 0, 0, 0, 0, yield_op), RS | RD}, | |
abc597fe SH |
204 | }; |
205 | ||
206 | #undef M | |
207 | ||
078a55fc | 208 | static inline u32 build_bimm(s32 arg) |
abc597fe SH |
209 | { |
210 | WARN(arg > 0x1ffff || arg < -0x20000, | |
211 | KERN_WARNING "Micro-assembler field overflow\n"); | |
212 | ||
213 | WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); | |
214 | ||
215 | return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); | |
216 | } | |
217 | ||
078a55fc | 218 | static inline u32 build_jimm(u32 arg) |
abc597fe SH |
219 | { |
220 | WARN(arg & ~(JIMM_MASK << 2), | |
221 | KERN_WARNING "Micro-assembler field overflow\n"); | |
222 | ||
223 | return (arg >> 2) & JIMM_MASK; | |
224 | } | |
225 | ||
226 | /* | |
227 | * The order of opcode arguments is implicitly left to right, | |
228 | * starting with RS and ending with FUNC or IMM. | |
229 | */ | |
078a55fc | 230 | static void build_insn(u32 **buf, enum opcode opc, ...) |
abc597fe | 231 | { |
ce807d5f | 232 | const struct insn *ip; |
abc597fe SH |
233 | va_list ap; |
234 | u32 op; | |
235 | ||
ce807d5f DD |
236 | if (opc < 0 || opc >= insn_invalid || |
237 | (opc == insn_daddiu && r4k_daddiu_bug()) || | |
238 | (insn_table[opc].match == 0 && insn_table[opc].fields == 0)) | |
abc597fe SH |
239 | panic("Unsupported Micro-assembler instruction %d", opc); |
240 | ||
ce807d5f DD |
241 | ip = &insn_table[opc]; |
242 | ||
abc597fe SH |
243 | op = ip->match; |
244 | va_start(ap, opc); | |
245 | if (ip->fields & RS) | |
246 | op |= build_rs(va_arg(ap, u32)); | |
247 | if (ip->fields & RT) | |
248 | op |= build_rt(va_arg(ap, u32)); | |
249 | if (ip->fields & RD) | |
250 | op |= build_rd(va_arg(ap, u32)); | |
251 | if (ip->fields & RE) | |
252 | op |= build_re(va_arg(ap, u32)); | |
253 | if (ip->fields & SIMM) | |
254 | op |= build_simm(va_arg(ap, s32)); | |
255 | if (ip->fields & UIMM) | |
256 | op |= build_uimm(va_arg(ap, u32)); | |
257 | if (ip->fields & BIMM) | |
258 | op |= build_bimm(va_arg(ap, s32)); | |
259 | if (ip->fields & JIMM) | |
260 | op |= build_jimm(va_arg(ap, u32)); | |
261 | if (ip->fields & FUNC) | |
262 | op |= build_func(va_arg(ap, u32)); | |
263 | if (ip->fields & SET) | |
264 | op |= build_set(va_arg(ap, u32)); | |
265 | if (ip->fields & SCIMM) | |
266 | op |= build_scimm(va_arg(ap, u32)); | |
a168b8f1 LY |
267 | if (ip->fields & SIMM9) |
268 | op |= build_scimm9(va_arg(ap, u32)); | |
abc597fe SH |
269 | va_end(ap); |
270 | ||
271 | **buf = op; | |
272 | (*buf)++; | |
273 | } | |
274 | ||
078a55fc | 275 | static inline void |
abc597fe SH |
276 | __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) |
277 | { | |
278 | long laddr = (long)lab->addr; | |
279 | long raddr = (long)rel->addr; | |
280 | ||
281 | switch (rel->type) { | |
282 | case R_MIPS_PC16: | |
283 | *rel->addr |= build_bimm(laddr - (raddr + 4)); | |
284 | break; | |
285 | ||
286 | default: | |
287 | panic("Unsupported Micro-assembler relocation %d", | |
288 | rel->type); | |
289 | } | |
290 | } |