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a6a4834c SH |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * A small micro-assembler. It is intentionally kept simple, does only | |
7 | * support a subset of instructions, and does not try to hide pipeline | |
8 | * effects like branch delay slots. | |
9 | * | |
10 | * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer | |
11 | * Copyright (C) 2005, 2007 Maciej W. Rozycki | |
12 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | |
13 | * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/types.h> | |
a6a4834c SH |
18 | |
19 | #include <asm/inst.h> | |
20 | #include <asm/elf.h> | |
21 | #include <asm/bugs.h> | |
22 | #define UASM_ISA _UASM_ISA_MICROMIPS | |
23 | #include <asm/uasm.h> | |
24 | ||
25 | #define RS_MASK 0x1f | |
26 | #define RS_SH 16 | |
27 | #define RT_MASK 0x1f | |
28 | #define RT_SH 21 | |
29 | #define SCIMM_MASK 0x3ff | |
30 | #define SCIMM_SH 16 | |
31 | ||
32 | /* This macro sets the non-variable bits of an instruction. */ | |
33 | #define M(a, b, c, d, e, f) \ | |
34 | ((a) << OP_SH \ | |
35 | | (b) << RT_SH \ | |
36 | | (c) << RS_SH \ | |
37 | | (d) << RD_SH \ | |
38 | | (e) << RE_SH \ | |
39 | | (f) << FUNC_SH) | |
40 | ||
a6a4834c SH |
41 | #include "uasm.c" |
42 | ||
078a55fc | 43 | static struct insn insn_table_MM[] = { |
a6a4834c SH |
44 | { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD }, |
45 | { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, | |
46 | { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD }, | |
47 | { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, | |
48 | { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM }, | |
49 | { insn_beql, 0, 0 }, | |
50 | { insn_bgez, M(mm_pool32i_op, mm_bgez_op, 0, 0, 0, 0), RS | BIMM }, | |
51 | { insn_bgezl, 0, 0 }, | |
52 | { insn_bltz, M(mm_pool32i_op, mm_bltz_op, 0, 0, 0, 0), RS | BIMM }, | |
53 | { insn_bltzl, 0, 0 }, | |
54 | { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM }, | |
55 | { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM }, | |
56 | { insn_daddu, 0, 0 }, | |
57 | { insn_daddiu, 0, 0 }, | |
4c12a854 | 58 | { insn_divu, M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS }, |
a6a4834c SH |
59 | { insn_dmfc0, 0, 0 }, |
60 | { insn_dmtc0, 0, 0 }, | |
61 | { insn_dsll, 0, 0 }, | |
62 | { insn_dsll32, 0, 0 }, | |
63 | { insn_dsra, 0, 0 }, | |
64 | { insn_dsrl, 0, 0 }, | |
65 | { insn_dsrl32, 0, 0 }, | |
66 | { insn_drotr, 0, 0 }, | |
67 | { insn_drotr32, 0, 0 }, | |
68 | { insn_dsubu, 0, 0 }, | |
69 | { insn_eret, M(mm_pool32a_op, 0, 0, 0, mm_eret_op, mm_pool32axf_op), 0 }, | |
70 | { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE }, | |
71 | { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE }, | |
72 | { insn_j, M(mm_j32_op, 0, 0, 0, 0, 0), JIMM }, | |
73 | { insn_jal, M(mm_jal32_op, 0, 0, 0, 0, 0), JIMM }, | |
7fa22681 | 74 | { insn_jalr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS }, |
a6a4834c | 75 | { insn_jr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RS }, |
82488818 | 76 | { insn_lb, M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, |
a6a4834c | 77 | { insn_ld, 0, 0 }, |
d6b3314b | 78 | { insn_lh, M(mm_lh32_op, 0, 0, 0, 0, 0), RS | RS | SIMM }, |
a6a4834c SH |
79 | { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM }, |
80 | { insn_lld, 0, 0 }, | |
81 | { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM }, | |
82 | { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, | |
83 | { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, | |
f3ec7a23 | 84 | { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS }, |
16d21a81 | 85 | { insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS }, |
a6a4834c | 86 | { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, |
a8e897ad | 87 | { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD }, |
a6a4834c SH |
88 | { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, |
89 | { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, | |
90 | { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM }, | |
91 | { insn_rfe, 0, 0 }, | |
92 | { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM }, | |
93 | { insn_scd, 0, 0 }, | |
94 | { insn_sd, 0, 0 }, | |
95 | { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD }, | |
bef581ba | 96 | { insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD }, |
7682f9e8 | 97 | { insn_slt, M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD }, |
390363ed | 98 | { insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, |
e8ef868b | 99 | { insn_sltu, M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD }, |
a6a4834c SH |
100 | { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD }, |
101 | { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD }, | |
f31318fd | 102 | { insn_srlv, M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD }, |
a6a4834c SH |
103 | { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD }, |
104 | { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD }, | |
105 | { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, | |
729ff561 | 106 | { insn_sync, M(mm_pool32a_op, 0, 0, 0, mm_sync_op, mm_pool32axf_op), RS }, |
a6a4834c SH |
107 | { insn_tlbp, M(mm_pool32a_op, 0, 0, 0, mm_tlbp_op, mm_pool32axf_op), 0 }, |
108 | { insn_tlbr, M(mm_pool32a_op, 0, 0, 0, mm_tlbr_op, mm_pool32axf_op), 0 }, | |
109 | { insn_tlbwi, M(mm_pool32a_op, 0, 0, 0, mm_tlbwi_op, mm_pool32axf_op), 0 }, | |
110 | { insn_tlbwr, M(mm_pool32a_op, 0, 0, 0, mm_tlbwr_op, mm_pool32axf_op), 0 }, | |
53ed1389 | 111 | { insn_wait, M(mm_pool32a_op, 0, 0, 0, mm_wait_op, mm_pool32axf_op), SCIMM }, |
ab9e4fa0 | 112 | { insn_wsbh, M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS }, |
a6a4834c SH |
113 | { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD }, |
114 | { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM }, | |
115 | { insn_dins, 0, 0 }, | |
116 | { insn_dinsm, 0, 0 }, | |
117 | { insn_syscall, M(mm_pool32a_op, 0, 0, 0, mm_syscall_op, mm_pool32axf_op), SCIMM}, | |
118 | { insn_bbit0, 0, 0 }, | |
119 | { insn_bbit1, 0, 0 }, | |
120 | { insn_lwx, 0, 0 }, | |
121 | { insn_ldx, 0, 0 }, | |
122 | { insn_invalid, 0, 0 } | |
123 | }; | |
124 | ||
125 | #undef M | |
126 | ||
078a55fc | 127 | static inline u32 build_bimm(s32 arg) |
a6a4834c SH |
128 | { |
129 | WARN(arg > 0xffff || arg < -0x10000, | |
130 | KERN_WARNING "Micro-assembler field overflow\n"); | |
131 | ||
132 | WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n"); | |
133 | ||
134 | return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 1) & 0x7fff); | |
135 | } | |
136 | ||
078a55fc | 137 | static inline u32 build_jimm(u32 arg) |
a6a4834c | 138 | { |
8fe4bb98 SH |
139 | |
140 | WARN(arg & ~((JIMM_MASK << 2) | 1), | |
a6a4834c SH |
141 | KERN_WARNING "Micro-assembler field overflow\n"); |
142 | ||
143 | return (arg >> 1) & JIMM_MASK; | |
144 | } | |
145 | ||
146 | /* | |
147 | * The order of opcode arguments is implicitly left to right, | |
148 | * starting with RS and ending with FUNC or IMM. | |
149 | */ | |
078a55fc | 150 | static void build_insn(u32 **buf, enum opcode opc, ...) |
a6a4834c SH |
151 | { |
152 | struct insn *ip = NULL; | |
153 | unsigned int i; | |
154 | va_list ap; | |
155 | u32 op; | |
156 | ||
157 | for (i = 0; insn_table_MM[i].opcode != insn_invalid; i++) | |
158 | if (insn_table_MM[i].opcode == opc) { | |
159 | ip = &insn_table_MM[i]; | |
160 | break; | |
161 | } | |
162 | ||
163 | if (!ip || (opc == insn_daddiu && r4k_daddiu_bug())) | |
164 | panic("Unsupported Micro-assembler instruction %d", opc); | |
165 | ||
166 | op = ip->match; | |
167 | va_start(ap, opc); | |
168 | if (ip->fields & RS) { | |
169 | if (opc == insn_mfc0 || opc == insn_mtc0) | |
170 | op |= build_rt(va_arg(ap, u32)); | |
171 | else | |
172 | op |= build_rs(va_arg(ap, u32)); | |
173 | } | |
174 | if (ip->fields & RT) { | |
175 | if (opc == insn_mfc0 || opc == insn_mtc0) | |
176 | op |= build_rs(va_arg(ap, u32)); | |
177 | else | |
178 | op |= build_rt(va_arg(ap, u32)); | |
179 | } | |
180 | if (ip->fields & RD) | |
181 | op |= build_rd(va_arg(ap, u32)); | |
182 | if (ip->fields & RE) | |
183 | op |= build_re(va_arg(ap, u32)); | |
184 | if (ip->fields & SIMM) | |
185 | op |= build_simm(va_arg(ap, s32)); | |
186 | if (ip->fields & UIMM) | |
187 | op |= build_uimm(va_arg(ap, u32)); | |
188 | if (ip->fields & BIMM) | |
189 | op |= build_bimm(va_arg(ap, s32)); | |
190 | if (ip->fields & JIMM) | |
191 | op |= build_jimm(va_arg(ap, u32)); | |
192 | if (ip->fields & FUNC) | |
193 | op |= build_func(va_arg(ap, u32)); | |
194 | if (ip->fields & SET) | |
195 | op |= build_set(va_arg(ap, u32)); | |
196 | if (ip->fields & SCIMM) | |
197 | op |= build_scimm(va_arg(ap, u32)); | |
198 | va_end(ap); | |
199 | ||
200 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
201 | **buf = ((op & 0xffff) << 16) | (op >> 16); | |
202 | #else | |
203 | **buf = op; | |
204 | #endif | |
205 | (*buf)++; | |
206 | } | |
207 | ||
078a55fc | 208 | static inline void |
a6a4834c SH |
209 | __resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab) |
210 | { | |
211 | long laddr = (long)lab->addr; | |
212 | long raddr = (long)rel->addr; | |
213 | ||
214 | switch (rel->type) { | |
215 | case R_MIPS_PC16: | |
216 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | |
217 | *rel->addr |= (build_bimm(laddr - (raddr + 4)) << 16); | |
218 | #else | |
219 | *rel->addr |= build_bimm(laddr - (raddr + 4)); | |
220 | #endif | |
221 | break; | |
222 | ||
223 | default: | |
224 | panic("Unsupported Micro-assembler relocation %d", | |
225 | rel->type); | |
226 | } | |
227 | } |